drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c

   1 /*
   2  * Copyright 2021 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "ior.h"
  23
  24 #include <subdev/timer.h>
  25
  26 static int
  27 ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
  28 {
  29         struct nvkm_device *device = sor->disp->engine.subdev.device;
  30         const u32 soff = nv50_ior_base(sor);
  31         const u32 loff = nv50_sor_link(sor);
  32         u32 dpctrl = 0x00000000;
  33         u32 clksor = 0x00000000;
  34
  35         switch (sor->dp.bw) {
  36         case 0x06: clksor |= 0x00000000; break;
  37         case 0x0a: clksor |= 0x00040000; break;
  38         case 0x14: clksor |= 0x00080000; break;
  39         case 0x1e: clksor |= 0x000c0000; break;
  40         default:
  41                 WARN_ON(1);
  42                 return -EINVAL;
  43         }
  44
  45         dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
  46         if (sor->dp.mst)
  47                 dpctrl |= 0x40000000;
  48         if (sor->dp.ef)
  49                 dpctrl |= 0x00004000;
  50
  51         nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
  52
  53         /*XXX*/
  54         nvkm_msec(device, 40, NVKM_DELAY);
  55         nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
  56         nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
  57
  58         nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
  59         return 0;
  60 }
  61
  62 static void
  63 ga102_sor_clock(struct nvkm_ior *sor)
  64 {
  65         struct nvkm_device *device = sor->disp->engine.subdev.device;
  66         u32 div2 = 0;
  67         if (sor->asy.proto == TMDS) {
  68                 if (sor->tmds.high_speed)
  69                         div2 = 1;
  70         }
  71         nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000);
  72         nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2);
  73 }
  74
  75 static const struct nvkm_ior_func
  76 ga102_sor_hda = {
  77         .route = {
  78                 .get = gm200_sor_route_get,
  79                 .set = gm200_sor_route_set,
  80         },
  81         .state = gv100_sor_state,
  82         .power = nv50_sor_power,
  83         .clock = ga102_sor_clock,
  84         .hdmi = {
  85                 .ctrl = gv100_hdmi_ctrl,
  86                 .scdc = gm200_hdmi_scdc,
  87         },
  88         .dp = {
  89                 .lanes = { 0, 1, 2, 3 },
  90                 .links = ga102_sor_dp_links,
  91                 .power = g94_sor_dp_power,
  92                 .pattern = gm107_sor_dp_pattern,
  93                 .drive = gm200_sor_dp_drive,
  94                 .vcpi = tu102_sor_dp_vcpi,
  95                 .audio = gv100_sor_dp_audio,
  96                 .audio_sym = gv100_sor_dp_audio_sym,
  97                 .watermark = gv100_sor_dp_watermark,
  98         },
  99         .hda = {
 100                 .hpd = gf119_hda_hpd,
 101                 .eld = gf119_hda_eld,
 102                 .device_entry = gv100_hda_device_entry,
 103         },
 104 };
 105
 106 static const struct nvkm_ior_func
 107 ga102_sor = {
 108         .route = {
 109                 .get = gm200_sor_route_get,
 110                 .set = gm200_sor_route_set,
 111         },
 112         .state = gv100_sor_state,
 113         .power = nv50_sor_power,
 114         .clock = ga102_sor_clock,
 115         .hdmi = {
 116                 .ctrl = gv100_hdmi_ctrl,
 117                 .scdc = gm200_hdmi_scdc,
 118         },
 119         .dp = {
 120                 .lanes = { 0, 1, 2, 3 },
 121                 .links = ga102_sor_dp_links,
 122                 .power = g94_sor_dp_power,
 123                 .pattern = gm107_sor_dp_pattern,
 124                 .drive = gm200_sor_dp_drive,
 125                 .vcpi = tu102_sor_dp_vcpi,
 126                 .audio = gv100_sor_dp_audio,
 127                 .audio_sym = gv100_sor_dp_audio_sym,
 128                 .watermark = gv100_sor_dp_watermark,
 129         },
 130 };
 131
 132 int
 133 ga102_sor_new(struct nvkm_disp *disp, int id)
 134 {
 135         struct nvkm_device *device = disp->engine.subdev.device;
 136         u32 hda = nvkm_rd32(device, 0x08a15c);
 137         if (hda & BIT(id))
 138                 return nvkm_ior_new_(&ga102_sor_hda, disp, SOR, id);
 139         return nvkm_ior_new_(&ga102_sor, disp, SOR, id);
 140 }