drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h

   1 /* SPDX-License-Identifier: MIT */
   2 #ifndef __NVKM_DISP_DP_H__
   3 #define __NVKM_DISP_DP_H__
   4 #define nvkm_dp(p) container_of((p), struct nvkm_dp, outp)
   5 #include "outp.h"
   6
   7 #include <core/notify.h>
   8 #include <subdev/bios.h>
   9 #include <subdev/bios/dp.h>
  10
  11 struct nvkm_dp {
  12         union {
  13                 struct nvkm_outp base;
  14                 struct nvkm_outp outp;
  15         };
  16
  17         struct nvbios_dpout info;
  18         u8 version;
  19
  20         struct nvkm_i2c_aux *aux;
  21
  22         struct nvkm_notify hpd;
  23         bool present;
  24         u8 dpcd[16];
  25
  26         struct mutex mutex;
  27         struct {
  28                 atomic_t done;
  29                 bool mst;
  30         } lt;
  31 };
  32
  33 int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *,
  34                 struct nvkm_outp **);
  35
  36 /* DPCD Receiver Capabilities */
  37 #define DPCD_RC00_DPCD_REV                                              0x00000
  38 #define DPCD_RC01_MAX_LINK_RATE                                         0x00001
  39 #define DPCD_RC02                                                       0x00002
  40 #define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80
  41 #define DPCD_RC02_TPS3_SUPPORTED                                           0x40
  42 #define DPCD_RC02_MAX_LANE_COUNT                                           0x1f
  43 #define DPCD_RC03                                                       0x00003
  44 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
  45 #define DPCD_RC0E_AUX_RD_INTERVAL                                       0x0000e
  46
  47 /* DPCD Link Configuration */
  48 #define DPCD_LC00_LINK_BW_SET                                           0x00100
  49 #define DPCD_LC01                                                       0x00101
  50 #define DPCD_LC01_ENHANCED_FRAME_EN                                        0x80
  51 #define DPCD_LC01_LANE_COUNT_SET                                           0x1f
  52 #define DPCD_LC02                                                       0x00102
  53 #define DPCD_LC02_TRAINING_PATTERN_SET                                     0x03
  54 #define DPCD_LC03(l)                                            ((l) +  0x00103)
  55 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED                                 0x20
  56 #define DPCD_LC03_PRE_EMPHASIS_SET                                         0x18
  57 #define DPCD_LC03_MAX_SWING_REACHED                                        0x04
  58 #define DPCD_LC03_VOLTAGE_SWING_SET                                        0x03
  59 #define DPCD_LC0F                                                       0x0010f
  60 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED                           0x40
  61 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET                                   0x30
  62 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED                           0x04
  63 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET                                   0x03
  64 #define DPCD_LC10                                                       0x00110
  65 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED                           0x40
  66 #define DPCD_LC10_LANE3_POST_CURSOR2_SET                                   0x30
  67 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED                           0x04
  68 #define DPCD_LC10_LANE2_POST_CURSOR2_SET                                   0x03
  69
  70 /* DPCD Link/Sink Status */
  71 #define DPCD_LS02                                                       0x00202
  72 #define DPCD_LS02_LANE1_SYMBOL_LOCKED                                      0x40
  73 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE                                    0x20
  74 #define DPCD_LS02_LANE1_CR_DONE                                            0x10
  75 #define DPCD_LS02_LANE0_SYMBOL_LOCKED                                      0x04
  76 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE                                    0x02
  77 #define DPCD_LS02_LANE0_CR_DONE                                            0x01
  78 #define DPCD_LS03                                                       0x00203
  79 #define DPCD_LS03_LANE3_SYMBOL_LOCKED                                      0x40
  80 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE                                    0x20
  81 #define DPCD_LS03_LANE3_CR_DONE                                            0x10
  82 #define DPCD_LS03_LANE2_SYMBOL_LOCKED                                      0x04
  83 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE                                    0x02
  84 #define DPCD_LS03_LANE2_CR_DONE                                            0x01
  85 #define DPCD_LS04                                                       0x00204
  86 #define DPCD_LS04_LINK_STATUS_UPDATED                                      0x80
  87 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED                           0x40
  88 #define DPCD_LS04_INTERLANE_ALIGN_DONE                                     0x01
  89 #define DPCD_LS06                                                       0x00206
  90 #define DPCD_LS06_LANE1_PRE_EMPHASIS                                       0xc0
  91 #define DPCD_LS06_LANE1_VOLTAGE_SWING                                      0x30
  92 #define DPCD_LS06_LANE0_PRE_EMPHASIS                                       0x0c
  93 #define DPCD_LS06_LANE0_VOLTAGE_SWING                                      0x03
  94 #define DPCD_LS07                                                       0x00207
  95 #define DPCD_LS07_LANE3_PRE_EMPHASIS                                       0xc0
  96 #define DPCD_LS07_LANE3_VOLTAGE_SWING                                      0x30
  97 #define DPCD_LS07_LANE2_PRE_EMPHASIS                                       0x0c
  98 #define DPCD_LS07_LANE2_VOLTAGE_SWING                                      0x03
  99 #define DPCD_LS0C                                                       0x0020c
 100 #define DPCD_LS0C_LANE3_POST_CURSOR2                                       0xc0
 101 #define DPCD_LS0C_LANE2_POST_CURSOR2                                       0x30
 102 #define DPCD_LS0C_LANE1_POST_CURSOR2                                       0x0c
 103 #define DPCD_LS0C_LANE0_POST_CURSOR2                                       0x03
 104
 105 /* DPCD Sink Control */
 106 #define DPCD_SC00                                                       0x00600
 107 #define DPCD_SC00_SET_POWER                                                0x03
 108 #define DPCD_SC00_SET_POWER_D0                                             0x01
 109 #define DPCD_SC00_SET_POWER_D3                                             0x03
 110 #endif