drivers/gpu/drm/nouveau/nv84_fence.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nouveau_drv.h"
  25 #include "nouveau_dma.h"
  26 #include "nouveau_fence.h"
  27 #include "nouveau_vmm.h"
  28
  29 #include "nv50_display.h"
  30
  31 #include <nvif/push206e.h>
  32
  33 static int
  34 nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  35 {
  36         struct nvif_push *push = chan->chan.push;
  37         int ret = PUSH_WAIT(push, 8);
  38         if (ret == 0) {
  39                 PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
  40                 PUSH_NVSQ(push, NV826F,
  41                                 NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
  42                                 NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
  43                                 NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
  44                                 NV84_SUBCHAN_SEMAPHORE_TRIGGER,
  45                                 NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG,
  46                                 NV84_SUBCHAN_UEVENT, 0x00000000);
  47                 PUSH_KICK(push);
  48         }
  49         return ret;
  50 }
  51
  52 static int
  53 nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
  54 {
  55         struct nvif_push *push = chan->chan.push;
  56         int ret = PUSH_WAIT(push, 7);
  57         if (ret == 0) {
  58                 PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
  59                 PUSH_NVSQ(push, NV826F,
  60                                 NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
  61                                 NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
  62                                 NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
  63                                 NV84_SUBCHAN_SEMAPHORE_TRIGGER,
  64                                 NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
  65                 PUSH_KICK(push);
  66         }
  67         return ret;
  68 }
  69
  70 static int
  71 nv84_fence_emit(struct nouveau_fence *fence)
  72 {
  73         struct nouveau_channel *chan = fence->channel;
  74         struct nv84_fence_chan *fctx = chan->fence;
  75         u64 addr = fctx->vma->addr + chan->chid * 16;
  76
  77         return fctx->base.emit32(chan, addr, fence->base.seqno);
  78 }
  79
  80 static int
  81 nv84_fence_sync(struct nouveau_fence *fence,
  82                 struct nouveau_channel *prev, struct nouveau_channel *chan)
  83 {
  84         struct nv84_fence_chan *fctx = chan->fence;
  85         u64 addr = fctx->vma->addr + prev->chid * 16;
  86
  87         return fctx->base.sync32(chan, addr, fence->base.seqno);
  88 }
  89
  90 static u32
  91 nv84_fence_read(struct nouveau_channel *chan)
  92 {
  93         struct nv84_fence_priv *priv = chan->drm->fence;
  94         return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
  95 }
  96
  97 static void
  98 nv84_fence_context_del(struct nouveau_channel *chan)
  99 {
 100         struct nv84_fence_priv *priv = chan->drm->fence;
 101         struct nv84_fence_chan *fctx = chan->fence;
 102
 103         nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
 104         mutex_lock(&priv->mutex);
 105         nouveau_vma_del(&fctx->vma);
 106         mutex_unlock(&priv->mutex);
 107         nouveau_fence_context_del(&fctx->base);
 108         chan->fence = NULL;
 109         nouveau_fence_context_free(&fctx->base);
 110 }
 111
 112 int
 113 nv84_fence_context_new(struct nouveau_channel *chan)
 114 {
 115         struct nv84_fence_priv *priv = chan->drm->fence;
 116         struct nv84_fence_chan *fctx;
 117         int ret;
 118
 119         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 120         if (!fctx)
 121                 return -ENOMEM;
 122
 123         nouveau_fence_context_new(chan, &fctx->base);
 124         fctx->base.emit = nv84_fence_emit;
 125         fctx->base.sync = nv84_fence_sync;
 126         fctx->base.read = nv84_fence_read;
 127         fctx->base.emit32 = nv84_fence_emit32;
 128         fctx->base.sync32 = nv84_fence_sync32;
 129         fctx->base.sequence = nv84_fence_read(chan);
 130
 131         mutex_lock(&priv->mutex);
 132         ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma);
 133         mutex_unlock(&priv->mutex);
 134
 135         if (ret)
 136                 nv84_fence_context_del(chan);
 137         return ret;
 138 }
 139
 140 static bool
 141 nv84_fence_suspend(struct nouveau_drm *drm)
 142 {
 143         struct nv84_fence_priv *priv = drm->fence;
 144         int i;
 145
 146         priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan.nr));
 147         if (priv->suspend) {
 148                 for (i = 0; i < drm->chan.nr; i++)
 149                         priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
 150         }
 151
 152         return priv->suspend != NULL;
 153 }
 154
 155 static void
 156 nv84_fence_resume(struct nouveau_drm *drm)
 157 {
 158         struct nv84_fence_priv *priv = drm->fence;
 159         int i;
 160
 161         if (priv->suspend) {
 162                 for (i = 0; i < drm->chan.nr; i++)
 163                         nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
 164                 vfree(priv->suspend);
 165                 priv->suspend = NULL;
 166         }
 167 }
 168
 169 static void
 170 nv84_fence_destroy(struct nouveau_drm *drm)
 171 {
 172         struct nv84_fence_priv *priv = drm->fence;
 173         nouveau_bo_unmap(priv->bo);
 174         if (priv->bo)
 175                 nouveau_bo_unpin(priv->bo);
 176         nouveau_bo_ref(NULL, &priv->bo);
 177         drm->fence = NULL;
 178         kfree(priv);
 179 }
 180
 181 int
 182 nv84_fence_create(struct nouveau_drm *drm)
 183 {
 184         struct nv84_fence_priv *priv;
 185         u32 domain;
 186         int ret;
 187
 188         priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
 189         if (!priv)
 190                 return -ENOMEM;
 191
 192         priv->base.dtor = nv84_fence_destroy;
 193         priv->base.suspend = nv84_fence_suspend;
 194         priv->base.resume = nv84_fence_resume;
 195         priv->base.context_new = nv84_fence_context_new;
 196         priv->base.context_del = nv84_fence_context_del;
 197
 198         priv->base.uevent = true;
 199
 200         mutex_init(&priv->mutex);
 201
 202         /* Use VRAM if there is any ; otherwise fallback to system memory */
 203         domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
 204                          /*
 205                           * fences created in sysmem must be non-cached or we
 206                           * will lose CPU/GPU coherency!
 207                           */
 208                          TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
 209         ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0,
 210                              domain, 0, 0, NULL, NULL, &priv->bo);
 211         if (ret == 0) {
 212                 ret = nouveau_bo_pin(priv->bo, domain, false);
 213                 if (ret == 0) {
 214                         ret = nouveau_bo_map(priv->bo);
 215                         if (ret)
 216                                 nouveau_bo_unpin(priv->bo);
 217                 }
 218                 if (ret)
 219                         nouveau_bo_ref(NULL, &priv->bo);
 220         }
 221
 222         if (ret)
 223                 nv84_fence_destroy(drm);
 224         return ret;
 225 }