2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 #include "drm_crtc_helper.h"
30 #include "nouveau_drv.h"
31 #include "nouveau_encoder.h"
32 #include "nouveau_connector.h"
33 #include "nouveau_crtc.h"
34 #include "nouveau_hw.h"
37 int nv04_dac_output_offset(struct drm_encoder *encoder)
39 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
42 if (dcb->or & (8 | OUTPUT_C))
44 if (dcb->or & (8 | OUTPUT_B))
51 * arbitrary limit to number of sense oscillations tolerated in one sample
52 * period (observed to be at least 13 in "nvidia")
54 #define MAX_HBLANK_OSC 20
57 * arbitrary limit to number of conflicting sample pairs to tolerate at a
58 * voltage step (observed to be at least 5 in "nvidia")
60 #define MAX_SAMPLE_PAIRS 10
62 static int sample_load_twice(struct drm_device *dev, bool sense[2])
66 for (i = 0; i < 2; i++) {
67 bool sense_a, sense_b, sense_b_prime;
71 * wait for bit 0 clear -- out of hblank -- (say reg value 0x4),
72 * then wait for transition 0x4->0x5->0x4: enter hblank, leave
74 * use a 10ms timeout (guards against crtc being inactive, in
75 * which case blank state would never change)
77 if (!nouveau_wait_until(dev, 10000000, NV_PRMCIO_INP0__COLOR,
78 0x00000001, 0x00000000))
80 if (!nouveau_wait_until(dev, 10000000, NV_PRMCIO_INP0__COLOR,
81 0x00000001, 0x00000001))
83 if (!nouveau_wait_until(dev, 10000000, NV_PRMCIO_INP0__COLOR,
84 0x00000001, 0x00000000))
88 /* when level triggers, sense is _LO_ */
89 sense_a = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
91 /* take another reading until it agrees with sense_a... */
94 sense_b = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
95 if (sense_a != sense_b) {
97 nv_rd08(dev, NV_PRMCIO_INP0) & 0x10;
98 if (sense_b == sense_b_prime) {
99 /* ... unless two consecutive subsequent
100 * samples agree; sense_a is replaced */
102 /* force mis-match so we loop */
106 } while ((sense_a != sense_b) && ++j < MAX_HBLANK_OSC);
108 if (j == MAX_HBLANK_OSC)
109 /* with so much oscillation, default to sense:LO */
118 static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
119 struct drm_connector *connector)
121 struct drm_device *dev = encoder->dev;
122 uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
123 uint8_t saved_palette0[3], saved_palette_mask;
124 uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
130 * for this detection to work, there needs to be a mode set up on the
131 * CRTC. this is presumed to be the case
134 if (nv_two_heads(dev))
135 /* only implemented for head A for now */
138 saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX);
139 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80);
141 saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX);
142 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20);
144 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL);
145 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL,
146 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
150 saved_pi = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX);
151 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX,
152 saved_pi & ~(0x80 | MASK(NV_CIO_CRE_PIXEL_FORMAT)));
153 saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
154 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
156 nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
157 for (i = 0; i < 3; i++)
158 saved_palette0[i] = nv_rd08(dev, NV_PRMDIO_PALETTE_DATA);
159 saved_palette_mask = nv_rd08(dev, NV_PRMDIO_PIXEL_MASK);
160 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, 0);
162 saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
163 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,
164 (saved_rgen_ctrl & ~(NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
165 NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM)) |
166 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON);
168 blue = 8; /* start of test range */
173 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
174 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0);
175 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0);
176 /* testing blue won't find monochrome monitors. I don't care */
177 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, blue);
180 /* take sample pairs until both samples in the pair agree */
182 if (sample_load_twice(dev, sense_pair))
184 } while ((sense_pair[0] != sense_pair[1]) &&
185 ++i < MAX_SAMPLE_PAIRS);
187 if (i == MAX_SAMPLE_PAIRS)
188 /* too much oscillation defaults to LO */
191 sense = sense_pair[0];
194 * if sense goes LO before blue ramps to 0x18, monitor is not connected.
195 * ergo, if blue gets to 0x18, monitor must be connected
197 } while (++blue < 0x18 && sense);
200 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
201 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);
202 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
203 for (i = 0; i < 3; i++)
204 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
205 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);
206 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
207 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
208 NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1);
209 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
212 NV_INFO(dev, "Load detected on head A\n");
213 return connector_status_connected;
216 return connector_status_disconnected;
219 uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
221 struct drm_device *dev = encoder->dev;
222 struct drm_nouveau_private *dev_priv = dev->dev_private;
223 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
224 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
225 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
226 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
227 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput;
230 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
231 if (dcb->type == OUTPUT_TV) {
232 testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0);
234 if (dev_priv->vbios.tvdactestval)
235 testval = dev_priv->vbios.tvdactestval;
237 testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
239 if (dev_priv->vbios.dactestval)
240 testval = dev_priv->vbios.dactestval;
243 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
244 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
245 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
247 saved_powerctrl_2 = nvReadMC(dev, NV_PBUS_POWERCTRL_2);
249 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
250 if (regoffset == 0x68) {
251 saved_powerctrl_4 = nvReadMC(dev, NV_PBUS_POWERCTRL_4);
252 nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
255 saved_gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
256 saved_gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
258 gpio->set(dev, DCB_GPIO_TVDAC1, dcb->type == OUTPUT_TV);
259 gpio->set(dev, DCB_GPIO_TVDAC0, dcb->type == OUTPUT_TV);
263 saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
264 head = (saved_routput & 0x100) >> 8;
266 /* if there's a spare crtc, using it will minimise flicker */
267 if (!(NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX) & 0xC0))
270 /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
271 routput = (saved_routput & 0xfffffece) | head << 8;
273 if (dev_priv->card_type >= NV_40) {
274 if (dcb->type == OUTPUT_TV)
275 routput |= 0x1a << 16;
277 routput &= ~(0x1a << 16);
280 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput);
283 temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
284 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, temp | 1);
286 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA,
287 NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK | testval);
288 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
289 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
290 temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
293 sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
294 /* do it again just in case it's a residual current */
295 sample &= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
297 temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL);
298 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL,
299 temp & ~NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED);
300 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA, 0);
302 /* bios does something more complex for restoring, but I think this is good enough */
303 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);
304 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
305 if (regoffset == 0x68)
306 nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
307 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
309 gpio->set(dev, DCB_GPIO_TVDAC1, saved_gpio1);
310 gpio->set(dev, DCB_GPIO_TVDAC0, saved_gpio0);
315 static enum drm_connector_status
316 nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
318 struct drm_device *dev = encoder->dev;
319 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
321 if (nv04_dac_in_use(encoder))
322 return connector_status_disconnected;
324 if (nv17_dac_sample_load(encoder) &
325 NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) {
326 NV_INFO(dev, "Load detected on output %c\n",
328 return connector_status_connected;
330 return connector_status_disconnected;
334 static bool nv04_dac_mode_fixup(struct drm_encoder *encoder,
335 struct drm_display_mode *mode,
336 struct drm_display_mode *adjusted_mode)
338 if (nv04_dac_in_use(encoder))
344 static void nv04_dac_prepare(struct drm_encoder *encoder)
346 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
347 struct drm_device *dev = encoder->dev;
348 struct drm_nouveau_private *dev_priv = dev->dev_private;
349 int head = nouveau_crtc(encoder->crtc)->index;
350 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
352 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
354 nv04_dfp_disable(dev, head);
355 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] = 0;
358 static void nv04_dac_mode_set(struct drm_encoder *encoder,
359 struct drm_display_mode *mode,
360 struct drm_display_mode *adjusted_mode)
362 struct drm_device *dev = encoder->dev;
363 struct drm_nouveau_private *dev_priv = dev->dev_private;
364 int head = nouveau_crtc(encoder->crtc)->index;
366 if (nv_gf4_disp_arch(dev)) {
367 struct drm_encoder *rebind;
368 uint32_t dac_offset = nv04_dac_output_offset(encoder);
371 /* bit 16-19 are bits that are set on some G70 cards,
372 * but don't seem to have much effect */
373 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset,
374 head << 8 | NV_PRAMDAC_DACCLK_SEL_DACCLK);
375 /* force any other vga encoders to bind to the other crtc */
376 list_for_each_entry(rebind, &dev->mode_config.encoder_list, head) {
377 if (rebind == encoder
378 || nouveau_encoder(rebind)->dcb->type != OUTPUT_ANALOG)
381 dac_offset = nv04_dac_output_offset(rebind);
382 otherdac = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset);
383 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset,
384 (otherdac & ~0x0100) | (head ^ 1) << 8);
388 /* This could use refinement for flatpanels, but it should work this way */
389 if (dev_priv->chipset < 0x44)
390 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
392 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
395 static void nv04_dac_commit(struct drm_encoder *encoder)
397 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
398 struct drm_device *dev = encoder->dev;
399 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
400 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
402 helper->dpms(encoder, DRM_MODE_DPMS_ON);
404 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
405 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
406 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
409 void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable)
411 struct drm_device *dev = encoder->dev;
412 struct drm_nouveau_private *dev_priv = dev->dev_private;
413 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
415 if (nv_gf4_disp_arch(dev)) {
416 uint32_t *dac_users = &dev_priv->dac_users[ffs(dcb->or) - 1];
417 int dacclk_off = NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder);
418 uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off);
421 *dac_users |= 1 << dcb->index;
422 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk | NV_PRAMDAC_DACCLK_SEL_DACCLK);
425 *dac_users &= ~(1 << dcb->index);
427 NVWriteRAMDAC(dev, 0, dacclk_off,
428 dacclk & ~NV_PRAMDAC_DACCLK_SEL_DACCLK);
433 /* Check if the DAC corresponding to 'encoder' is being used by
435 bool nv04_dac_in_use(struct drm_encoder *encoder)
437 struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
438 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
440 return nv_gf4_disp_arch(encoder->dev) &&
441 (dev_priv->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
444 static void nv04_dac_dpms(struct drm_encoder *encoder, int mode)
446 struct drm_device *dev = encoder->dev;
447 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
449 if (nv_encoder->last_dpms == mode)
451 nv_encoder->last_dpms = mode;
453 NV_INFO(dev, "Setting dpms mode %d on vga encoder (output %d)\n",
454 mode, nv_encoder->dcb->index);
456 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
459 static void nv04_dac_save(struct drm_encoder *encoder)
461 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
462 struct drm_device *dev = encoder->dev;
464 if (nv_gf4_disp_arch(dev))
465 nv_encoder->restore.output = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
466 nv04_dac_output_offset(encoder));
469 static void nv04_dac_restore(struct drm_encoder *encoder)
471 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
472 struct drm_device *dev = encoder->dev;
474 if (nv_gf4_disp_arch(dev))
475 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder),
476 nv_encoder->restore.output);
478 nv_encoder->last_dpms = NV_DPMS_CLEARED;
481 static void nv04_dac_destroy(struct drm_encoder *encoder)
483 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
485 NV_DEBUG_KMS(encoder->dev, "\n");
487 drm_encoder_cleanup(encoder);
491 static const struct drm_encoder_helper_funcs nv04_dac_helper_funcs = {
492 .dpms = nv04_dac_dpms,
493 .save = nv04_dac_save,
494 .restore = nv04_dac_restore,
495 .mode_fixup = nv04_dac_mode_fixup,
496 .prepare = nv04_dac_prepare,
497 .commit = nv04_dac_commit,
498 .mode_set = nv04_dac_mode_set,
499 .detect = nv04_dac_detect
502 static const struct drm_encoder_helper_funcs nv17_dac_helper_funcs = {
503 .dpms = nv04_dac_dpms,
504 .save = nv04_dac_save,
505 .restore = nv04_dac_restore,
506 .mode_fixup = nv04_dac_mode_fixup,
507 .prepare = nv04_dac_prepare,
508 .commit = nv04_dac_commit,
509 .mode_set = nv04_dac_mode_set,
510 .detect = nv17_dac_detect
513 static const struct drm_encoder_funcs nv04_dac_funcs = {
514 .destroy = nv04_dac_destroy,
518 nv04_dac_create(struct drm_connector *connector, struct dcb_entry *entry)
520 const struct drm_encoder_helper_funcs *helper;
521 struct nouveau_encoder *nv_encoder = NULL;
522 struct drm_device *dev = connector->dev;
523 struct drm_encoder *encoder;
525 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
529 encoder = to_drm_encoder(nv_encoder);
531 nv_encoder->dcb = entry;
532 nv_encoder->or = ffs(entry->or) - 1;
534 if (nv_gf4_disp_arch(dev))
535 helper = &nv17_dac_helper_funcs;
537 helper = &nv04_dac_helper_funcs;
539 drm_encoder_init(dev, encoder, &nv04_dac_funcs, DRM_MODE_ENCODER_DAC);
540 drm_encoder_helper_add(encoder, helper);
542 encoder->possible_crtcs = entry->heads;
543 encoder->possible_clones = 0;
545 drm_mode_connector_attach_encoder(connector, encoder);