1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA,
4 * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA,
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "nouveau_drv.h"
26 #include "nouveau_gem.h"
27 #include "nouveau_mem.h"
28 #include "nouveau_ttm.h"
30 #include <drm/drm_legacy.h>
32 #include <core/tegra.h>
35 nouveau_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
41 nouveau_manager_fini(struct ttm_mem_type_manager *man)
47 nouveau_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *reg)
53 nouveau_manager_debug(struct ttm_mem_type_manager *man,
54 struct drm_printer *printer)
59 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
60 struct ttm_buffer_object *bo,
61 const struct ttm_place *place,
62 struct ttm_mem_reg *reg)
64 struct nouveau_bo *nvbo = nouveau_bo(bo);
65 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
68 if (drm->client.device.info.ram_size == 0)
71 ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
75 ret = nouveau_mem_vram(reg, nvbo->contig, nvbo->page);
84 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
85 .init = nouveau_manager_init,
86 .takedown = nouveau_manager_fini,
87 .get_node = nouveau_vram_manager_new,
88 .put_node = nouveau_manager_del,
89 .debug = nouveau_manager_debug,
93 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
94 struct ttm_buffer_object *bo,
95 const struct ttm_place *place,
96 struct ttm_mem_reg *reg)
98 struct nouveau_bo *nvbo = nouveau_bo(bo);
99 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
102 ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
110 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
111 .init = nouveau_manager_init,
112 .takedown = nouveau_manager_fini,
113 .get_node = nouveau_gart_manager_new,
114 .put_node = nouveau_manager_del,
115 .debug = nouveau_manager_debug
119 nv04_gart_manager_new(struct ttm_mem_type_manager *man,
120 struct ttm_buffer_object *bo,
121 const struct ttm_place *place,
122 struct ttm_mem_reg *reg)
124 struct nouveau_bo *nvbo = nouveau_bo(bo);
125 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
126 struct nouveau_mem *mem;
129 ret = nouveau_mem_new(&drm->master, nvbo->kind, nvbo->comp, reg);
130 mem = nouveau_mem(reg);
134 ret = nvif_vmm_get(&mem->cli->vmm.vmm, PTES, false, 12, 0,
135 reg->num_pages << PAGE_SHIFT, &mem->vma[0]);
137 nouveau_mem_del(reg);
141 reg->start = mem->vma[0].addr >> PAGE_SHIFT;
145 const struct ttm_mem_type_manager_func nv04_gart_manager = {
146 .init = nouveau_manager_init,
147 .takedown = nouveau_manager_fini,
148 .get_node = nv04_gart_manager_new,
149 .put_node = nouveau_manager_del,
150 .debug = nouveau_manager_debug
154 nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
156 struct drm_file *file_priv = filp->private_data;
157 struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
159 return ttm_bo_mmap(filp, vma, &drm->ttm.bdev);
163 nouveau_ttm_init_host(struct nouveau_drm *drm, u8 kind)
165 struct nvif_mmu *mmu = &drm->client.mmu;
168 typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE |
169 kind | NVIF_MEM_COHERENT);
173 drm->ttm.type_host[!!kind] = typei;
175 typei = nvif_mmu_type(mmu, NVIF_MEM_HOST | NVIF_MEM_MAPPABLE | kind);
179 drm->ttm.type_ncoh[!!kind] = typei;
184 nouveau_ttm_init(struct nouveau_drm *drm)
186 struct nvkm_device *device = nvxx_device(&drm->client.device);
187 struct nvkm_pci *pci = device->pci;
188 struct nvif_mmu *mmu = &drm->client.mmu;
189 struct drm_device *dev = drm->dev;
192 ret = nouveau_ttm_init_host(drm, 0);
196 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
197 drm->client.device.info.chipset != 0x50) {
198 ret = nouveau_ttm_init_host(drm, NVIF_MEM_KIND);
203 if (drm->client.device.info.platform != NV_DEVICE_INFO_V0_SOC &&
204 drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
205 typei = nvif_mmu_type(mmu, NVIF_MEM_VRAM | NVIF_MEM_MAPPABLE |
212 drm->ttm.type_vram = typei;
214 drm->ttm.type_vram = -1;
217 if (pci && pci->agp.bridge) {
218 drm->agp.bridge = pci->agp.bridge;
219 drm->agp.base = pci->agp.base;
220 drm->agp.size = pci->agp.size;
221 drm->agp.cma = pci->agp.cma;
224 ret = ttm_bo_device_init(&drm->ttm.bdev,
226 dev->anon_inode->i_mapping,
227 dev->vma_offset_manager,
228 drm->client.mmu.dmabits <= 32 ? true : false);
230 NV_ERROR(drm, "error initialising bo driver, %d\n", ret);
235 drm->gem.vram_available = drm->client.device.info.ram_user;
237 arch_io_reserve_memtype_wc(device->func->resource_addr(device, 1),
238 device->func->resource_size(device, 1));
240 ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
241 drm->gem.vram_available >> PAGE_SHIFT);
243 NV_ERROR(drm, "VRAM mm init failed, %d\n", ret);
247 drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1),
248 device->func->resource_size(device, 1));
251 if (!drm->agp.bridge) {
252 drm->gem.gart_available = drm->client.vmm.vmm.limit;
254 drm->gem.gart_available = drm->agp.size;
257 ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT,
258 drm->gem.gart_available >> PAGE_SHIFT);
260 NV_ERROR(drm, "GART mm init failed, %d\n", ret);
264 NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20));
265 NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20));
270 nouveau_ttm_fini(struct nouveau_drm *drm)
272 struct nvkm_device *device = nvxx_device(&drm->client.device);
274 ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM);
275 ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT);
277 ttm_bo_device_release(&drm->ttm.bdev);
279 arch_phys_wc_del(drm->ttm.mtrr);
281 arch_io_free_memtype_wc(device->func->resource_addr(device, 1),
282 device->func->resource_size(device, 1));