2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
23 #include <linux/clk.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
28 #include <linux/reset.h>
29 #include <linux/regulator/consumer.h>
30 #include <soc/tegra/pmc.h>
32 #include "nouveau_drm.h"
33 #include "nouveau_platform.h"
35 static int nouveau_platform_power_up(struct nouveau_platform_gpu *gpu)
39 err = regulator_enable(gpu->vdd);
43 err = clk_prepare_enable(gpu->clk);
46 err = clk_prepare_enable(gpu->clk_pwr);
49 clk_set_rate(gpu->clk_pwr, 204000000);
52 reset_control_assert(gpu->rst);
55 err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D);
60 reset_control_deassert(gpu->rst);
66 clk_disable_unprepare(gpu->clk_pwr);
68 clk_disable_unprepare(gpu->clk);
70 regulator_disable(gpu->vdd);
75 static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu)
79 reset_control_assert(gpu->rst);
82 clk_disable_unprepare(gpu->clk_pwr);
83 clk_disable_unprepare(gpu->clk);
86 err = regulator_disable(gpu->vdd);
93 static int nouveau_platform_probe(struct platform_device *pdev)
95 struct nouveau_platform_gpu *gpu;
96 struct nouveau_platform_device *device;
97 struct drm_device *drm;
100 gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL);
104 gpu->vdd = devm_regulator_get(&pdev->dev, "vdd");
105 if (IS_ERR(gpu->vdd))
106 return PTR_ERR(gpu->vdd);
108 gpu->rst = devm_reset_control_get(&pdev->dev, "gpu");
109 if (IS_ERR(gpu->rst))
110 return PTR_ERR(gpu->rst);
112 gpu->clk = devm_clk_get(&pdev->dev, "gpu");
113 if (IS_ERR(gpu->clk))
114 return PTR_ERR(gpu->clk);
116 gpu->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
117 if (IS_ERR(gpu->clk_pwr))
118 return PTR_ERR(gpu->clk_pwr);
120 err = nouveau_platform_power_up(gpu);
124 drm = nouveau_platform_device_create(pdev, &device);
132 err = drm_dev_register(drm, 0);
144 nouveau_platform_power_down(gpu);
149 static int nouveau_platform_remove(struct platform_device *pdev)
151 struct drm_device *drm_dev = platform_get_drvdata(pdev);
152 struct nouveau_drm *drm = nouveau_drm(drm_dev);
153 struct nouveau_device *device = nvkm_device(&drm->device);
154 struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu;
156 nouveau_drm_device_remove(drm_dev);
158 return nouveau_platform_power_down(gpu);
161 #if IS_ENABLED(CONFIG_OF)
162 static const struct of_device_id nouveau_platform_match[] = {
163 { .compatible = "nvidia,gk20a" },
167 MODULE_DEVICE_TABLE(of, nouveau_platform_match);
170 struct platform_driver nouveau_platform_driver = {
173 .of_match_table = of_match_ptr(nouveau_platform_match),
175 .probe = nouveau_platform_probe,
176 .remove = nouveau_platform_remove,
179 module_platform_driver(nouveau_platform_driver);
181 MODULE_AUTHOR(DRIVER_AUTHOR);
182 MODULE_DESCRIPTION(DRIVER_DESC);
183 MODULE_LICENSE("GPL and additional rights");