2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/console.h>
26 #include <linux/module.h>
30 #include "drm_crtc_helper.h"
31 #include "nouveau_drv.h"
32 #include "nouveau_hw.h"
33 #include "nouveau_fb.h"
34 #include "nouveau_fbcon.h"
35 #include "nouveau_pm.h"
36 #include "nv50_display.h"
38 #include "drm_pciids.h"
40 MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
41 int nouveau_agpmode = -1;
42 module_param_named(agpmode, nouveau_agpmode, int, 0400);
44 MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
45 int nouveau_modeset = -1;
46 module_param_named(modeset, nouveau_modeset, int, 0400);
48 MODULE_PARM_DESC(vbios, "Override default VBIOS location");
50 module_param_named(vbios, nouveau_vbios, charp, 0400);
52 MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
53 int nouveau_vram_pushbuf;
54 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
56 MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
57 int nouveau_vram_notify = 0;
58 module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
60 MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
61 char *nouveau_vram_type;
62 module_param_named(vram_type, nouveau_vram_type, charp, 0400);
64 MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
65 int nouveau_duallink = 1;
66 module_param_named(duallink, nouveau_duallink, int, 0400);
68 MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
69 int nouveau_uscript_lvds = -1;
70 module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
72 MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
73 int nouveau_uscript_tmds = -1;
74 module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
76 MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
77 int nouveau_ignorelid = 0;
78 module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
80 MODULE_PARM_DESC(noaccel, "Disable all acceleration");
81 int nouveau_noaccel = -1;
82 module_param_named(noaccel, nouveau_noaccel, int, 0400);
84 MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
85 int nouveau_nofbaccel = 0;
86 module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
88 MODULE_PARM_DESC(force_post, "Force POST");
89 int nouveau_force_post = 0;
90 module_param_named(force_post, nouveau_force_post, int, 0400);
92 MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
93 int nouveau_override_conntype = 0;
94 module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
96 MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
97 int nouveau_tv_disable = 0;
98 module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
100 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
101 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
102 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
104 "\t\t*NOTE* Ignored for cards with external TV encoders.");
105 char *nouveau_tv_norm;
106 module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
108 MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
109 "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
110 "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
111 "\t\t0x100 vgaattr, 0x200 EVO (G80+)");
112 int nouveau_reg_debug;
113 module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
115 MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
116 char *nouveau_perflvl;
117 module_param_named(perflvl, nouveau_perflvl, charp, 0400);
119 MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
120 int nouveau_perflvl_wr;
121 module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
123 MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
125 module_param_named(msi, nouveau_msi, int, 0400);
127 MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
129 module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
131 MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
132 int nouveau_mxmdcb = 1;
133 module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
135 int nouveau_fbpercrtc;
137 module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
140 static struct pci_device_id pciidlist[] = {
142 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
143 .class = PCI_BASE_CLASS_DISPLAY << 16,
144 .class_mask = 0xff << 16,
147 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
148 .class = PCI_BASE_CLASS_DISPLAY << 16,
149 .class_mask = 0xff << 16,
154 MODULE_DEVICE_TABLE(pci, pciidlist);
156 static struct drm_driver driver;
159 nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
161 return drm_get_pci_dev(pdev, ent, &driver);
165 nouveau_pci_remove(struct pci_dev *pdev)
167 struct drm_device *dev = pci_get_drvdata(pdev);
173 nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
175 struct drm_device *dev = pci_get_drvdata(pdev);
176 struct drm_nouveau_private *dev_priv = dev->dev_private;
177 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
178 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
179 struct nouveau_channel *chan;
180 struct drm_crtc *crtc;
183 if (pm_state.event == PM_EVENT_PRETHAW)
186 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
189 NV_INFO(dev, "Disabling display...\n");
190 nouveau_display_fini(dev);
192 NV_INFO(dev, "Disabling fbcon...\n");
193 nouveau_fbcon_set_suspend(dev, 1);
195 NV_INFO(dev, "Unpinning framebuffer(s)...\n");
196 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
197 struct nouveau_framebuffer *nouveau_fb;
199 nouveau_fb = nouveau_framebuffer(crtc->fb);
200 if (!nouveau_fb || !nouveau_fb->nvbo)
203 nouveau_bo_unpin(nouveau_fb->nvbo);
206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
207 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
209 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
210 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
213 NV_INFO(dev, "Evicting buffers...\n");
214 ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
216 NV_INFO(dev, "Idling channels...\n");
217 for (i = 0; i < pfifo->channels; i++) {
218 chan = dev_priv->channels.ptr[i];
220 if (chan && chan->pushbuf_bo)
221 nouveau_channel_idle(chan);
224 if (dev_priv->card_type < NV_50) {
225 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
226 nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
227 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
228 nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
230 pfifo->unload_context(dev);
232 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
233 if (!dev_priv->eng[e])
236 ret = dev_priv->eng[e]->fini(dev, e, true);
238 NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
243 ret = pinstmem->suspend(dev);
245 NV_ERROR(dev, "... failed: %d\n", ret);
249 NV_INFO(dev, "Suspending GPU objects...\n");
250 ret = nouveau_gpuobj_suspend(dev);
252 NV_ERROR(dev, "... failed: %d\n", ret);
253 pinstmem->resume(dev);
257 NV_INFO(dev, "And we're gone!\n");
258 pci_save_state(pdev);
259 if (pm_state.event == PM_EVENT_SUSPEND) {
260 pci_disable_device(pdev);
261 pci_set_power_state(pdev, PCI_D3hot);
267 NV_INFO(dev, "Re-enabling acceleration..\n");
268 for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
269 if (dev_priv->eng[e])
270 dev_priv->eng[e]->init(dev, e);
272 if (dev_priv->card_type < NV_50) {
273 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
274 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
275 nv_wr32(dev, NV03_PFIFO_CACHES, 1);
281 nouveau_pci_resume(struct pci_dev *pdev)
283 struct drm_device *dev = pci_get_drvdata(pdev);
284 struct drm_nouveau_private *dev_priv = dev->dev_private;
285 struct nouveau_engine *engine = &dev_priv->engine;
286 struct drm_crtc *crtc;
289 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
292 NV_INFO(dev, "We're back, enabling device...\n");
293 pci_set_power_state(pdev, PCI_D0);
294 pci_restore_state(pdev);
295 if (pci_enable_device(pdev))
297 pci_set_master(dev->pdev);
299 /* Make sure the AGP controller is in a consistent state */
300 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
301 nouveau_mem_reset_agp(dev);
303 /* Make the CRTCs accessible */
304 engine->display.early_init(dev);
306 NV_INFO(dev, "POSTing device...\n");
307 ret = nouveau_run_vbios_init(dev);
311 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
312 ret = nouveau_mem_init_agp(dev);
314 NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
319 NV_INFO(dev, "Restoring GPU objects...\n");
320 nouveau_gpuobj_resume(dev);
322 NV_INFO(dev, "Reinitialising engines...\n");
323 engine->instmem.resume(dev);
324 engine->mc.init(dev);
325 engine->timer.init(dev);
326 engine->fb.init(dev);
327 for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
328 if (dev_priv->eng[i])
329 dev_priv->eng[i]->init(dev, i);
331 engine->fifo.init(dev);
333 nouveau_irq_postinstall(dev);
335 /* Re-write SKIPS, they'll have been lost over the suspend */
336 if (nouveau_vram_pushbuf) {
337 struct nouveau_channel *chan;
340 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
341 chan = dev_priv->channels.ptr[i];
342 if (!chan || !chan->pushbuf_bo)
345 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
346 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
350 nouveau_pm_resume(dev);
352 NV_INFO(dev, "Restoring mode...\n");
353 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
354 struct nouveau_framebuffer *nouveau_fb;
356 nouveau_fb = nouveau_framebuffer(crtc->fb);
357 if (!nouveau_fb || !nouveau_fb->nvbo)
360 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
364 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
366 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
368 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
370 NV_ERROR(dev, "Could not pin/map cursor.\n");
373 nouveau_fbcon_set_suspend(dev, 0);
374 nouveau_fbcon_zfill_all(dev);
376 nouveau_display_init(dev);
378 /* Force CLUT to get re-loaded during modeset */
379 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
380 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
382 nv_crtc->lut.depth = 0;
385 drm_helper_resume_force_mode(dev);
387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
388 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
389 u32 offset = nv_crtc->cursor.nvbo->bo.offset;
391 nv_crtc->cursor.set_offset(nv_crtc, offset);
392 nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
393 nv_crtc->cursor_saved_y);
399 static const struct file_operations nouveau_driver_fops = {
400 .owner = THIS_MODULE,
402 .release = drm_release,
403 .unlocked_ioctl = drm_ioctl,
404 .mmap = nouveau_ttm_mmap,
406 .fasync = drm_fasync,
408 #if defined(CONFIG_COMPAT)
409 .compat_ioctl = nouveau_compat_ioctl,
411 .llseek = noop_llseek,
414 static struct drm_driver driver = {
416 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
417 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
418 DRIVER_MODESET | DRIVER_PRIME,
419 .load = nouveau_load,
420 .firstopen = nouveau_firstopen,
421 .lastclose = nouveau_lastclose,
422 .unload = nouveau_unload,
423 .open = nouveau_open,
424 .preclose = nouveau_preclose,
425 .postclose = nouveau_postclose,
426 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
427 .debugfs_init = nouveau_debugfs_init,
428 .debugfs_cleanup = nouveau_debugfs_takedown,
430 .irq_preinstall = nouveau_irq_preinstall,
431 .irq_postinstall = nouveau_irq_postinstall,
432 .irq_uninstall = nouveau_irq_uninstall,
433 .irq_handler = nouveau_irq_handler,
434 .get_vblank_counter = drm_vblank_count,
435 .enable_vblank = nouveau_vblank_enable,
436 .disable_vblank = nouveau_vblank_disable,
437 .reclaim_buffers = drm_core_reclaim_buffers,
438 .ioctls = nouveau_ioctls,
439 .fops = &nouveau_driver_fops,
441 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
442 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
443 .gem_prime_export = nouveau_gem_prime_export,
444 .gem_prime_import = nouveau_gem_prime_import,
446 .gem_init_object = nouveau_gem_object_new,
447 .gem_free_object = nouveau_gem_object_del,
448 .gem_open_object = nouveau_gem_object_open,
449 .gem_close_object = nouveau_gem_object_close,
451 .dumb_create = nouveau_display_dumb_create,
452 .dumb_map_offset = nouveau_display_dumb_map_offset,
453 .dumb_destroy = nouveau_display_dumb_destroy,
458 .date = GIT_REVISION,
462 .major = DRIVER_MAJOR,
463 .minor = DRIVER_MINOR,
464 .patchlevel = DRIVER_PATCHLEVEL,
467 static struct pci_driver nouveau_pci_driver = {
469 .id_table = pciidlist,
470 .probe = nouveau_pci_probe,
471 .remove = nouveau_pci_remove,
472 .suspend = nouveau_pci_suspend,
473 .resume = nouveau_pci_resume
476 static int __init nouveau_init(void)
478 driver.num_ioctls = nouveau_max_ioctl;
480 if (nouveau_modeset == -1) {
481 #ifdef CONFIG_VGA_CONSOLE
482 if (vgacon_text_force())
489 if (!nouveau_modeset)
492 nouveau_register_dsm_handler();
493 return drm_pci_init(&driver, &nouveau_pci_driver);
496 static void __exit nouveau_exit(void)
498 if (!nouveau_modeset)
501 drm_pci_exit(&driver, &nouveau_pci_driver);
502 nouveau_unregister_dsm_handler();
505 module_init(nouveau_init);
506 module_exit(nouveau_exit);
508 MODULE_AUTHOR(DRIVER_AUTHOR);
509 MODULE_DESCRIPTION(DRIVER_DESC);
510 MODULE_LICENSE("GPL and additional rights");