2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef __NOUVEAU_DMA_H__
28 #define __NOUVEAU_DMA_H__
30 #include "nouveau_bo.h"
31 #include "nouveau_chan.h"
33 int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
34 void nv50_dma_push(struct nouveau_channel *, u64 addr, int length);
37 * There's a hw race condition where you can't jump to your PUT offset,
38 * to avoid this we jump to offset + SKIPS and fill the difference with
41 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
42 * a SKIPS value of 8. Lets assume that the race condition is to do
43 * with writing into the fetch area, we configure a fetch size of 128
44 * bytes so we need a larger SKIPS value.
46 #define NOUVEAU_DMA_SKIPS (128 / 4)
48 /* Hardcoded object assignments to subchannels (subchannel id). */
53 NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
54 NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */
57 /* Object handles - for stuff that's doesn't use handle == oclass. */
61 NvNotify0 = 0x80000006,
63 NvEvoSema0 = 0x80000010,
64 NvEvoSema1 = 0x80000011,
67 #define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
68 #define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
69 #define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
70 #define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
71 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
72 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
73 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
74 #define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
75 #define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
76 #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
78 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
79 #define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
80 #define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
81 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
82 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
84 static __must_check inline int
85 RING_SPACE(struct nouveau_channel *chan, int size)
89 ret = nouveau_dma_wait(chan, 1, size);
93 chan->dma.free -= size;
98 OUT_RING(struct nouveau_channel *chan, int data)
100 nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
104 BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
106 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
110 BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
112 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
116 BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
118 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
121 #define WRITE_PUT(val) do { \
123 nouveau_bo_rd32(chan->push.buffer, 0); \
124 nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\
128 FIRE_RING(struct nouveau_channel *chan)
130 if (chan->dma.cur == chan->dma.put)
132 chan->accel_done = true;
134 if (chan->dma.ib_max) {
135 nv50_dma_push(chan, chan->push.addr + (chan->dma.put << 2),
136 (chan->dma.cur - chan->dma.put) << 2);
138 WRITE_PUT(chan->dma.cur);
141 chan->dma.put = chan->dma.cur;
145 WIND_RING(struct nouveau_channel *chan)
147 chan->dma.cur = chan->dma.put;
151 #define NV01_SUBCHAN_OBJECT 0x00000000
152 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
153 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
154 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
155 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
156 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
157 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
158 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
159 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
160 #define NV84_SUBCHAN_UEVENT 0x00000020
161 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
162 #define NV10_SUBCHAN_REF_CNT 0x00000050
163 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
164 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
165 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
166 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
167 #define NV40_SUBCHAN_YIELD 0x00000080
169 /* NV_SW object class */
170 #define NV_SW_DMA_VBLSEM 0x0000018c
171 #define NV_SW_VBLSEM_OFFSET 0x00000400
172 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
173 #define NV_SW_VBLSEM_RELEASE 0x00000408
174 #define NV_SW_PAGE_FLIP 0x00000500