drivers/gpu/drm/nouveau/nouveau_dma.h

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef __NOUVEAU_DMA_H__
  28 #define __NOUVEAU_DMA_H__
  29
  30 #include "nouveau_bo.h"
  31 #include "nouveau_chan.h"
  32
  33 int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
  34 void nv50_dma_push(struct nouveau_channel *, u64 addr, int length);
  35
  36 /*
  37  * There's a hw race condition where you can't jump to your PUT offset,
  38  * to avoid this we jump to offset + SKIPS and fill the difference with
  39  * NOPs.
  40  *
  41  * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
  42  * a SKIPS value of 8.  Lets assume that the race condition is to do
  43  * with writing into the fetch area, we configure a fetch size of 128
  44  * bytes so we need a larger SKIPS value.
  45  */
  46 #define NOUVEAU_DMA_SKIPS (128 / 4)
  47
  48 /* Hardcoded object assignments to subchannels (subchannel id). */
  49 enum {
  50         NvSubSw         = 1,
  51         NvSubImageBlit  = 2,
  52 };
  53
  54 /* Object handles - for stuff that's doesn't use handle == oclass. */
  55 enum {
  56         NvDmaFB         = 0x80000002,
  57         NvDmaTT         = 0x80000003,
  58         NvNotify0       = 0x80000006,
  59         NvSema          = 0x8000000f,
  60         NvEvoSema0      = 0x80000010,
  61         NvEvoSema1      = 0x80000011,
  62 };
  63
  64 static __must_check inline int
  65 RING_SPACE(struct nouveau_channel *chan, int size)
  66 {
  67         int ret;
  68
  69         ret = nouveau_dma_wait(chan, 1, size);
  70         if (ret)
  71                 return ret;
  72
  73         chan->dma.free -= size;
  74         return 0;
  75 }
  76
  77 static inline void
  78 OUT_RING(struct nouveau_channel *chan, int data)
  79 {
  80         nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
  81 }
  82
  83 static inline void
  84 BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
  85 {
  86         OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
  87 }
  88
  89 static inline void
  90 BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
  91 {
  92         OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
  93 }
  94
  95 #define WRITE_PUT(val) do {                                                    \
  96         mb();                                                   \
  97         nouveau_bo_rd32(chan->push.buffer, 0);                                 \
  98         nvif_wr32(&chan->user, chan->user_put, ((val) << 2) + chan->push.addr);\
  99 } while (0)
 100
 101 static inline void
 102 FIRE_RING(struct nouveau_channel *chan)
 103 {
 104         if (chan->dma.cur == chan->dma.put)
 105                 return;
 106         chan->accel_done = true;
 107
 108         if (chan->dma.ib_max) {
 109                 nv50_dma_push(chan, chan->push.addr + (chan->dma.put << 2),
 110                               (chan->dma.cur - chan->dma.put) << 2);
 111         } else {
 112                 WRITE_PUT(chan->dma.cur);
 113         }
 114
 115         chan->dma.put = chan->dma.cur;
 116 }
 117
 118 static inline void
 119 WIND_RING(struct nouveau_channel *chan)
 120 {
 121         chan->dma.cur = chan->dma.put;
 122 }
 123
 124 /* FIFO methods */
 125 #define NV01_SUBCHAN_OBJECT                                          0x00000000
 126 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH                          0x00000010
 127 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW                           0x00000014
 128 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE                              0x00000018
 129 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER                               0x0000001c
 130 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL                 0x00000001
 131 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG                    0x00000002
 132 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL                0x00000004
 133 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD                         0x00001000
 134 #define NV84_SUBCHAN_UEVENT                                          0x00000020
 135 #define NV84_SUBCHAN_WRCACHE_FLUSH                                   0x00000024
 136 #define NV10_SUBCHAN_REF_CNT                                         0x00000050
 137 #define NV11_SUBCHAN_DMA_SEMAPHORE                                   0x00000060
 138 #define NV11_SUBCHAN_SEMAPHORE_OFFSET                                0x00000064
 139 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE                               0x00000068
 140 #define NV11_SUBCHAN_SEMAPHORE_RELEASE                               0x0000006c
 141 #define NV40_SUBCHAN_YIELD                                           0x00000080
 142
 143 /* NV_SW object class */
 144 #define NV_SW_DMA_VBLSEM                                             0x0000018c
 145 #define NV_SW_VBLSEM_OFFSET                                          0x00000400
 146 #define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404
 147 #define NV_SW_VBLSEM_RELEASE                                         0x00000408
 148 #define NV_SW_PAGE_FLIP                                              0x00000500
 149
 150 #endif