2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
28 #include <nvif/cl006b.h>
29 #include <nvif/cl506f.h>
30 #include <nvif/cl906f.h>
31 #include <nvif/cla06f.h>
32 #include <nvif/ioctl.h>
35 #include <core/client.h>
37 #include "nouveau_drv.h"
38 #include "nouveau_dma.h"
39 #include "nouveau_bo.h"
40 #include "nouveau_chan.h"
41 #include "nouveau_fence.h"
42 #include "nouveau_abi16.h"
43 #include "nouveau_vmm.h"
45 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
46 int nouveau_vram_pushbuf;
47 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
50 nouveau_channel_killed(struct nvif_notify *ntfy)
52 struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill);
53 struct nouveau_cli *cli = (void *)chan->user.client;
54 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid);
55 atomic_set(&chan->killed, 1);
56 return NVIF_NOTIFY_DROP;
60 nouveau_channel_idle(struct nouveau_channel *chan)
62 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) {
63 struct nouveau_cli *cli = (void *)chan->user.client;
64 struct nouveau_fence *fence = NULL;
67 ret = nouveau_fence_new(chan, false, &fence);
69 ret = nouveau_fence_wait(fence, false, false);
70 nouveau_fence_unref(&fence);
74 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n",
75 chan->chid, nvxx_client(&cli->base)->name);
83 nouveau_channel_del(struct nouveau_channel **pchan)
85 struct nouveau_channel *chan = *pchan;
87 struct nouveau_cli *cli = (void *)chan->user.client;
91 super = cli->base.super;
92 cli->base.super = true;
96 nouveau_fence(chan->drm)->context_del(chan);
97 nvif_object_fini(&chan->nvsw);
98 nvif_object_fini(&chan->gart);
99 nvif_object_fini(&chan->vram);
100 nvif_notify_fini(&chan->kill);
101 nvif_object_fini(&chan->user);
102 nvif_object_fini(&chan->push.ctxdma);
103 nouveau_vma_del(&chan->push.vma);
104 nouveau_bo_unmap(chan->push.buffer);
105 if (chan->push.buffer && chan->push.buffer->pin_refcnt)
106 nouveau_bo_unpin(chan->push.buffer);
107 nouveau_bo_ref(NULL, &chan->push.buffer);
111 cli->base.super = super;
117 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
118 u32 size, struct nouveau_channel **pchan)
120 struct nouveau_cli *cli = (void *)device->object.client;
121 struct nv_dma_v0 args = {};
122 struct nouveau_channel *chan;
126 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
130 chan->device = device;
132 atomic_set(&chan->killed, 0);
134 /* allocate memory for dma push buffer */
135 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
136 if (nouveau_vram_pushbuf)
137 target = TTM_PL_FLAG_VRAM;
139 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL,
142 ret = nouveau_bo_pin(chan->push.buffer, target, false);
144 ret = nouveau_bo_map(chan->push.buffer);
148 nouveau_channel_del(pchan);
152 /* create dma object covering the *entire* memory space that the
153 * pushbuf lives in, this is because the GEM code requires that
154 * we be able to call out to other (indirect) push buffers
156 chan->push.addr = chan->push.buffer->bo.offset;
158 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
159 ret = nouveau_vma_new(chan->push.buffer, &cli->vmm,
162 nouveau_channel_del(pchan);
166 args.target = NV_DMA_V0_TARGET_VM;
167 args.access = NV_DMA_V0_ACCESS_VM;
169 args.limit = cli->vmm.vmm.limit - 1;
171 chan->push.addr = chan->push.vma->addr;
173 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
174 if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
175 /* nv04 vram pushbuf hack, retarget to its location in
176 * the framebuffer bar rather than direct vram access..
177 * nfi why this exists, it came from the -nv ddx.
179 args.target = NV_DMA_V0_TARGET_PCI;
180 args.access = NV_DMA_V0_ACCESS_RDWR;
181 args.start = nvxx_device(device)->func->
182 resource_addr(nvxx_device(device), 1);
183 args.limit = args.start + device->info.ram_user - 1;
185 args.target = NV_DMA_V0_TARGET_VRAM;
186 args.access = NV_DMA_V0_ACCESS_RDWR;
188 args.limit = device->info.ram_user - 1;
191 if (chan->drm->agp.bridge) {
192 args.target = NV_DMA_V0_TARGET_AGP;
193 args.access = NV_DMA_V0_ACCESS_RDWR;
194 args.start = chan->drm->agp.base;
195 args.limit = chan->drm->agp.base +
196 chan->drm->agp.size - 1;
198 args.target = NV_DMA_V0_TARGET_VM;
199 args.access = NV_DMA_V0_ACCESS_RDWR;
201 args.limit = cli->vmm.vmm.limit - 1;
205 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
206 &args, sizeof(args), &chan->push.ctxdma);
208 nouveau_channel_del(pchan);
216 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
217 u32 engine, struct nouveau_channel **pchan)
219 struct nouveau_cli *cli = (void *)device->object.client;
220 static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A,
221 MAXWELL_CHANNEL_GPFIFO_A,
222 KEPLER_CHANNEL_GPFIFO_B,
223 KEPLER_CHANNEL_GPFIFO_A,
224 FERMI_CHANNEL_GPFIFO,
228 const u16 *oclass = oclasses;
230 struct nv50_channel_gpfifo_v0 nv50;
231 struct fermi_channel_gpfifo_v0 fermi;
232 struct kepler_channel_gpfifo_a_v0 kepler;
234 struct nouveau_channel *chan;
238 /* allocate dma push buffer */
239 ret = nouveau_channel_prep(drm, device, 0x12000, &chan);
244 /* create channel object */
246 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
247 args.kepler.version = 0;
248 args.kepler.engines = engine;
249 args.kepler.ilength = 0x02000;
250 args.kepler.ioffset = 0x10000 + chan->push.addr;
251 args.kepler.vmm = nvif_handle(&cli->vmm.vmm.object);
252 size = sizeof(args.kepler);
254 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) {
255 args.fermi.version = 0;
256 args.fermi.ilength = 0x02000;
257 args.fermi.ioffset = 0x10000 + chan->push.addr;
258 args.fermi.vmm = nvif_handle(&cli->vmm.vmm.object);
259 size = sizeof(args.fermi);
261 args.nv50.version = 0;
262 args.nv50.ilength = 0x02000;
263 args.nv50.ioffset = 0x10000 + chan->push.addr;
264 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
265 args.nv50.vmm = nvif_handle(&cli->vmm.vmm.object);
266 size = sizeof(args.nv50);
269 ret = nvif_object_init(&device->object, 0, *oclass++,
270 &args, size, &chan->user);
272 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A)
273 chan->chid = args.kepler.chid;
275 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO)
276 chan->chid = args.fermi.chid;
278 chan->chid = args.nv50.chid;
283 nouveau_channel_del(pchan);
288 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
289 struct nouveau_channel **pchan)
291 static const u16 oclasses[] = { NV40_CHANNEL_DMA,
296 const u16 *oclass = oclasses;
297 struct nv03_channel_dma_v0 args;
298 struct nouveau_channel *chan;
301 /* allocate dma push buffer */
302 ret = nouveau_channel_prep(drm, device, 0x10000, &chan);
307 /* create channel object */
309 args.pushbuf = nvif_handle(&chan->push.ctxdma);
310 args.offset = chan->push.addr;
313 ret = nvif_object_init(&device->object, 0, *oclass++,
314 &args, sizeof(args), &chan->user);
316 chan->chid = args.chid;
319 } while (ret && *oclass);
321 nouveau_channel_del(pchan);
326 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
328 struct nvif_device *device = chan->device;
329 struct nouveau_cli *cli = (void *)chan->user.client;
330 struct nouveau_drm *drm = chan->drm;
331 struct nv_dma_v0 args = {};
334 nvif_object_map(&chan->user, NULL, 0);
336 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) {
337 ret = nvif_notify_init(&chan->user, nouveau_channel_killed,
338 true, NV906F_V0_NTFY_KILLED,
339 NULL, 0, 0, &chan->kill);
341 ret = nvif_notify_get(&chan->kill);
343 NV_ERROR(drm, "Failed to request channel kill "
344 "notification: %d\n", ret);
349 /* allocate dma objects to cover all allowed vram, and gart */
350 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
351 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
352 args.target = NV_DMA_V0_TARGET_VM;
353 args.access = NV_DMA_V0_ACCESS_VM;
355 args.limit = cli->vmm.vmm.limit - 1;
357 args.target = NV_DMA_V0_TARGET_VRAM;
358 args.access = NV_DMA_V0_ACCESS_RDWR;
360 args.limit = device->info.ram_user - 1;
363 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY,
364 &args, sizeof(args), &chan->vram);
368 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
369 args.target = NV_DMA_V0_TARGET_VM;
370 args.access = NV_DMA_V0_ACCESS_VM;
372 args.limit = cli->vmm.vmm.limit - 1;
374 if (chan->drm->agp.bridge) {
375 args.target = NV_DMA_V0_TARGET_AGP;
376 args.access = NV_DMA_V0_ACCESS_RDWR;
377 args.start = chan->drm->agp.base;
378 args.limit = chan->drm->agp.base +
379 chan->drm->agp.size - 1;
381 args.target = NV_DMA_V0_TARGET_VM;
382 args.access = NV_DMA_V0_ACCESS_RDWR;
384 args.limit = cli->vmm.vmm.limit - 1;
387 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY,
388 &args, sizeof(args), &chan->gart);
393 /* initialise dma tracking parameters */
394 switch (chan->user.oclass & 0x00ff) {
397 chan->user_put = 0x40;
398 chan->user_get = 0x44;
399 chan->dma.max = (0x10000 / 4) - 2;
402 chan->user_put = 0x40;
403 chan->user_get = 0x44;
404 chan->user_get_hi = 0x60;
405 chan->dma.ib_base = 0x10000 / 4;
406 chan->dma.ib_max = (0x02000 / 8) - 1;
407 chan->dma.ib_put = 0;
408 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
409 chan->dma.max = chan->dma.ib_base;
414 chan->dma.cur = chan->dma.put;
415 chan->dma.free = chan->dma.max - chan->dma.cur;
417 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
421 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
422 OUT_RING(chan, 0x00000000);
424 /* allocate software object class (used for fences on <= nv05) */
425 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
426 ret = nvif_object_init(&chan->user, 0x006e,
428 NULL, 0, &chan->nvsw);
432 ret = RING_SPACE(chan, 2);
436 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
437 OUT_RING (chan, chan->nvsw.handle);
441 /* initialise synchronisation */
442 return nouveau_fence(chan->drm)->context_new(chan);
446 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
447 u32 arg0, u32 arg1, struct nouveau_channel **pchan)
449 struct nouveau_cli *cli = (void *)device->object.client;
453 /* hack until fencenv50 is fixed, and agp access relaxed */
454 super = cli->base.super;
455 cli->base.super = true;
457 ret = nouveau_channel_ind(drm, device, arg0, pchan);
459 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret);
460 ret = nouveau_channel_dma(drm, device, pchan);
462 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret);
467 ret = nouveau_channel_init(*pchan, arg0, arg1);
469 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret);
470 nouveau_channel_del(pchan);
474 cli->base.super = super;