2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <linux/dma-mapping.h>
32 #include "nouveau_drv.h"
33 #include "nouveau_chan.h"
34 #include "nouveau_fence.h"
36 #include "nouveau_bo.h"
37 #include "nouveau_ttm.h"
38 #include "nouveau_gem.h"
39 #include "nouveau_mem.h"
40 #include "nouveau_vmm.h"
42 #include <nvif/class.h>
43 #include <nvif/if500b.h>
44 #include <nvif/if900b.h>
46 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
47 struct ttm_resource *reg);
48 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
51 * NV10-NV40 tiling helpers
55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63 nouveau_fence_unref(®->fence);
66 nvkm_fb_tile_fini(fb, i, tile);
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71 nvkm_fb_tile_prog(fb, i, tile);
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80 spin_lock(&drm->tile.lock);
83 (!tile->fence || nouveau_fence_done(tile->fence)))
88 spin_unlock(&drm->tile.lock);
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
96 struct nouveau_drm *drm = nouveau_drm(dev);
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 spin_unlock(&drm->tile.lock);
106 static struct nouveau_drm_tile *
107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
118 if (pitch && !found) {
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
127 nv10_bo_put_tile_region(dev, tile, NULL);
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
142 WARN_ON(nvbo->bo.pin_count > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
151 drm_gem_object_release(&bo->base);
157 roundup_64(u64 x, u32 y)
165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
168 struct nvif_device *device = &drm->client.device;
170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
172 if (device->info.chipset >= 0x40) {
174 *size = roundup_64(*size, 64 * nvbo->mode);
176 } else if (device->info.chipset >= 0x30) {
178 *size = roundup_64(*size, 64 * nvbo->mode);
180 } else if (device->info.chipset >= 0x20) {
182 *size = roundup_64(*size, 64 * nvbo->mode);
184 } else if (device->info.chipset >= 0x10) {
186 *size = roundup_64(*size, 32 * nvbo->mode);
190 *size = roundup_64(*size, (1 << nvbo->page));
191 *align = max((1 << nvbo->page), *align);
194 *size = roundup_64(*size, PAGE_SIZE);
198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
199 u32 tile_mode, u32 tile_flags)
201 struct nouveau_drm *drm = cli->drm;
202 struct nouveau_bo *nvbo;
203 struct nvif_mmu *mmu = &cli->mmu;
204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
208 NV_WARN(drm, "skipped size %016llx\n", *size);
209 return ERR_PTR(-EINVAL);
212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
214 return ERR_PTR(-ENOMEM);
215 INIT_LIST_HEAD(&nvbo->head);
216 INIT_LIST_HEAD(&nvbo->entry);
217 INIT_LIST_HEAD(&nvbo->vma_list);
218 nvbo->bo.bdev = &drm->ttm.bdev;
220 /* This is confusing, and doesn't actually mean we want an uncached
221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
222 * into in nouveau_gem_new().
224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
225 /* Determine if we can get a cache-coherent map, forcing
226 * uncached mapping if we can't.
228 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
229 nvbo->force_coherent = true;
232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
236 return ERR_PTR(-EINVAL);
239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
242 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
243 nvbo->comp = (tile_flags & 0x00030000) >> 16;
244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
246 return ERR_PTR(-EINVAL);
249 nvbo->zeta = (tile_flags & 0x00000007);
251 nvbo->mode = tile_mode;
252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
254 /* Determine the desirable target GPU page size for the buffer. */
255 for (i = 0; i < vmm->page_nr; i++) {
256 /* Because we cannot currently allow VMM maps to fail
257 * during buffer migration, we need to determine page
258 * size for the buffer up-front, and pre-allocate its
261 * Skip page sizes that can't support needed domains.
263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
270 /* Select this page size if it's the first that supports
271 * the potential memory domains, or when it's compatible
272 * with the requested compression settings.
274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
277 /* Stop once the buffer is larger than the current page size. */
278 if (*size >= 1ULL << vmm->page[i].shift)
283 return ERR_PTR(-EINVAL);
285 /* Disable compression if suitable settings couldn't be found. */
286 if (nvbo->comp && !vmm->page[pi].comp) {
287 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
288 nvbo->kind = mmu->kind[nvbo->kind];
291 nvbo->page = vmm->page[pi].shift;
293 nouveau_bo_fixup_align(nvbo, align, size);
299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
300 struct sg_table *sg, struct dma_resv *robj)
302 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
305 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
306 nouveau_bo_placement_set(nvbo, domain, 0);
307 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
309 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
310 &nvbo->placement, align >> PAGE_SHIFT, false, sg,
311 robj, nouveau_bo_del_ttm);
313 /* ttm will call nouveau_bo_del_ttm if it fails.. */
321 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
322 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
323 struct sg_table *sg, struct dma_resv *robj,
324 struct nouveau_bo **pnvbo)
326 struct nouveau_bo *nvbo;
329 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
332 return PTR_ERR(nvbo);
334 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
343 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
347 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
348 pl[*n].mem_type = TTM_PL_VRAM;
352 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
353 pl[*n].mem_type = TTM_PL_TT;
357 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
358 pl[*n].mem_type = TTM_PL_SYSTEM;
359 pl[(*n)++].flags = 0;
364 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
366 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
367 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
368 unsigned i, fpfn, lpfn;
370 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
371 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
372 nvbo->bo.mem.num_pages < vram_pages / 4) {
374 * Make sure that the color and depth buffers are handled
375 * by independent memory controller units. Up to a 9x
376 * speed up when alpha-blending and depth-test are enabled
380 fpfn = vram_pages / 2;
384 lpfn = vram_pages / 2;
386 for (i = 0; i < nvbo->placement.num_placement; ++i) {
387 nvbo->placements[i].fpfn = fpfn;
388 nvbo->placements[i].lpfn = lpfn;
390 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
391 nvbo->busy_placements[i].fpfn = fpfn;
392 nvbo->busy_placements[i].lpfn = lpfn;
398 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
401 struct ttm_placement *pl = &nvbo->placement;
403 pl->placement = nvbo->placements;
404 set_placement_list(nvbo->placements, &pl->num_placement, domain);
406 pl->busy_placement = nvbo->busy_placements;
407 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
410 set_placement_range(nvbo, domain);
414 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
416 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
417 struct ttm_buffer_object *bo = &nvbo->bo;
418 bool force = false, evict = false;
421 ret = ttm_bo_reserve(bo, false, false, NULL);
425 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
426 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
434 if (nvbo->bo.pin_count) {
437 switch (bo->mem.mem_type) {
439 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
442 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
449 NV_ERROR(drm, "bo %p pinned elsewhere: "
450 "0x%08x vs 0x%08x\n", bo,
451 bo->mem.mem_type, domain);
454 ttm_bo_pin(&nvbo->bo);
459 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
460 ret = nouveau_bo_validate(nvbo, false, false);
465 nouveau_bo_placement_set(nvbo, domain, 0);
466 ret = nouveau_bo_validate(nvbo, false, false);
470 ttm_bo_pin(&nvbo->bo);
472 switch (bo->mem.mem_type) {
474 drm->gem.vram_available -= bo->base.size;
477 drm->gem.gart_available -= bo->base.size;
485 nvbo->contig = false;
486 ttm_bo_unreserve(bo);
491 nouveau_bo_unpin(struct nouveau_bo *nvbo)
493 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
494 struct ttm_buffer_object *bo = &nvbo->bo;
497 ret = ttm_bo_reserve(bo, false, false, NULL);
501 ttm_bo_unpin(&nvbo->bo);
502 if (!nvbo->bo.pin_count) {
503 switch (bo->mem.mem_type) {
505 drm->gem.vram_available += bo->base.size;
508 drm->gem.gart_available += bo->base.size;
515 ttm_bo_unreserve(bo);
520 nouveau_bo_map(struct nouveau_bo *nvbo)
524 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
528 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
530 ttm_bo_unreserve(&nvbo->bo);
535 nouveau_bo_unmap(struct nouveau_bo *nvbo)
540 ttm_bo_kunmap(&nvbo->kmap);
544 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
546 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
547 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
550 if (!ttm_dma || !ttm_dma->dma_address)
552 if (!ttm_dma->pages) {
553 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
557 /* Don't waste time looping if the object is coherent */
558 if (nvbo->force_coherent)
562 while (i < ttm_dma->num_pages) {
563 struct page *p = ttm_dma->pages[i];
564 size_t num_pages = 1;
566 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
567 if (++p != ttm_dma->pages[j])
572 dma_sync_single_for_device(drm->dev->dev,
573 ttm_dma->dma_address[i],
574 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
580 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
582 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
583 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
586 if (!ttm_dma || !ttm_dma->dma_address)
588 if (!ttm_dma->pages) {
589 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
593 /* Don't waste time looping if the object is coherent */
594 if (nvbo->force_coherent)
598 while (i < ttm_dma->num_pages) {
599 struct page *p = ttm_dma->pages[i];
600 size_t num_pages = 1;
602 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
603 if (++p != ttm_dma->pages[j])
609 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
610 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
615 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
617 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
618 struct nouveau_bo *nvbo = nouveau_bo(bo);
620 mutex_lock(&drm->ttm.io_reserve_mutex);
621 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
622 mutex_unlock(&drm->ttm.io_reserve_mutex);
625 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
627 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
628 struct nouveau_bo *nvbo = nouveau_bo(bo);
630 mutex_lock(&drm->ttm.io_reserve_mutex);
631 list_del_init(&nvbo->io_reserve_lru);
632 mutex_unlock(&drm->ttm.io_reserve_mutex);
636 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
639 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
642 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
646 nouveau_bo_sync_for_device(nvbo);
652 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
655 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
660 iowrite16_native(val, (void __force __iomem *)mem);
666 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
669 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
674 return ioread32_native((void __force __iomem *)mem);
680 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
683 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
688 iowrite32_native(val, (void __force __iomem *)mem);
693 static struct ttm_tt *
694 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
696 #if IS_ENABLED(CONFIG_AGP)
697 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
699 if (drm->agp.bridge) {
700 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
704 return nouveau_sgdma_create_ttm(bo, page_flags);
708 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
709 struct ttm_resource *reg)
711 #if IS_ENABLED(CONFIG_AGP)
712 struct nouveau_drm *drm = nouveau_bdev(bdev);
716 #if IS_ENABLED(CONFIG_AGP)
718 return ttm_agp_bind(ttm, reg);
720 return nouveau_sgdma_bind(bdev, ttm, reg);
724 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
726 #if IS_ENABLED(CONFIG_AGP)
727 struct nouveau_drm *drm = nouveau_bdev(bdev);
729 if (drm->agp.bridge) {
734 nouveau_sgdma_unbind(bdev, ttm);
738 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
740 struct nouveau_bo *nvbo = nouveau_bo(bo);
742 switch (bo->mem.mem_type) {
744 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
745 NOUVEAU_GEM_DOMAIN_CPU);
748 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
752 *pl = nvbo->placement;
756 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
757 struct ttm_resource *reg)
759 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
760 struct nouveau_mem *new_mem = nouveau_mem(reg);
761 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
764 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
765 old_mem->mem.size, &old_mem->vma[0]);
769 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
770 new_mem->mem.size, &old_mem->vma[1]);
774 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
778 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
781 nvif_vmm_put(vmm, &old_mem->vma[1]);
782 nvif_vmm_put(vmm, &old_mem->vma[0]);
788 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
789 struct ttm_operation_ctx *ctx,
790 struct ttm_resource *new_reg)
792 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
793 struct nouveau_channel *chan = drm->ttm.chan;
794 struct nouveau_cli *cli = (void *)chan->user.client;
795 struct nouveau_fence *fence;
798 /* create temporary vmas for the transfer and attach them to the
799 * old nvkm_mem node, these will get cleaned up after ttm has
800 * destroyed the ttm_resource
802 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
803 ret = nouveau_bo_move_prep(drm, bo, new_reg);
808 if (drm_drv_uses_atomic_modeset(drm->dev))
809 mutex_lock(&cli->mutex);
811 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
812 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
814 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
816 ret = nouveau_fence_new(chan, false, &fence);
818 ret = ttm_bo_move_accel_cleanup(bo,
822 nouveau_fence_unref(&fence);
826 mutex_unlock(&cli->mutex);
831 nouveau_bo_move_init(struct nouveau_drm *drm)
833 static const struct _method_table {
837 int (*exec)(struct nouveau_channel *,
838 struct ttm_buffer_object *,
839 struct ttm_resource *, struct ttm_resource *);
840 int (*init)(struct nouveau_channel *, u32 handle);
842 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
843 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
844 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
845 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
846 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
847 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
848 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
849 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
850 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
851 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
852 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
853 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
854 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
855 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
856 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
857 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
858 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
859 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
860 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
863 const struct _method_table *mthd = _methods;
864 const char *name = "CPU";
868 struct nouveau_channel *chan;
877 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
878 mthd->oclass | (mthd->engine << 16),
879 mthd->oclass, NULL, 0,
882 ret = mthd->init(chan, drm->ttm.copy.handle);
884 nvif_object_dtor(&drm->ttm.copy);
888 drm->ttm.move = mthd->exec;
889 drm->ttm.chan = chan;
893 } while ((++mthd)->exec);
895 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
898 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
899 struct ttm_resource *new_reg)
901 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
902 struct nouveau_bo *nvbo = nouveau_bo(bo);
903 struct nouveau_vma *vma;
905 /* ttm can now (stupidly) pass the driver bos it didn't create... */
906 if (bo->destroy != nouveau_bo_del_ttm)
909 nouveau_bo_del_io_reserve_lru(bo);
911 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
912 mem->mem.page == nvbo->page) {
913 list_for_each_entry(vma, &nvbo->vma_list, head) {
914 nouveau_vma_map(vma, mem);
917 list_for_each_entry(vma, &nvbo->vma_list, head) {
918 WARN_ON(ttm_bo_wait(bo, false, false));
919 nouveau_vma_unmap(vma);
924 if (new_reg->mm_node)
925 nvbo->offset = (new_reg->start << PAGE_SHIFT);
933 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
934 struct nouveau_drm_tile **new_tile)
936 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
937 struct drm_device *dev = drm->dev;
938 struct nouveau_bo *nvbo = nouveau_bo(bo);
939 u64 offset = new_reg->start << PAGE_SHIFT;
942 if (new_reg->mem_type != TTM_PL_VRAM)
945 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
946 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
947 nvbo->mode, nvbo->zeta);
954 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
955 struct nouveau_drm_tile *new_tile,
956 struct nouveau_drm_tile **old_tile)
958 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
959 struct drm_device *dev = drm->dev;
960 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
962 nv10_bo_put_tile_region(dev, *old_tile, fence);
963 *old_tile = new_tile;
967 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
968 struct ttm_operation_ctx *ctx,
969 struct ttm_resource *new_reg,
970 struct ttm_place *hop)
972 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
973 struct nouveau_bo *nvbo = nouveau_bo(bo);
974 struct ttm_resource *old_reg = &bo->mem;
975 struct nouveau_drm_tile *new_tile = NULL;
979 if (new_reg->mem_type == TTM_PL_TT) {
980 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
985 nouveau_bo_move_ntfy(bo, new_reg);
986 ret = ttm_bo_wait_ctx(bo, ctx);
990 if (nvbo->bo.pin_count)
991 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
993 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
994 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1000 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1001 ttm_bo_move_null(bo, new_reg);
1005 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1006 new_reg->mem_type == TTM_PL_TT) {
1007 ttm_bo_move_null(bo, new_reg);
1011 if (old_reg->mem_type == TTM_PL_TT &&
1012 new_reg->mem_type == TTM_PL_SYSTEM) {
1013 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1014 ttm_resource_free(bo, &bo->mem);
1015 ttm_bo_assign_mem(bo, new_reg);
1019 /* Hardware assisted copy. */
1020 if (drm->ttm.move) {
1021 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1022 new_reg->mem_type == TTM_PL_VRAM) ||
1023 (old_reg->mem_type == TTM_PL_VRAM &&
1024 new_reg->mem_type == TTM_PL_SYSTEM)) {
1027 hop->mem_type = TTM_PL_TT;
1031 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1037 /* Fallback to software copy. */
1038 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1042 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1044 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1046 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1050 nouveau_bo_move_ntfy(bo, &bo->mem);
1056 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1058 struct nouveau_bo *nvbo = nouveau_bo(bo);
1060 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1061 filp->private_data);
1065 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1066 struct ttm_resource *reg)
1068 struct nouveau_mem *mem = nouveau_mem(reg);
1070 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1071 switch (reg->mem_type) {
1074 nvif_object_unmap_handle(&mem->mem.object);
1077 nvif_object_unmap_handle(&mem->mem.object);
1086 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1088 struct nouveau_drm *drm = nouveau_bdev(bdev);
1089 struct nvkm_device *device = nvxx_device(&drm->client.device);
1090 struct nouveau_mem *mem = nouveau_mem(reg);
1091 struct nvif_mmu *mmu = &drm->client.mmu;
1094 mutex_lock(&drm->ttm.io_reserve_mutex);
1096 switch (reg->mem_type) {
1102 #if IS_ENABLED(CONFIG_AGP)
1103 if (drm->agp.bridge) {
1104 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1106 reg->bus.is_iomem = !drm->agp.cma;
1107 reg->bus.caching = ttm_write_combined;
1110 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1116 fallthrough; /* tiled memory */
1118 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1119 device->func->resource_addr(device, 1);
1120 reg->bus.is_iomem = true;
1122 /* Some BARs do not support being ioremapped WC */
1123 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1124 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1125 reg->bus.caching = ttm_uncached;
1127 reg->bus.caching = ttm_write_combined;
1129 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1131 struct nv50_mem_map_v0 nv50;
1132 struct gf100_mem_map_v0 gf100;
1137 switch (mem->mem.object.oclass) {
1138 case NVIF_CLASS_MEM_NV50:
1139 args.nv50.version = 0;
1141 args.nv50.kind = mem->kind;
1142 args.nv50.comp = mem->comp;
1143 argc = sizeof(args.nv50);
1145 case NVIF_CLASS_MEM_GF100:
1146 args.gf100.version = 0;
1148 args.gf100.kind = mem->kind;
1149 argc = sizeof(args.gf100);
1156 ret = nvif_object_map_handle(&mem->mem.object,
1160 if (WARN_ON(ret == 0))
1165 reg->bus.offset = handle;
1174 if (ret == -ENOSPC) {
1175 struct nouveau_bo *nvbo;
1177 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1181 list_del_init(&nvbo->io_reserve_lru);
1182 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1184 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
1189 mutex_unlock(&drm->ttm.io_reserve_mutex);
1194 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1196 struct nouveau_drm *drm = nouveau_bdev(bdev);
1198 mutex_lock(&drm->ttm.io_reserve_mutex);
1199 nouveau_ttm_io_mem_free_locked(drm, reg);
1200 mutex_unlock(&drm->ttm.io_reserve_mutex);
1203 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1205 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1206 struct nouveau_bo *nvbo = nouveau_bo(bo);
1207 struct nvkm_device *device = nvxx_device(&drm->client.device);
1208 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1211 /* as long as the bo isn't in vram, and isn't tiled, we've got
1212 * nothing to do here.
1214 if (bo->mem.mem_type != TTM_PL_VRAM) {
1215 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1219 if (bo->mem.mem_type != TTM_PL_SYSTEM)
1222 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1225 /* make sure bo is in mappable vram */
1226 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1227 bo->mem.start + bo->mem.num_pages < mappable)
1230 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1231 nvbo->placements[i].fpfn = 0;
1232 nvbo->placements[i].lpfn = mappable;
1235 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1236 nvbo->busy_placements[i].fpfn = 0;
1237 nvbo->busy_placements[i].lpfn = mappable;
1240 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1243 ret = nouveau_bo_validate(nvbo, false, false);
1244 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1245 return VM_FAULT_NOPAGE;
1246 else if (unlikely(ret))
1247 return VM_FAULT_SIGBUS;
1249 ttm_bo_move_to_lru_tail_unlocked(bo);
1254 nouveau_ttm_tt_populate(struct ttm_device *bdev,
1255 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1257 struct ttm_tt *ttm_dma = (void *)ttm;
1258 struct nouveau_drm *drm;
1260 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1262 if (ttm_tt_is_populated(ttm))
1265 if (slave && ttm->sg) {
1266 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1271 drm = nouveau_bdev(bdev);
1272 dev = drm->dev->dev;
1274 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1278 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1281 struct nouveau_drm *drm;
1283 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1288 drm = nouveau_bdev(bdev);
1289 dev = drm->dev->dev;
1291 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1295 nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1298 #if IS_ENABLED(CONFIG_AGP)
1299 struct nouveau_drm *drm = nouveau_bdev(bdev);
1300 if (drm->agp.bridge) {
1301 ttm_agp_unbind(ttm);
1302 ttm_tt_destroy_common(bdev, ttm);
1303 ttm_agp_destroy(ttm);
1307 nouveau_sgdma_destroy(bdev, ttm);
1311 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1313 struct dma_resv *resv = nvbo->bo.base.resv;
1316 dma_resv_add_excl_fence(resv, &fence->base);
1318 dma_resv_add_shared_fence(resv, &fence->base);
1322 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1324 nouveau_bo_move_ntfy(bo, NULL);
1327 struct ttm_device_funcs nouveau_bo_driver = {
1328 .ttm_tt_create = &nouveau_ttm_tt_create,
1329 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1330 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1331 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1332 .eviction_valuable = ttm_bo_eviction_valuable,
1333 .evict_flags = nouveau_bo_evict_flags,
1334 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1335 .move = nouveau_bo_move,
1336 .verify_access = nouveau_bo_verify_access,
1337 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1338 .io_mem_free = &nouveau_ttm_io_mem_free,