drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include "nouveau_drm.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40
  41 /*
  42  * NV10-NV40 tiling helpers
  43  */
  44
  45 static void
  46 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  47                            u32 addr, u32 size, u32 pitch, u32 flags)
  48 {
  49         struct nouveau_drm *drm = nouveau_drm(dev);
  50         int i = reg - drm->tile.reg;
  51         struct nouveau_fb *pfb = nvkm_fb(&drm->device);
  52         struct nouveau_fb_tile *tile = &pfb->tile.region[i];
  53         struct nouveau_engine *engine;
  54
  55         nouveau_fence_unref(&reg->fence);
  56
  57         if (tile->pitch)
  58                 pfb->tile.fini(pfb, i, tile);
  59
  60         if (pitch)
  61                 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
  62
  63         pfb->tile.prog(pfb, i, tile);
  64
  65         if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
  66                 engine->tile_prog(engine, i);
  67         if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
  68                 engine->tile_prog(engine, i);
  69 }
  70
  71 static struct nouveau_drm_tile *
  72 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  73 {
  74         struct nouveau_drm *drm = nouveau_drm(dev);
  75         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  76
  77         spin_lock(&drm->tile.lock);
  78
  79         if (!tile->used &&
  80             (!tile->fence || nouveau_fence_done(tile->fence)))
  81                 tile->used = true;
  82         else
  83                 tile = NULL;
  84
  85         spin_unlock(&drm->tile.lock);
  86         return tile;
  87 }
  88
  89 static void
  90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  91                         struct fence *fence)
  92 {
  93         struct nouveau_drm *drm = nouveau_drm(dev);
  94
  95         if (tile) {
  96                 spin_lock(&drm->tile.lock);
  97                 tile->fence = (struct nouveau_fence *)fence_get(fence);
  98                 tile->used = false;
  99                 spin_unlock(&drm->tile.lock);
 100         }
 101 }
 102
 103 static struct nouveau_drm_tile *
 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 105                    u32 size, u32 pitch, u32 flags)
 106 {
 107         struct nouveau_drm *drm = nouveau_drm(dev);
 108         struct nouveau_fb *pfb = nvkm_fb(&drm->device);
 109         struct nouveau_drm_tile *tile, *found = NULL;
 110         int i;
 111
 112         for (i = 0; i < pfb->tile.regions; i++) {
 113                 tile = nv10_bo_get_tile_region(dev, i);
 114
 115                 if (pitch && !found) {
 116                         found = tile;
 117                         continue;
 118
 119                 } else if (tile && pfb->tile.region[i].pitch) {
 120                         /* Kill an unused tile region. */
 121                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 122                 }
 123
 124                 nv10_bo_put_tile_region(dev, tile, NULL);
 125         }
 126
 127         if (found)
 128                 nv10_bo_update_tile_region(dev, found, addr, size,
 129                                             pitch, flags);
 130         return found;
 131 }
 132
 133 static void
 134 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 135 {
 136         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 137         struct drm_device *dev = drm->dev;
 138         struct nouveau_bo *nvbo = nouveau_bo(bo);
 139
 140         if (unlikely(nvbo->gem.filp))
 141                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
 142         WARN_ON(nvbo->pin_refcnt > 0);
 143         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 144         kfree(nvbo);
 145 }
 146
 147 static void
 148 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
 149                        int *align, int *size)
 150 {
 151         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 152         struct nvif_device *device = &drm->device;
 153
 154         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 155                 if (nvbo->tile_mode) {
 156                         if (device->info.chipset >= 0x40) {
 157                                 *align = 65536;
 158                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 159
 160                         } else if (device->info.chipset >= 0x30) {
 161                                 *align = 32768;
 162                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 163
 164                         } else if (device->info.chipset >= 0x20) {
 165                                 *align = 16384;
 166                                 *size = roundup(*size, 64 * nvbo->tile_mode);
 167
 168                         } else if (device->info.chipset >= 0x10) {
 169                                 *align = 16384;
 170                                 *size = roundup(*size, 32 * nvbo->tile_mode);
 171                         }
 172                 }
 173         } else {
 174                 *size = roundup(*size, (1 << nvbo->page_shift));
 175                 *align = max((1 <<  nvbo->page_shift), *align);
 176         }
 177
 178         *size = roundup(*size, PAGE_SIZE);
 179 }
 180
 181 int
 182 nouveau_bo_new(struct drm_device *dev, int size, int align,
 183                uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
 184                struct sg_table *sg, struct reservation_object *robj,
 185                struct nouveau_bo **pnvbo)
 186 {
 187         struct nouveau_drm *drm = nouveau_drm(dev);
 188         struct nouveau_bo *nvbo;
 189         size_t acc_size;
 190         int ret;
 191         int type = ttm_bo_type_device;
 192         int lpg_shift = 12;
 193         int max_size;
 194
 195         if (drm->client.vm)
 196                 lpg_shift = drm->client.vm->vmm->lpg_shift;
 197         max_size = INT_MAX & ~((1 << lpg_shift) - 1);
 198
 199         if (size <= 0 || size > max_size) {
 200                 NV_WARN(drm, "skipped size %x\n", (u32)size);
 201                 return -EINVAL;
 202         }
 203
 204         if (sg)
 205                 type = ttm_bo_type_sg;
 206
 207         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 208         if (!nvbo)
 209                 return -ENOMEM;
 210         INIT_LIST_HEAD(&nvbo->head);
 211         INIT_LIST_HEAD(&nvbo->entry);
 212         INIT_LIST_HEAD(&nvbo->vma_list);
 213         nvbo->tile_mode = tile_mode;
 214         nvbo->tile_flags = tile_flags;
 215         nvbo->bo.bdev = &drm->ttm.bdev;
 216
 217         if (!nv_device_is_cpu_coherent(nvkm_device(&drm->device)))
 218                 nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
 219
 220         nvbo->page_shift = 12;
 221         if (drm->client.vm) {
 222                 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
 223                         nvbo->page_shift = drm->client.vm->vmm->lpg_shift;
 224         }
 225
 226         nouveau_bo_fixup_align(nvbo, flags, &align, &size);
 227         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 228         nouveau_bo_placement_set(nvbo, flags, 0);
 229
 230         acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
 231                                        sizeof(struct nouveau_bo));
 232
 233         ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
 234                           type, &nvbo->placement,
 235                           align >> PAGE_SHIFT, false, NULL, acc_size, sg,
 236                           robj, nouveau_bo_del_ttm);
 237         if (ret) {
 238                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 239                 return ret;
 240         }
 241
 242         *pnvbo = nvbo;
 243         return 0;
 244 }
 245
 246 static void
 247 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
 248 {
 249         *n = 0;
 250
 251         if (type & TTM_PL_FLAG_VRAM)
 252                 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
 253         if (type & TTM_PL_FLAG_TT)
 254                 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
 255         if (type & TTM_PL_FLAG_SYSTEM)
 256                 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
 257 }
 258
 259 static void
 260 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 261 {
 262         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 263         u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
 264         unsigned i, fpfn, lpfn;
 265
 266         if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 267             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
 268             nvbo->bo.mem.num_pages < vram_pages / 4) {
 269                 /*
 270                  * Make sure that the color and depth buffers are handled
 271                  * by independent memory controller units. Up to a 9x
 272                  * speed up when alpha-blending and depth-test are enabled
 273                  * at the same time.
 274                  */
 275                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 276                         fpfn = vram_pages / 2;
 277                         lpfn = ~0;
 278                 } else {
 279                         fpfn = 0;
 280                         lpfn = vram_pages / 2;
 281                 }
 282                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 283                         nvbo->placements[i].fpfn = fpfn;
 284                         nvbo->placements[i].lpfn = lpfn;
 285                 }
 286                 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
 287                         nvbo->busy_placements[i].fpfn = fpfn;
 288                         nvbo->busy_placements[i].lpfn = lpfn;
 289                 }
 290         }
 291 }
 292
 293 void
 294 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 295 {
 296         struct ttm_placement *pl = &nvbo->placement;
 297         uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
 298                                                  TTM_PL_MASK_CACHING) |
 299                          (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 300
 301         pl->placement = nvbo->placements;
 302         set_placement_list(nvbo->placements, &pl->num_placement,
 303                            type, flags);
 304
 305         pl->busy_placement = nvbo->busy_placements;
 306         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 307                            type | busy, flags);
 308
 309         set_placement_range(nvbo, type);
 310 }
 311
 312 int
 313 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 314 {
 315         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 316         struct ttm_buffer_object *bo = &nvbo->bo;
 317         int ret;
 318
 319         ret = ttm_bo_reserve(bo, false, false, false, NULL);
 320         if (ret)
 321                 goto out;
 322
 323         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 324                 NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 325                          1 << bo->mem.mem_type, memtype);
 326                 ret = -EINVAL;
 327                 goto out;
 328         }
 329
 330         if (nvbo->pin_refcnt)
 331                 goto ref_inc;
 332
 333         nouveau_bo_placement_set(nvbo, memtype, 0);
 334
 335         ret = nouveau_bo_validate(nvbo, false, false);
 336         if (ret == 0) {
 337                 switch (bo->mem.mem_type) {
 338                 case TTM_PL_VRAM:
 339                         drm->gem.vram_available -= bo->mem.size;
 340                         break;
 341                 case TTM_PL_TT:
 342                         drm->gem.gart_available -= bo->mem.size;
 343                         break;
 344                 default:
 345                         break;
 346                 }
 347         }
 348
 349 ref_inc:
 350         nvbo->pin_refcnt++;
 351
 352 out:
 353         ttm_bo_unreserve(bo);
 354         return ret;
 355 }
 356
 357 int
 358 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 359 {
 360         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 361         struct ttm_buffer_object *bo = &nvbo->bo;
 362         int ret, ref;
 363
 364         ret = ttm_bo_reserve(bo, false, false, false, NULL);
 365         if (ret)
 366                 return ret;
 367
 368         ref = --nvbo->pin_refcnt;
 369         WARN_ON_ONCE(ref < 0);
 370         if (ref)
 371                 goto out;
 372
 373         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 374
 375         ret = nouveau_bo_validate(nvbo, false, false);
 376         if (ret == 0) {
 377                 switch (bo->mem.mem_type) {
 378                 case TTM_PL_VRAM:
 379                         drm->gem.vram_available += bo->mem.size;
 380                         break;
 381                 case TTM_PL_TT:
 382                         drm->gem.gart_available += bo->mem.size;
 383                         break;
 384                 default:
 385                         break;
 386                 }
 387         }
 388
 389 out:
 390         ttm_bo_unreserve(bo);
 391         return ret;
 392 }
 393
 394 int
 395 nouveau_bo_map(struct nouveau_bo *nvbo)
 396 {
 397         int ret;
 398
 399         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL);
 400         if (ret)
 401                 return ret;
 402
 403         /*
 404          * TTM buffers allocated using the DMA API already have a mapping, let's
 405          * use it instead.
 406          */
 407         if (!nvbo->force_coherent)
 408                 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,
 409                                   &nvbo->kmap);
 410
 411         ttm_bo_unreserve(&nvbo->bo);
 412         return ret;
 413 }
 414
 415 void
 416 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 417 {
 418         if (!nvbo)
 419                 return;
 420
 421         /*
 422          * TTM buffers allocated using the DMA API already had a coherent
 423          * mapping which we used, no need to unmap.
 424          */
 425         if (!nvbo->force_coherent)
 426                 ttm_bo_kunmap(&nvbo->kmap);
 427 }
 428
 429 void
 430 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 431 {
 432         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 433         struct nouveau_device *device = nvkm_device(&drm->device);
 434         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 435         int i;
 436
 437         if (!ttm_dma)
 438                 return;
 439
 440         /* Don't waste time looping if the object is coherent */
 441         if (nvbo->force_coherent)
 442                 return;
 443
 444         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 445                 dma_sync_single_for_device(nv_device_base(device),
 446                         ttm_dma->dma_address[i], PAGE_SIZE, DMA_TO_DEVICE);
 447 }
 448
 449 void
 450 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 451 {
 452         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 453         struct nouveau_device *device = nvkm_device(&drm->device);
 454         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 455         int i;
 456
 457         if (!ttm_dma)
 458                 return;
 459
 460         /* Don't waste time looping if the object is coherent */
 461         if (nvbo->force_coherent)
 462                 return;
 463
 464         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 465                 dma_sync_single_for_cpu(nv_device_base(device),
 466                         ttm_dma->dma_address[i], PAGE_SIZE, DMA_FROM_DEVICE);
 467 }
 468
 469 int
 470 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 471                     bool no_wait_gpu)
 472 {
 473         int ret;
 474
 475         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
 476                               interruptible, no_wait_gpu);
 477         if (ret)
 478                 return ret;
 479
 480         nouveau_bo_sync_for_device(nvbo);
 481
 482         return 0;
 483 }
 484
 485 static inline void *
 486 _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
 487 {
 488         struct ttm_dma_tt *dma_tt;
 489         u8 *m = mem;
 490
 491         index *= sz;
 492
 493         if (m) {
 494                 /* kmap'd address, return the corresponding offset */
 495                 m += index;
 496         } else {
 497                 /* DMA-API mapping, lookup the right address */
 498                 dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;
 499                 m = dma_tt->cpu_address[index / PAGE_SIZE];
 500                 m += index % PAGE_SIZE;
 501         }
 502
 503         return m;
 504 }
 505 #define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
 506
 507 u16
 508 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 509 {
 510         bool is_iomem;
 511         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 512
 513         mem = nouveau_bo_mem_index(nvbo, index, mem);
 514
 515         if (is_iomem)
 516                 return ioread16_native((void __force __iomem *)mem);
 517         else
 518                 return *mem;
 519 }
 520
 521 void
 522 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 523 {
 524         bool is_iomem;
 525         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 526
 527         mem = nouveau_bo_mem_index(nvbo, index, mem);
 528
 529         if (is_iomem)
 530                 iowrite16_native(val, (void __force __iomem *)mem);
 531         else
 532                 *mem = val;
 533 }
 534
 535 u32
 536 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 537 {
 538         bool is_iomem;
 539         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 540
 541         mem = nouveau_bo_mem_index(nvbo, index, mem);
 542
 543         if (is_iomem)
 544                 return ioread32_native((void __force __iomem *)mem);
 545         else
 546                 return *mem;
 547 }
 548
 549 void
 550 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 551 {
 552         bool is_iomem;
 553         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 554
 555         mem = nouveau_bo_mem_index(nvbo, index, mem);
 556
 557         if (is_iomem)
 558                 iowrite32_native(val, (void __force __iomem *)mem);
 559         else
 560                 *mem = val;
 561 }
 562
 563 static struct ttm_tt *
 564 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
 565                       uint32_t page_flags, struct page *dummy_read)
 566 {
 567 #if __OS_HAS_AGP
 568         struct nouveau_drm *drm = nouveau_bdev(bdev);
 569         struct drm_device *dev = drm->dev;
 570
 571         if (drm->agp.stat == ENABLED) {
 572                 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
 573                                          page_flags, dummy_read);
 574         }
 575 #endif
 576
 577         return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
 578 }
 579
 580 static int
 581 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 582 {
 583         /* We'll do this from user space. */
 584         return 0;
 585 }
 586
 587 static int
 588 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 589                          struct ttm_mem_type_manager *man)
 590 {
 591         struct nouveau_drm *drm = nouveau_bdev(bdev);
 592
 593         switch (type) {
 594         case TTM_PL_SYSTEM:
 595                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 596                 man->available_caching = TTM_PL_MASK_CACHING;
 597                 man->default_caching = TTM_PL_FLAG_CACHED;
 598                 break;
 599         case TTM_PL_VRAM:
 600                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 601                              TTM_MEMTYPE_FLAG_MAPPABLE;
 602                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 603                                          TTM_PL_FLAG_WC;
 604                 man->default_caching = TTM_PL_FLAG_WC;
 605
 606                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 607                         /* Some BARs do not support being ioremapped WC */
 608                         if (nvkm_bar(&drm->device)->iomap_uncached) {
 609                                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 610                                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 611                         }
 612
 613                         man->func = &nouveau_vram_manager;
 614                         man->io_reserve_fastpath = false;
 615                         man->use_io_reserve_lru = true;
 616                 } else {
 617                         man->func = &ttm_bo_manager_func;
 618                 }
 619                 break;
 620         case TTM_PL_TT:
 621                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
 622                         man->func = &nouveau_gart_manager;
 623                 else
 624                 if (drm->agp.stat != ENABLED)
 625                         man->func = &nv04_gart_manager;
 626                 else
 627                         man->func = &ttm_bo_manager_func;
 628
 629                 if (drm->agp.stat == ENABLED) {
 630                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 631                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 632                                 TTM_PL_FLAG_WC;
 633                         man->default_caching = TTM_PL_FLAG_WC;
 634                 } else {
 635                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 636                                      TTM_MEMTYPE_FLAG_CMA;
 637                         man->available_caching = TTM_PL_MASK_CACHING;
 638                         man->default_caching = TTM_PL_FLAG_CACHED;
 639                 }
 640
 641                 break;
 642         default:
 643                 return -EINVAL;
 644         }
 645         return 0;
 646 }
 647
 648 static void
 649 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 650 {
 651         struct nouveau_bo *nvbo = nouveau_bo(bo);
 652
 653         switch (bo->mem.mem_type) {
 654         case TTM_PL_VRAM:
 655                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 656                                          TTM_PL_FLAG_SYSTEM);
 657                 break;
 658         default:
 659                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 660                 break;
 661         }
 662
 663         *pl = nvbo->placement;
 664 }
 665
 666
 667 static int
 668 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 669 {
 670         int ret = RING_SPACE(chan, 2);
 671         if (ret == 0) {
 672                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 673                 OUT_RING  (chan, handle & 0x0000ffff);
 674                 FIRE_RING (chan);
 675         }
 676         return ret;
 677 }
 678
 679 static int
 680 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 681                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 682 {
 683         struct nouveau_mem *node = old_mem->mm_node;
 684         int ret = RING_SPACE(chan, 10);
 685         if (ret == 0) {
 686                 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
 687                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 688                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 689                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 690                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 691                 OUT_RING  (chan, PAGE_SIZE);
 692                 OUT_RING  (chan, PAGE_SIZE);
 693                 OUT_RING  (chan, PAGE_SIZE);
 694                 OUT_RING  (chan, new_mem->num_pages);
 695                 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
 696         }
 697         return ret;
 698 }
 699
 700 static int
 701 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
 702 {
 703         int ret = RING_SPACE(chan, 2);
 704         if (ret == 0) {
 705                 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
 706                 OUT_RING  (chan, handle);
 707         }
 708         return ret;
 709 }
 710
 711 static int
 712 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 713                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 714 {
 715         struct nouveau_mem *node = old_mem->mm_node;
 716         u64 src_offset = node->vma[0].offset;
 717         u64 dst_offset = node->vma[1].offset;
 718         u32 page_count = new_mem->num_pages;
 719         int ret;
 720
 721         page_count = new_mem->num_pages;
 722         while (page_count) {
 723                 int line_count = (page_count > 8191) ? 8191 : page_count;
 724
 725                 ret = RING_SPACE(chan, 11);
 726                 if (ret)
 727                         return ret;
 728
 729                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
 730                 OUT_RING  (chan, upper_32_bits(src_offset));
 731                 OUT_RING  (chan, lower_32_bits(src_offset));
 732                 OUT_RING  (chan, upper_32_bits(dst_offset));
 733                 OUT_RING  (chan, lower_32_bits(dst_offset));
 734                 OUT_RING  (chan, PAGE_SIZE);
 735                 OUT_RING  (chan, PAGE_SIZE);
 736                 OUT_RING  (chan, PAGE_SIZE);
 737                 OUT_RING  (chan, line_count);
 738                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 739                 OUT_RING  (chan, 0x00000110);
 740
 741                 page_count -= line_count;
 742                 src_offset += (PAGE_SIZE * line_count);
 743                 dst_offset += (PAGE_SIZE * line_count);
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 751                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 752 {
 753         struct nouveau_mem *node = old_mem->mm_node;
 754         u64 src_offset = node->vma[0].offset;
 755         u64 dst_offset = node->vma[1].offset;
 756         u32 page_count = new_mem->num_pages;
 757         int ret;
 758
 759         page_count = new_mem->num_pages;
 760         while (page_count) {
 761                 int line_count = (page_count > 2047) ? 2047 : page_count;
 762
 763                 ret = RING_SPACE(chan, 12);
 764                 if (ret)
 765                         return ret;
 766
 767                 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
 768                 OUT_RING  (chan, upper_32_bits(dst_offset));
 769                 OUT_RING  (chan, lower_32_bits(dst_offset));
 770                 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
 771                 OUT_RING  (chan, upper_32_bits(src_offset));
 772                 OUT_RING  (chan, lower_32_bits(src_offset));
 773                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 774                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 775                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 776                 OUT_RING  (chan, line_count);
 777                 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
 778                 OUT_RING  (chan, 0x00100110);
 779
 780                 page_count -= line_count;
 781                 src_offset += (PAGE_SIZE * line_count);
 782                 dst_offset += (PAGE_SIZE * line_count);
 783         }
 784
 785         return 0;
 786 }
 787
 788 static int
 789 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 790                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 791 {
 792         struct nouveau_mem *node = old_mem->mm_node;
 793         u64 src_offset = node->vma[0].offset;
 794         u64 dst_offset = node->vma[1].offset;
 795         u32 page_count = new_mem->num_pages;
 796         int ret;
 797
 798         page_count = new_mem->num_pages;
 799         while (page_count) {
 800                 int line_count = (page_count > 8191) ? 8191 : page_count;
 801
 802                 ret = RING_SPACE(chan, 11);
 803                 if (ret)
 804                         return ret;
 805
 806                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 807                 OUT_RING  (chan, upper_32_bits(src_offset));
 808                 OUT_RING  (chan, lower_32_bits(src_offset));
 809                 OUT_RING  (chan, upper_32_bits(dst_offset));
 810                 OUT_RING  (chan, lower_32_bits(dst_offset));
 811                 OUT_RING  (chan, PAGE_SIZE);
 812                 OUT_RING  (chan, PAGE_SIZE);
 813                 OUT_RING  (chan, PAGE_SIZE);
 814                 OUT_RING  (chan, line_count);
 815                 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
 816                 OUT_RING  (chan, 0x00000110);
 817
 818                 page_count -= line_count;
 819                 src_offset += (PAGE_SIZE * line_count);
 820                 dst_offset += (PAGE_SIZE * line_count);
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int
 827 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 828                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 829 {
 830         struct nouveau_mem *node = old_mem->mm_node;
 831         int ret = RING_SPACE(chan, 7);
 832         if (ret == 0) {
 833                 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
 834                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 835                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 836                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 837                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 838                 OUT_RING  (chan, 0x00000000 /* COPY */);
 839                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 840         }
 841         return ret;
 842 }
 843
 844 static int
 845 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 846                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 847 {
 848         struct nouveau_mem *node = old_mem->mm_node;
 849         int ret = RING_SPACE(chan, 7);
 850         if (ret == 0) {
 851                 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
 852                 OUT_RING  (chan, new_mem->num_pages << PAGE_SHIFT);
 853                 OUT_RING  (chan, upper_32_bits(node->vma[0].offset));
 854                 OUT_RING  (chan, lower_32_bits(node->vma[0].offset));
 855                 OUT_RING  (chan, upper_32_bits(node->vma[1].offset));
 856                 OUT_RING  (chan, lower_32_bits(node->vma[1].offset));
 857                 OUT_RING  (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
 858         }
 859         return ret;
 860 }
 861
 862 static int
 863 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
 864 {
 865         int ret = RING_SPACE(chan, 6);
 866         if (ret == 0) {
 867                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 868                 OUT_RING  (chan, handle);
 869                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
 870                 OUT_RING  (chan, chan->drm->ntfy.handle);
 871                 OUT_RING  (chan, chan->vram.handle);
 872                 OUT_RING  (chan, chan->vram.handle);
 873         }
 874
 875         return ret;
 876 }
 877
 878 static int
 879 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 880                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 881 {
 882         struct nouveau_mem *node = old_mem->mm_node;
 883         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 884         u64 src_offset = node->vma[0].offset;
 885         u64 dst_offset = node->vma[1].offset;
 886         int src_tiled = !!node->memtype;
 887         int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
 888         int ret;
 889
 890         while (length) {
 891                 u32 amount, stride, height;
 892
 893                 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
 894                 if (ret)
 895                         return ret;
 896
 897                 amount  = min(length, (u64)(4 * 1024 * 1024));
 898                 stride  = 16 * 4;
 899                 height  = amount / stride;
 900
 901                 if (src_tiled) {
 902                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
 903                         OUT_RING  (chan, 0);
 904                         OUT_RING  (chan, 0);
 905                         OUT_RING  (chan, stride);
 906                         OUT_RING  (chan, height);
 907                         OUT_RING  (chan, 1);
 908                         OUT_RING  (chan, 0);
 909                         OUT_RING  (chan, 0);
 910                 } else {
 911                         BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
 912                         OUT_RING  (chan, 1);
 913                 }
 914                 if (dst_tiled) {
 915                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
 916                         OUT_RING  (chan, 0);
 917                         OUT_RING  (chan, 0);
 918                         OUT_RING  (chan, stride);
 919                         OUT_RING  (chan, height);
 920                         OUT_RING  (chan, 1);
 921                         OUT_RING  (chan, 0);
 922                         OUT_RING  (chan, 0);
 923                 } else {
 924                         BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
 925                         OUT_RING  (chan, 1);
 926                 }
 927
 928                 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
 929                 OUT_RING  (chan, upper_32_bits(src_offset));
 930                 OUT_RING  (chan, upper_32_bits(dst_offset));
 931                 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
 932                 OUT_RING  (chan, lower_32_bits(src_offset));
 933                 OUT_RING  (chan, lower_32_bits(dst_offset));
 934                 OUT_RING  (chan, stride);
 935                 OUT_RING  (chan, stride);
 936                 OUT_RING  (chan, stride);
 937                 OUT_RING  (chan, height);
 938                 OUT_RING  (chan, 0x00000101);
 939                 OUT_RING  (chan, 0x00000000);
 940                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 941                 OUT_RING  (chan, 0);
 942
 943                 length -= amount;
 944                 src_offset += amount;
 945                 dst_offset += amount;
 946         }
 947
 948         return 0;
 949 }
 950
 951 static int
 952 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
 953 {
 954         int ret = RING_SPACE(chan, 4);
 955         if (ret == 0) {
 956                 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
 957                 OUT_RING  (chan, handle);
 958                 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
 959                 OUT_RING  (chan, chan->drm->ntfy.handle);
 960         }
 961
 962         return ret;
 963 }
 964
 965 static inline uint32_t
 966 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 967                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 968 {
 969         if (mem->mem_type == TTM_PL_TT)
 970                 return NvDmaTT;
 971         return chan->vram.handle;
 972 }
 973
 974 static int
 975 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 976                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 977 {
 978         u32 src_offset = old_mem->start << PAGE_SHIFT;
 979         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 980         u32 page_count = new_mem->num_pages;
 981         int ret;
 982
 983         ret = RING_SPACE(chan, 3);
 984         if (ret)
 985                 return ret;
 986
 987         BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 988         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 989         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 990
 991         page_count = new_mem->num_pages;
 992         while (page_count) {
 993                 int line_count = (page_count > 2047) ? 2047 : page_count;
 994
 995                 ret = RING_SPACE(chan, 11);
 996                 if (ret)
 997                         return ret;
 998
 999                 BEGIN_NV04(chan, NvSubCopy,
1000                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1001                 OUT_RING  (chan, src_offset);
1002                 OUT_RING  (chan, dst_offset);
1003                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
1004                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
1005                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
1006                 OUT_RING  (chan, line_count);
1007                 OUT_RING  (chan, 0x00000101);
1008                 OUT_RING  (chan, 0x00000000);
1009                 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1010                 OUT_RING  (chan, 0);
1011
1012                 page_count -= line_count;
1013                 src_offset += (PAGE_SIZE * line_count);
1014                 dst_offset += (PAGE_SIZE * line_count);
1015         }
1016
1017         return 0;
1018 }
1019
1020 static int
1021 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1022                      struct ttm_mem_reg *mem)
1023 {
1024         struct nouveau_mem *old_node = bo->mem.mm_node;
1025         struct nouveau_mem *new_node = mem->mm_node;
1026         u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1027         int ret;
1028
1029         ret = nouveau_vm_get(drm->client.vm, size, old_node->page_shift,
1030                              NV_MEM_ACCESS_RW, &old_node->vma[0]);
1031         if (ret)
1032                 return ret;
1033
1034         ret = nouveau_vm_get(drm->client.vm, size, new_node->page_shift,
1035                              NV_MEM_ACCESS_RW, &old_node->vma[1]);
1036         if (ret) {
1037                 nouveau_vm_put(&old_node->vma[0]);
1038                 return ret;
1039         }
1040
1041         nouveau_vm_map(&old_node->vma[0], old_node);
1042         nouveau_vm_map(&old_node->vma[1], new_node);
1043         return 0;
1044 }
1045
1046 static int
1047 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1048                      bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1049 {
1050         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1051         struct nouveau_channel *chan = drm->ttm.chan;
1052         struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
1053         struct nouveau_fence *fence;
1054         int ret;
1055
1056         /* create temporary vmas for the transfer and attach them to the
1057          * old nouveau_mem node, these will get cleaned up after ttm has
1058          * destroyed the ttm_mem_reg
1059          */
1060         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1061                 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1062                 if (ret)
1063                         return ret;
1064         }
1065
1066         mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1067         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1068         if (ret == 0) {
1069                 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1070                 if (ret == 0) {
1071                         ret = nouveau_fence_new(chan, false, &fence);
1072                         if (ret == 0) {
1073                                 ret = ttm_bo_move_accel_cleanup(bo,
1074                                                                 &fence->base,
1075                                                                 evict,
1076                                                                 no_wait_gpu,
1077                                                                 new_mem);
1078                                 nouveau_fence_unref(&fence);
1079                         }
1080                 }
1081         }
1082         mutex_unlock(&cli->mutex);
1083         return ret;
1084 }
1085
1086 void
1087 nouveau_bo_move_init(struct nouveau_drm *drm)
1088 {
1089         static const struct {
1090                 const char *name;
1091                 int engine;
1092                 u32 oclass;
1093                 int (*exec)(struct nouveau_channel *,
1094                             struct ttm_buffer_object *,
1095                             struct ttm_mem_reg *, struct ttm_mem_reg *);
1096                 int (*init)(struct nouveau_channel *, u32 handle);
1097         } _methods[] = {
1098                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1099                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1100                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1101                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1102                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1103                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1104                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1105                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1106                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1107                 {},
1108                 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1109         }, *mthd = _methods;
1110         const char *name = "CPU";
1111         int ret;
1112
1113         do {
1114                 struct nouveau_channel *chan;
1115
1116                 if (mthd->engine)
1117                         chan = drm->cechan;
1118                 else
1119                         chan = drm->channel;
1120                 if (chan == NULL)
1121                         continue;
1122
1123                 ret = nvif_object_init(chan->object, NULL,
1124                                        mthd->oclass | (mthd->engine << 16),
1125                                        mthd->oclass, NULL, 0,
1126                                        &drm->ttm.copy);
1127                 if (ret == 0) {
1128                         ret = mthd->init(chan, drm->ttm.copy.handle);
1129                         if (ret) {
1130                                 nvif_object_fini(&drm->ttm.copy);
1131                                 continue;
1132                         }
1133
1134                         drm->ttm.move = mthd->exec;
1135                         drm->ttm.chan = chan;
1136                         name = mthd->name;
1137                         break;
1138                 }
1139         } while ((++mthd)->exec);
1140
1141         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1142 }
1143
1144 static int
1145 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1146                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1147 {
1148         struct ttm_place placement_memtype = {
1149                 .fpfn = 0,
1150                 .lpfn = 0,
1151                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1152         };
1153         struct ttm_placement placement;
1154         struct ttm_mem_reg tmp_mem;
1155         int ret;
1156
1157         placement.num_placement = placement.num_busy_placement = 1;
1158         placement.placement = placement.busy_placement = &placement_memtype;
1159
1160         tmp_mem = *new_mem;
1161         tmp_mem.mm_node = NULL;
1162         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1163         if (ret)
1164                 return ret;
1165
1166         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1167         if (ret)
1168                 goto out;
1169
1170         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1171         if (ret)
1172                 goto out;
1173
1174         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1175 out:
1176         ttm_bo_mem_put(bo, &tmp_mem);
1177         return ret;
1178 }
1179
1180 static int
1181 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1182                       bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1183 {
1184         struct ttm_place placement_memtype = {
1185                 .fpfn = 0,
1186                 .lpfn = 0,
1187                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1188         };
1189         struct ttm_placement placement;
1190         struct ttm_mem_reg tmp_mem;
1191         int ret;
1192
1193         placement.num_placement = placement.num_busy_placement = 1;
1194         placement.placement = placement.busy_placement = &placement_memtype;
1195
1196         tmp_mem = *new_mem;
1197         tmp_mem.mm_node = NULL;
1198         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1199         if (ret)
1200                 return ret;
1201
1202         ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1203         if (ret)
1204                 goto out;
1205
1206         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1207         if (ret)
1208                 goto out;
1209
1210 out:
1211         ttm_bo_mem_put(bo, &tmp_mem);
1212         return ret;
1213 }
1214
1215 static void
1216 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1217 {
1218         struct nouveau_bo *nvbo = nouveau_bo(bo);
1219         struct nouveau_vma *vma;
1220
1221         /* ttm can now (stupidly) pass the driver bos it didn't create... */
1222         if (bo->destroy != nouveau_bo_del_ttm)
1223                 return;
1224
1225         list_for_each_entry(vma, &nvbo->vma_list, head) {
1226                 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1227                               (new_mem->mem_type == TTM_PL_VRAM ||
1228                                nvbo->page_shift != vma->vm->vmm->lpg_shift)) {
1229                         nouveau_vm_map(vma, new_mem->mm_node);
1230                 } else {
1231                         nouveau_vm_unmap(vma);
1232                 }
1233         }
1234 }
1235
1236 static int
1237 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1238                    struct nouveau_drm_tile **new_tile)
1239 {
1240         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1241         struct drm_device *dev = drm->dev;
1242         struct nouveau_bo *nvbo = nouveau_bo(bo);
1243         u64 offset = new_mem->start << PAGE_SHIFT;
1244
1245         *new_tile = NULL;
1246         if (new_mem->mem_type != TTM_PL_VRAM)
1247                 return 0;
1248
1249         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1250                 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1251                                                 nvbo->tile_mode,
1252                                                 nvbo->tile_flags);
1253         }
1254
1255         return 0;
1256 }
1257
1258 static void
1259 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1260                       struct nouveau_drm_tile *new_tile,
1261                       struct nouveau_drm_tile **old_tile)
1262 {
1263         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1264         struct drm_device *dev = drm->dev;
1265         struct fence *fence = reservation_object_get_excl(bo->resv);
1266
1267         nv10_bo_put_tile_region(dev, *old_tile, fence);
1268         *old_tile = new_tile;
1269 }
1270
1271 static int
1272 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1273                 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1274 {
1275         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1276         struct nouveau_bo *nvbo = nouveau_bo(bo);
1277         struct ttm_mem_reg *old_mem = &bo->mem;
1278         struct nouveau_drm_tile *new_tile = NULL;
1279         int ret = 0;
1280
1281         if (nvbo->pin_refcnt)
1282                 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1283
1284         if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1285                 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1286                 if (ret)
1287                         return ret;
1288         }
1289
1290         /* Fake bo copy. */
1291         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1292                 BUG_ON(bo->mem.mm_node != NULL);
1293                 bo->mem = *new_mem;
1294                 new_mem->mm_node = NULL;
1295                 goto out;
1296         }
1297
1298         /* Hardware assisted copy. */
1299         if (drm->ttm.move) {
1300                 if (new_mem->mem_type == TTM_PL_SYSTEM)
1301                         ret = nouveau_bo_move_flipd(bo, evict, intr,
1302                                                     no_wait_gpu, new_mem);
1303                 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1304                         ret = nouveau_bo_move_flips(bo, evict, intr,
1305                                                     no_wait_gpu, new_mem);
1306                 else
1307                         ret = nouveau_bo_move_m2mf(bo, evict, intr,
1308                                                    no_wait_gpu, new_mem);
1309                 if (!ret)
1310                         goto out;
1311         }
1312
1313         /* Fallback to software copy. */
1314         ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1315         if (ret == 0)
1316                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1317
1318 out:
1319         if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1320                 if (ret)
1321                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1322                 else
1323                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1324         }
1325
1326         return ret;
1327 }
1328
1329 static int
1330 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1331 {
1332         struct nouveau_bo *nvbo = nouveau_bo(bo);
1333
1334         return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1335 }
1336
1337 static int
1338 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1339 {
1340         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1341         struct nouveau_drm *drm = nouveau_bdev(bdev);
1342         struct nouveau_mem *node = mem->mm_node;
1343         int ret;
1344
1345         mem->bus.addr = NULL;
1346         mem->bus.offset = 0;
1347         mem->bus.size = mem->num_pages << PAGE_SHIFT;
1348         mem->bus.base = 0;
1349         mem->bus.is_iomem = false;
1350         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1351                 return -EINVAL;
1352         switch (mem->mem_type) {
1353         case TTM_PL_SYSTEM:
1354                 /* System memory */
1355                 return 0;
1356         case TTM_PL_TT:
1357 #if __OS_HAS_AGP
1358                 if (drm->agp.stat == ENABLED) {
1359                         mem->bus.offset = mem->start << PAGE_SHIFT;
1360                         mem->bus.base = drm->agp.base;
1361                         mem->bus.is_iomem = !drm->dev->agp->cant_use_aperture;
1362                 }
1363 #endif
1364                 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1365                         /* untiled */
1366                         break;
1367                 /* fallthrough, tiled memory */
1368         case TTM_PL_VRAM:
1369                 mem->bus.offset = mem->start << PAGE_SHIFT;
1370                 mem->bus.base = nv_device_resource_start(nvkm_device(&drm->device), 1);
1371                 mem->bus.is_iomem = true;
1372                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1373                         struct nouveau_bar *bar = nvkm_bar(&drm->device);
1374
1375                         ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1376                                         &node->bar_vma);
1377                         if (ret)
1378                                 return ret;
1379
1380                         mem->bus.offset = node->bar_vma.offset;
1381                 }
1382                 break;
1383         default:
1384                 return -EINVAL;
1385         }
1386         return 0;
1387 }
1388
1389 static void
1390 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1391 {
1392         struct nouveau_drm *drm = nouveau_bdev(bdev);
1393         struct nouveau_bar *bar = nvkm_bar(&drm->device);
1394         struct nouveau_mem *node = mem->mm_node;
1395
1396         if (!node->bar_vma.node)
1397                 return;
1398
1399         bar->unmap(bar, &node->bar_vma);
1400 }
1401
1402 static int
1403 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1404 {
1405         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1406         struct nouveau_bo *nvbo = nouveau_bo(bo);
1407         struct nvif_device *device = &drm->device;
1408         u32 mappable = nv_device_resource_len(nvkm_device(device), 1) >> PAGE_SHIFT;
1409         int i, ret;
1410
1411         /* as long as the bo isn't in vram, and isn't tiled, we've got
1412          * nothing to do here.
1413          */
1414         if (bo->mem.mem_type != TTM_PL_VRAM) {
1415                 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1416                     !nouveau_bo_tile_layout(nvbo))
1417                         return 0;
1418
1419                 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1420                         nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1421
1422                         ret = nouveau_bo_validate(nvbo, false, false);
1423                         if (ret)
1424                                 return ret;
1425                 }
1426                 return 0;
1427         }
1428
1429         /* make sure bo is in mappable vram */
1430         if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1431             bo->mem.start + bo->mem.num_pages < mappable)
1432                 return 0;
1433
1434         for (i = 0; i < nvbo->placement.num_placement; ++i) {
1435                 nvbo->placements[i].fpfn = 0;
1436                 nvbo->placements[i].lpfn = mappable;
1437         }
1438
1439         for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1440                 nvbo->busy_placements[i].fpfn = 0;
1441                 nvbo->busy_placements[i].lpfn = mappable;
1442         }
1443
1444         nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1445         return nouveau_bo_validate(nvbo, false, false);
1446 }
1447
1448 static int
1449 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1450 {
1451         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1452         struct nouveau_drm *drm;
1453         struct nouveau_device *device;
1454         struct drm_device *dev;
1455         struct device *pdev;
1456         unsigned i;
1457         int r;
1458         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1459
1460         if (ttm->state != tt_unpopulated)
1461                 return 0;
1462
1463         if (slave && ttm->sg) {
1464                 /* make userspace faulting work */
1465                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1466                                                  ttm_dma->dma_address, ttm->num_pages);
1467                 ttm->state = tt_unbound;
1468                 return 0;
1469         }
1470
1471         drm = nouveau_bdev(ttm->bdev);
1472         device = nvkm_device(&drm->device);
1473         dev = drm->dev;
1474         pdev = nv_device_base(device);
1475
1476         /*
1477          * Objects matching this condition have been marked as force_coherent,
1478          * so use the DMA API for them.
1479          */
1480         if (!nv_device_is_cpu_coherent(device) &&
1481             ttm->caching_state == tt_uncached)
1482                 return ttm_dma_populate(ttm_dma, dev->dev);
1483
1484 #if __OS_HAS_AGP
1485         if (drm->agp.stat == ENABLED) {
1486                 return ttm_agp_tt_populate(ttm);
1487         }
1488 #endif
1489
1490 #ifdef CONFIG_SWIOTLB
1491         if (swiotlb_nr_tbl()) {
1492                 return ttm_dma_populate((void *)ttm, dev->dev);
1493         }
1494 #endif
1495
1496         r = ttm_pool_populate(ttm);
1497         if (r) {
1498                 return r;
1499         }
1500
1501         for (i = 0; i < ttm->num_pages; i++) {
1502                 dma_addr_t addr;
1503
1504                 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1505                                     DMA_BIDIRECTIONAL);
1506
1507                 if (dma_mapping_error(pdev, addr)) {
1508                         while (--i) {
1509                                 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1510                                                PAGE_SIZE, DMA_BIDIRECTIONAL);
1511                                 ttm_dma->dma_address[i] = 0;
1512                         }
1513                         ttm_pool_unpopulate(ttm);
1514                         return -EFAULT;
1515                 }
1516
1517                 ttm_dma->dma_address[i] = addr;
1518         }
1519         return 0;
1520 }
1521
1522 static void
1523 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1524 {
1525         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1526         struct nouveau_drm *drm;
1527         struct nouveau_device *device;
1528         struct drm_device *dev;
1529         struct device *pdev;
1530         unsigned i;
1531         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1532
1533         if (slave)
1534                 return;
1535
1536         drm = nouveau_bdev(ttm->bdev);
1537         device = nvkm_device(&drm->device);
1538         dev = drm->dev;
1539         pdev = nv_device_base(device);
1540
1541         /*
1542          * Objects matching this condition have been marked as force_coherent,
1543          * so use the DMA API for them.
1544          */
1545         if (!nv_device_is_cpu_coherent(device) &&
1546             ttm->caching_state == tt_uncached)
1547                 ttm_dma_unpopulate(ttm_dma, dev->dev);
1548
1549 #if __OS_HAS_AGP
1550         if (drm->agp.stat == ENABLED) {
1551                 ttm_agp_tt_unpopulate(ttm);
1552                 return;
1553         }
1554 #endif
1555
1556 #ifdef CONFIG_SWIOTLB
1557         if (swiotlb_nr_tbl()) {
1558                 ttm_dma_unpopulate((void *)ttm, dev->dev);
1559                 return;
1560         }
1561 #endif
1562
1563         for (i = 0; i < ttm->num_pages; i++) {
1564                 if (ttm_dma->dma_address[i]) {
1565                         dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1566                                        DMA_BIDIRECTIONAL);
1567                 }
1568         }
1569
1570         ttm_pool_unpopulate(ttm);
1571 }
1572
1573 void
1574 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1575 {
1576         struct reservation_object *resv = nvbo->bo.resv;
1577
1578         if (exclusive)
1579                 reservation_object_add_excl_fence(resv, &fence->base);
1580         else if (fence)
1581                 reservation_object_add_shared_fence(resv, &fence->base);
1582 }
1583
1584 struct ttm_bo_driver nouveau_bo_driver = {
1585         .ttm_tt_create = &nouveau_ttm_tt_create,
1586         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1587         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1588         .invalidate_caches = nouveau_bo_invalidate_caches,
1589         .init_mem_type = nouveau_bo_init_mem_type,
1590         .evict_flags = nouveau_bo_evict_flags,
1591         .move_notify = nouveau_bo_move_ntfy,
1592         .move = nouveau_bo_move,
1593         .verify_access = nouveau_bo_verify_access,
1594         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1595         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1596         .io_mem_free = &nouveau_ttm_io_mem_free,
1597 };
1598
1599 struct nouveau_vma *
1600 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1601 {
1602         struct nouveau_vma *vma;
1603         list_for_each_entry(vma, &nvbo->vma_list, head) {
1604                 if (vma->vm == vm)
1605                         return vma;
1606         }
1607
1608         return NULL;
1609 }
1610
1611 int
1612 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1613                    struct nouveau_vma *vma)
1614 {
1615         const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1616         int ret;
1617
1618         ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1619                              NV_MEM_ACCESS_RW, vma);
1620         if (ret)
1621                 return ret;
1622
1623         if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1624             (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1625              nvbo->page_shift != vma->vm->vmm->lpg_shift))
1626                 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1627
1628         list_add_tail(&vma->head, &nvbo->vma_list);
1629         vma->refcount = 1;
1630         return 0;
1631 }
1632
1633 void
1634 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1635 {
1636         if (vma->node) {
1637                 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1638                         nouveau_vm_unmap(vma);
1639                 nouveau_vm_put(vma);
1640                 list_del(&vma->head);
1641         }
1642 }