drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/swiotlb.h>
  32
  33 #include "nouveau_drv.h"
  34 #include "nouveau_chan.h"
  35 #include "nouveau_fence.h"
  36
  37 #include "nouveau_bo.h"
  38 #include "nouveau_ttm.h"
  39 #include "nouveau_gem.h"
  40 #include "nouveau_mem.h"
  41 #include "nouveau_vmm.h"
  42
  43 #include <nvif/class.h>
  44 #include <nvif/if500b.h>
  45 #include <nvif/if900b.h>
  46
  47 /*
  48  * NV10-NV40 tiling helpers
  49  */
  50
  51 static void
  52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
  53                            u32 addr, u32 size, u32 pitch, u32 flags)
  54 {
  55         struct nouveau_drm *drm = nouveau_drm(dev);
  56         int i = reg - drm->tile.reg;
  57         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
  58         struct nvkm_fb_tile *tile = &fb->tile.region[i];
  59
  60         nouveau_fence_unref(&reg->fence);
  61
  62         if (tile->pitch)
  63                 nvkm_fb_tile_fini(fb, i, tile);
  64
  65         if (pitch)
  66                 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
  67
  68         nvkm_fb_tile_prog(fb, i, tile);
  69 }
  70
  71 static struct nouveau_drm_tile *
  72 nv10_bo_get_tile_region(struct drm_device *dev, int i)
  73 {
  74         struct nouveau_drm *drm = nouveau_drm(dev);
  75         struct nouveau_drm_tile *tile = &drm->tile.reg[i];
  76
  77         spin_lock(&drm->tile.lock);
  78
  79         if (!tile->used &&
  80             (!tile->fence || nouveau_fence_done(tile->fence)))
  81                 tile->used = true;
  82         else
  83                 tile = NULL;
  84
  85         spin_unlock(&drm->tile.lock);
  86         return tile;
  87 }
  88
  89 static void
  90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
  91                         struct dma_fence *fence)
  92 {
  93         struct nouveau_drm *drm = nouveau_drm(dev);
  94
  95         if (tile) {
  96                 spin_lock(&drm->tile.lock);
  97                 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
  98                 tile->used = false;
  99                 spin_unlock(&drm->tile.lock);
 100         }
 101 }
 102
 103 static struct nouveau_drm_tile *
 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
 105                    u32 size, u32 pitch, u32 zeta)
 106 {
 107         struct nouveau_drm *drm = nouveau_drm(dev);
 108         struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
 109         struct nouveau_drm_tile *tile, *found = NULL;
 110         int i;
 111
 112         for (i = 0; i < fb->tile.regions; i++) {
 113                 tile = nv10_bo_get_tile_region(dev, i);
 114
 115                 if (pitch && !found) {
 116                         found = tile;
 117                         continue;
 118
 119                 } else if (tile && fb->tile.region[i].pitch) {
 120                         /* Kill an unused tile region. */
 121                         nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
 122                 }
 123
 124                 nv10_bo_put_tile_region(dev, tile, NULL);
 125         }
 126
 127         if (found)
 128                 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
 129         return found;
 130 }
 131
 132 static void
 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
 134 {
 135         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 136         struct drm_device *dev = drm->dev;
 137         struct nouveau_bo *nvbo = nouveau_bo(bo);
 138
 139         WARN_ON(nvbo->pin_refcnt > 0);
 140         nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
 141
 142         /*
 143          * If nouveau_bo_new() allocated this buffer, the GEM object was never
 144          * initialized, so don't attempt to release it.
 145          */
 146         if (bo->base.dev)
 147                 drm_gem_object_release(&bo->base);
 148
 149         kfree(nvbo);
 150 }
 151
 152 static inline u64
 153 roundup_64(u64 x, u32 y)
 154 {
 155         x += y - 1;
 156         do_div(x, y);
 157         return x * y;
 158 }
 159
 160 static void
 161 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
 162                        int *align, u64 *size)
 163 {
 164         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 165         struct nvif_device *device = &drm->client.device;
 166
 167         if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
 168                 if (nvbo->mode) {
 169                         if (device->info.chipset >= 0x40) {
 170                                 *align = 65536;
 171                                 *size = roundup_64(*size, 64 * nvbo->mode);
 172
 173                         } else if (device->info.chipset >= 0x30) {
 174                                 *align = 32768;
 175                                 *size = roundup_64(*size, 64 * nvbo->mode);
 176
 177                         } else if (device->info.chipset >= 0x20) {
 178                                 *align = 16384;
 179                                 *size = roundup_64(*size, 64 * nvbo->mode);
 180
 181                         } else if (device->info.chipset >= 0x10) {
 182                                 *align = 16384;
 183                                 *size = roundup_64(*size, 32 * nvbo->mode);
 184                         }
 185                 }
 186         } else {
 187                 *size = roundup_64(*size, (1 << nvbo->page));
 188                 *align = max((1 <<  nvbo->page), *align);
 189         }
 190
 191         *size = roundup_64(*size, PAGE_SIZE);
 192 }
 193
 194 struct nouveau_bo *
 195 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags,
 196                  u32 tile_mode, u32 tile_flags)
 197 {
 198         struct nouveau_drm *drm = cli->drm;
 199         struct nouveau_bo *nvbo;
 200         struct nvif_mmu *mmu = &cli->mmu;
 201         struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
 202         int i, pi = -1;
 203
 204         if (!*size) {
 205                 NV_WARN(drm, "skipped size %016llx\n", *size);
 206                 return ERR_PTR(-EINVAL);
 207         }
 208
 209         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 210         if (!nvbo)
 211                 return ERR_PTR(-ENOMEM);
 212         INIT_LIST_HEAD(&nvbo->head);
 213         INIT_LIST_HEAD(&nvbo->entry);
 214         INIT_LIST_HEAD(&nvbo->vma_list);
 215         nvbo->bo.bdev = &drm->ttm.bdev;
 216
 217         /* This is confusing, and doesn't actually mean we want an uncached
 218          * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
 219          * into in nouveau_gem_new().
 220          */
 221         if (flags & TTM_PL_FLAG_UNCACHED) {
 222                 /* Determine if we can get a cache-coherent map, forcing
 223                  * uncached mapping if we can't.
 224                  */
 225                 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
 226                         nvbo->force_coherent = true;
 227         }
 228
 229         if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
 230                 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
 231                 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 232                         kfree(nvbo);
 233                         return ERR_PTR(-EINVAL);
 234                 }
 235
 236                 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
 237         } else
 238         if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 239                 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
 240                 nvbo->comp = (tile_flags & 0x00030000) >> 16;
 241                 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
 242                         kfree(nvbo);
 243                         return ERR_PTR(-EINVAL);
 244                 }
 245         } else {
 246                 nvbo->zeta = (tile_flags & 0x00000007);
 247         }
 248         nvbo->mode = tile_mode;
 249         nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
 250
 251         /* Determine the desirable target GPU page size for the buffer. */
 252         for (i = 0; i < vmm->page_nr; i++) {
 253                 /* Because we cannot currently allow VMM maps to fail
 254                  * during buffer migration, we need to determine page
 255                  * size for the buffer up-front, and pre-allocate its
 256                  * page tables.
 257                  *
 258                  * Skip page sizes that can't support needed domains.
 259                  */
 260                 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
 261                     (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram)
 262                         continue;
 263                 if ((flags & TTM_PL_FLAG_TT) &&
 264                     (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
 265                         continue;
 266
 267                 /* Select this page size if it's the first that supports
 268                  * the potential memory domains, or when it's compatible
 269                  * with the requested compression settings.
 270                  */
 271                 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
 272                         pi = i;
 273
 274                 /* Stop once the buffer is larger than the current page size. */
 275                 if (*size >= 1ULL << vmm->page[i].shift)
 276                         break;
 277         }
 278
 279         if (WARN_ON(pi < 0))
 280                 return ERR_PTR(-EINVAL);
 281
 282         /* Disable compression if suitable settings couldn't be found. */
 283         if (nvbo->comp && !vmm->page[pi].comp) {
 284                 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
 285                         nvbo->kind = mmu->kind[nvbo->kind];
 286                 nvbo->comp = 0;
 287         }
 288         nvbo->page = vmm->page[pi].shift;
 289
 290         nouveau_bo_fixup_align(nvbo, flags, align, size);
 291
 292         return nvbo;
 293 }
 294
 295 int
 296 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 flags,
 297                 struct sg_table *sg, struct dma_resv *robj)
 298 {
 299         int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
 300         size_t acc_size;
 301         int ret;
 302
 303         acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
 304
 305         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 306         nouveau_bo_placement_set(nvbo, flags, 0);
 307
 308         ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
 309                           &nvbo->placement, align >> PAGE_SHIFT, false,
 310                           acc_size, sg, robj, nouveau_bo_del_ttm);
 311         if (ret) {
 312                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 313                 return ret;
 314         }
 315
 316         return 0;
 317 }
 318
 319 int
 320 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
 321                uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
 322                struct sg_table *sg, struct dma_resv *robj,
 323                struct nouveau_bo **pnvbo)
 324 {
 325         struct nouveau_bo *nvbo;
 326         int ret;
 327
 328         nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode,
 329                                 tile_flags);
 330         if (IS_ERR(nvbo))
 331                 return PTR_ERR(nvbo);
 332
 333         ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj);
 334         if (ret)
 335                 return ret;
 336
 337         *pnvbo = nvbo;
 338         return 0;
 339 }
 340
 341 static void
 342 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
 343 {
 344         *n = 0;
 345
 346         if (type & TTM_PL_FLAG_VRAM)
 347                 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
 348         if (type & TTM_PL_FLAG_TT)
 349                 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
 350         if (type & TTM_PL_FLAG_SYSTEM)
 351                 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
 352 }
 353
 354 static void
 355 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 356 {
 357         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 358         u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
 359         unsigned i, fpfn, lpfn;
 360
 361         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
 362             nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
 363             nvbo->bo.mem.num_pages < vram_pages / 4) {
 364                 /*
 365                  * Make sure that the color and depth buffers are handled
 366                  * by independent memory controller units. Up to a 9x
 367                  * speed up when alpha-blending and depth-test are enabled
 368                  * at the same time.
 369                  */
 370                 if (nvbo->zeta) {
 371                         fpfn = vram_pages / 2;
 372                         lpfn = ~0;
 373                 } else {
 374                         fpfn = 0;
 375                         lpfn = vram_pages / 2;
 376                 }
 377                 for (i = 0; i < nvbo->placement.num_placement; ++i) {
 378                         nvbo->placements[i].fpfn = fpfn;
 379                         nvbo->placements[i].lpfn = lpfn;
 380                 }
 381                 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
 382                         nvbo->busy_placements[i].fpfn = fpfn;
 383                         nvbo->busy_placements[i].lpfn = lpfn;
 384                 }
 385         }
 386 }
 387
 388 void
 389 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 390 {
 391         struct ttm_placement *pl = &nvbo->placement;
 392         uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
 393                                                  TTM_PL_MASK_CACHING) |
 394                          (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 395
 396         pl->placement = nvbo->placements;
 397         set_placement_list(nvbo->placements, &pl->num_placement,
 398                            type, flags);
 399
 400         pl->busy_placement = nvbo->busy_placements;
 401         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 402                            type | busy, flags);
 403
 404         set_placement_range(nvbo, type);
 405 }
 406
 407 int
 408 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
 409 {
 410         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 411         struct ttm_buffer_object *bo = &nvbo->bo;
 412         bool force = false, evict = false;
 413         int ret;
 414
 415         ret = ttm_bo_reserve(bo, false, false, NULL);
 416         if (ret)
 417                 return ret;
 418
 419         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
 420             memtype == TTM_PL_FLAG_VRAM && contig) {
 421                 if (!nvbo->contig) {
 422                         nvbo->contig = true;
 423                         force = true;
 424                         evict = true;
 425                 }
 426         }
 427
 428         if (nvbo->pin_refcnt) {
 429                 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
 430                         NV_ERROR(drm, "bo %p pinned elsewhere: "
 431                                       "0x%08x vs 0x%08x\n", bo,
 432                                  1 << bo->mem.mem_type, memtype);
 433                         ret = -EBUSY;
 434                 }
 435                 nvbo->pin_refcnt++;
 436                 goto out;
 437         }
 438
 439         if (evict) {
 440                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
 441                 ret = nouveau_bo_validate(nvbo, false, false);
 442                 if (ret)
 443                         goto out;
 444         }
 445
 446         nvbo->pin_refcnt++;
 447         nouveau_bo_placement_set(nvbo, memtype, 0);
 448
 449         /* drop pin_refcnt temporarily, so we don't trip the assertion
 450          * in nouveau_bo_move() that makes sure we're not trying to
 451          * move a pinned buffer
 452          */
 453         nvbo->pin_refcnt--;
 454         ret = nouveau_bo_validate(nvbo, false, false);
 455         if (ret)
 456                 goto out;
 457         nvbo->pin_refcnt++;
 458
 459         switch (bo->mem.mem_type) {
 460         case TTM_PL_VRAM:
 461                 drm->gem.vram_available -= bo->mem.size;
 462                 break;
 463         case TTM_PL_TT:
 464                 drm->gem.gart_available -= bo->mem.size;
 465                 break;
 466         default:
 467                 break;
 468         }
 469
 470 out:
 471         if (force && ret)
 472                 nvbo->contig = false;
 473         ttm_bo_unreserve(bo);
 474         return ret;
 475 }
 476
 477 int
 478 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 479 {
 480         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 481         struct ttm_buffer_object *bo = &nvbo->bo;
 482         int ret, ref;
 483
 484         ret = ttm_bo_reserve(bo, false, false, NULL);
 485         if (ret)
 486                 return ret;
 487
 488         ref = --nvbo->pin_refcnt;
 489         WARN_ON_ONCE(ref < 0);
 490         if (ref)
 491                 goto out;
 492
 493         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 494
 495         ret = nouveau_bo_validate(nvbo, false, false);
 496         if (ret == 0) {
 497                 switch (bo->mem.mem_type) {
 498                 case TTM_PL_VRAM:
 499                         drm->gem.vram_available += bo->mem.size;
 500                         break;
 501                 case TTM_PL_TT:
 502                         drm->gem.gart_available += bo->mem.size;
 503                         break;
 504                 default:
 505                         break;
 506                 }
 507         }
 508
 509 out:
 510         ttm_bo_unreserve(bo);
 511         return ret;
 512 }
 513
 514 int
 515 nouveau_bo_map(struct nouveau_bo *nvbo)
 516 {
 517         int ret;
 518
 519         ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
 520         if (ret)
 521                 return ret;
 522
 523         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 524
 525         ttm_bo_unreserve(&nvbo->bo);
 526         return ret;
 527 }
 528
 529 void
 530 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 531 {
 532         if (!nvbo)
 533                 return;
 534
 535         ttm_bo_kunmap(&nvbo->kmap);
 536 }
 537
 538 void
 539 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
 540 {
 541         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 542         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 543         int i;
 544
 545         if (!ttm_dma)
 546                 return;
 547
 548         /* Don't waste time looping if the object is coherent */
 549         if (nvbo->force_coherent)
 550                 return;
 551
 552         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 553                 dma_sync_single_for_device(drm->dev->dev,
 554                                            ttm_dma->dma_address[i],
 555                                            PAGE_SIZE, DMA_TO_DEVICE);
 556 }
 557
 558 void
 559 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
 560 {
 561         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
 562         struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
 563         int i;
 564
 565         if (!ttm_dma)
 566                 return;
 567
 568         /* Don't waste time looping if the object is coherent */
 569         if (nvbo->force_coherent)
 570                 return;
 571
 572         for (i = 0; i < ttm_dma->ttm.num_pages; i++)
 573                 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
 574                                         PAGE_SIZE, DMA_FROM_DEVICE);
 575 }
 576
 577 int
 578 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 579                     bool no_wait_gpu)
 580 {
 581         struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
 582         int ret;
 583
 584         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
 585         if (ret)
 586                 return ret;
 587
 588         nouveau_bo_sync_for_device(nvbo);
 589
 590         return 0;
 591 }
 592
 593 void
 594 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 595 {
 596         bool is_iomem;
 597         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 598
 599         mem += index;
 600
 601         if (is_iomem)
 602                 iowrite16_native(val, (void __force __iomem *)mem);
 603         else
 604                 *mem = val;
 605 }
 606
 607 u32
 608 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 609 {
 610         bool is_iomem;
 611         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 612
 613         mem += index;
 614
 615         if (is_iomem)
 616                 return ioread32_native((void __force __iomem *)mem);
 617         else
 618                 return *mem;
 619 }
 620
 621 void
 622 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 623 {
 624         bool is_iomem;
 625         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 626
 627         mem += index;
 628
 629         if (is_iomem)
 630                 iowrite32_native(val, (void __force __iomem *)mem);
 631         else
 632                 *mem = val;
 633 }
 634
 635 static struct ttm_tt *
 636 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
 637 {
 638 #if IS_ENABLED(CONFIG_AGP)
 639         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 640
 641         if (drm->agp.bridge) {
 642                 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
 643         }
 644 #endif
 645
 646         return nouveau_sgdma_create_ttm(bo, page_flags);
 647 }
 648
 649 static int
 650 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 651                          struct ttm_mem_type_manager *man)
 652 {
 653         struct nouveau_drm *drm = nouveau_bdev(bdev);
 654         struct nvif_mmu *mmu = &drm->client.mmu;
 655
 656         switch (type) {
 657         case TTM_PL_SYSTEM:
 658                 man->flags = 0;
 659                 man->available_caching = TTM_PL_MASK_CACHING;
 660                 man->default_caching = TTM_PL_FLAG_CACHED;
 661                 break;
 662         case TTM_PL_VRAM:
 663                 man->flags = TTM_MEMTYPE_FLAG_FIXED;
 664                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 665                                          TTM_PL_FLAG_WC;
 666                 man->default_caching = TTM_PL_FLAG_WC;
 667
 668                 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 669                         /* Some BARs do not support being ioremapped WC */
 670                         const u8 type = mmu->type[drm->ttm.type_vram].type;
 671                         if (type & NVIF_MEM_UNCACHED) {
 672                                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 673                                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 674                         }
 675
 676                         man->func = &nouveau_vram_manager;
 677                         man->use_io_reserve_lru = true;
 678                 } else {
 679                         man->func = &ttm_bo_manager_func;
 680                 }
 681                 break;
 682         case TTM_PL_TT:
 683                 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA)
 684                         man->func = &nouveau_gart_manager;
 685                 else
 686                 if (!drm->agp.bridge)
 687                         man->func = &nv04_gart_manager;
 688                 else
 689                         man->func = &ttm_bo_manager_func;
 690
 691                 if (drm->agp.bridge) {
 692                         man->flags = 0;
 693                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 694                                 TTM_PL_FLAG_WC;
 695                         man->default_caching = TTM_PL_FLAG_WC;
 696                 } else {
 697                         man->flags = 0;
 698                         man->available_caching = TTM_PL_MASK_CACHING;
 699                         man->default_caching = TTM_PL_FLAG_CACHED;
 700                 }
 701
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706         return 0;
 707 }
 708
 709 static void
 710 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 711 {
 712         struct nouveau_bo *nvbo = nouveau_bo(bo);
 713
 714         switch (bo->mem.mem_type) {
 715         case TTM_PL_VRAM:
 716                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 717                                          TTM_PL_FLAG_SYSTEM);
 718                 break;
 719         default:
 720                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 721                 break;
 722         }
 723
 724         *pl = nvbo->placement;
 725 }
 726
 727 static int
 728 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
 729                      struct ttm_mem_reg *reg)
 730 {
 731         struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
 732         struct nouveau_mem *new_mem = nouveau_mem(reg);
 733         struct nvif_vmm *vmm = &drm->client.vmm.vmm;
 734         int ret;
 735
 736         ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
 737                            old_mem->mem.size, &old_mem->vma[0]);
 738         if (ret)
 739                 return ret;
 740
 741         ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
 742                            new_mem->mem.size, &old_mem->vma[1]);
 743         if (ret)
 744                 goto done;
 745
 746         ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
 747         if (ret)
 748                 goto done;
 749
 750         ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
 751 done:
 752         if (ret) {
 753                 nvif_vmm_put(vmm, &old_mem->vma[1]);
 754                 nvif_vmm_put(vmm, &old_mem->vma[0]);
 755         }
 756         return 0;
 757 }
 758
 759 static int
 760 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 761                      bool no_wait_gpu, struct ttm_mem_reg *new_reg)
 762 {
 763         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 764         struct nouveau_channel *chan = drm->ttm.chan;
 765         struct nouveau_cli *cli = (void *)chan->user.client;
 766         struct nouveau_fence *fence;
 767         int ret;
 768
 769         /* create temporary vmas for the transfer and attach them to the
 770          * old nvkm_mem node, these will get cleaned up after ttm has
 771          * destroyed the ttm_mem_reg
 772          */
 773         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
 774                 ret = nouveau_bo_move_prep(drm, bo, new_reg);
 775                 if (ret)
 776                         return ret;
 777         }
 778
 779         mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
 780         ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
 781         if (ret == 0) {
 782                 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
 783                 if (ret == 0) {
 784                         ret = nouveau_fence_new(chan, false, &fence);
 785                         if (ret == 0) {
 786                                 ret = ttm_bo_move_accel_cleanup(bo,
 787                                                                 &fence->base,
 788                                                                 evict,
 789                                                                 new_reg);
 790                                 nouveau_fence_unref(&fence);
 791                         }
 792                 }
 793         }
 794         mutex_unlock(&cli->mutex);
 795         return ret;
 796 }
 797
 798 void
 799 nouveau_bo_move_init(struct nouveau_drm *drm)
 800 {
 801         static const struct _method_table {
 802                 const char *name;
 803                 int engine;
 804                 s32 oclass;
 805                 int (*exec)(struct nouveau_channel *,
 806                             struct ttm_buffer_object *,
 807                             struct ttm_mem_reg *, struct ttm_mem_reg *);
 808                 int (*init)(struct nouveau_channel *, u32 handle);
 809         } _methods[] = {
 810                 {  "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
 811                 {  "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
 812                 {  "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
 813                 {  "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
 814                 {  "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
 815                 {  "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
 816                 {  "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
 817                 {  "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 818                 {  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
 819                 {  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 820                 {  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
 821                 {  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
 822                 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
 823                 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
 824                 {  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
 825                 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
 826                 {  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
 827                 {  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
 828                 {  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
 829                 {},
 830         };
 831         const struct _method_table *mthd = _methods;
 832         const char *name = "CPU";
 833         int ret;
 834
 835         do {
 836                 struct nouveau_channel *chan;
 837
 838                 if (mthd->engine)
 839                         chan = drm->cechan;
 840                 else
 841                         chan = drm->channel;
 842                 if (chan == NULL)
 843                         continue;
 844
 845                 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
 846                                        mthd->oclass | (mthd->engine << 16),
 847                                        mthd->oclass, NULL, 0,
 848                                        &drm->ttm.copy);
 849                 if (ret == 0) {
 850                         ret = mthd->init(chan, drm->ttm.copy.handle);
 851                         if (ret) {
 852                                 nvif_object_dtor(&drm->ttm.copy);
 853                                 continue;
 854                         }
 855
 856                         drm->ttm.move = mthd->exec;
 857                         drm->ttm.chan = chan;
 858                         name = mthd->name;
 859                         break;
 860                 }
 861         } while ((++mthd)->exec);
 862
 863         NV_INFO(drm, "MM: using %s for buffer copies\n", name);
 864 }
 865
 866 static int
 867 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 868                       bool no_wait_gpu, struct ttm_mem_reg *new_reg)
 869 {
 870         struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
 871         struct ttm_place placement_memtype = {
 872                 .fpfn = 0,
 873                 .lpfn = 0,
 874                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
 875         };
 876         struct ttm_placement placement;
 877         struct ttm_mem_reg tmp_reg;
 878         int ret;
 879
 880         placement.num_placement = placement.num_busy_placement = 1;
 881         placement.placement = placement.busy_placement = &placement_memtype;
 882
 883         tmp_reg = *new_reg;
 884         tmp_reg.mm_node = NULL;
 885         ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
 886         if (ret)
 887                 return ret;
 888
 889         ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx);
 890         if (ret)
 891                 goto out;
 892
 893         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
 894         if (ret)
 895                 goto out;
 896
 897         ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
 898 out:
 899         ttm_bo_mem_put(bo, &tmp_reg);
 900         return ret;
 901 }
 902
 903 static int
 904 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 905                       bool no_wait_gpu, struct ttm_mem_reg *new_reg)
 906 {
 907         struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
 908         struct ttm_place placement_memtype = {
 909                 .fpfn = 0,
 910                 .lpfn = 0,
 911                 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
 912         };
 913         struct ttm_placement placement;
 914         struct ttm_mem_reg tmp_reg;
 915         int ret;
 916
 917         placement.num_placement = placement.num_busy_placement = 1;
 918         placement.placement = placement.busy_placement = &placement_memtype;
 919
 920         tmp_reg = *new_reg;
 921         tmp_reg.mm_node = NULL;
 922         ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
 923         if (ret)
 924                 return ret;
 925
 926         ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
 927         if (ret)
 928                 goto out;
 929
 930         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
 931         if (ret)
 932                 goto out;
 933
 934 out:
 935         ttm_bo_mem_put(bo, &tmp_reg);
 936         return ret;
 937 }
 938
 939 static void
 940 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
 941                      struct ttm_mem_reg *new_reg)
 942 {
 943         struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
 944         struct nouveau_bo *nvbo = nouveau_bo(bo);
 945         struct nouveau_vma *vma;
 946
 947         /* ttm can now (stupidly) pass the driver bos it didn't create... */
 948         if (bo->destroy != nouveau_bo_del_ttm)
 949                 return;
 950
 951         if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
 952             mem->mem.page == nvbo->page) {
 953                 list_for_each_entry(vma, &nvbo->vma_list, head) {
 954                         nouveau_vma_map(vma, mem);
 955                 }
 956         } else {
 957                 list_for_each_entry(vma, &nvbo->vma_list, head) {
 958                         WARN_ON(ttm_bo_wait(bo, false, false));
 959                         nouveau_vma_unmap(vma);
 960                 }
 961         }
 962
 963         if (new_reg) {
 964                 if (new_reg->mm_node)
 965                         nvbo->offset = (new_reg->start << PAGE_SHIFT);
 966                 else
 967                         nvbo->offset = 0;
 968         }
 969
 970 }
 971
 972 static int
 973 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg,
 974                    struct nouveau_drm_tile **new_tile)
 975 {
 976         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 977         struct drm_device *dev = drm->dev;
 978         struct nouveau_bo *nvbo = nouveau_bo(bo);
 979         u64 offset = new_reg->start << PAGE_SHIFT;
 980
 981         *new_tile = NULL;
 982         if (new_reg->mem_type != TTM_PL_VRAM)
 983                 return 0;
 984
 985         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
 986                 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
 987                                                nvbo->mode, nvbo->zeta);
 988         }
 989
 990         return 0;
 991 }
 992
 993 static void
 994 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
 995                       struct nouveau_drm_tile *new_tile,
 996                       struct nouveau_drm_tile **old_tile)
 997 {
 998         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
 999         struct drm_device *dev = drm->dev;
1000         struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1001
1002         nv10_bo_put_tile_region(dev, *old_tile, fence);
1003         *old_tile = new_tile;
1004 }
1005
1006 static int
1007 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1008                 struct ttm_operation_ctx *ctx,
1009                 struct ttm_mem_reg *new_reg)
1010 {
1011         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1012         struct nouveau_bo *nvbo = nouveau_bo(bo);
1013         struct ttm_mem_reg *old_reg = &bo->mem;
1014         struct nouveau_drm_tile *new_tile = NULL;
1015         int ret = 0;
1016
1017         ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1018         if (ret)
1019                 return ret;
1020
1021         if (nvbo->pin_refcnt)
1022                 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1023
1024         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1025                 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1026                 if (ret)
1027                         return ret;
1028         }
1029
1030         /* Fake bo copy. */
1031         if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1032                 BUG_ON(bo->mem.mm_node != NULL);
1033                 bo->mem = *new_reg;
1034                 new_reg->mm_node = NULL;
1035                 goto out;
1036         }
1037
1038         /* Hardware assisted copy. */
1039         if (drm->ttm.move) {
1040                 if (new_reg->mem_type == TTM_PL_SYSTEM)
1041                         ret = nouveau_bo_move_flipd(bo, evict,
1042                                                     ctx->interruptible,
1043                                                     ctx->no_wait_gpu, new_reg);
1044                 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1045                         ret = nouveau_bo_move_flips(bo, evict,
1046                                                     ctx->interruptible,
1047                                                     ctx->no_wait_gpu, new_reg);
1048                 else
1049                         ret = nouveau_bo_move_m2mf(bo, evict,
1050                                                    ctx->interruptible,
1051                                                    ctx->no_wait_gpu, new_reg);
1052                 if (!ret)
1053                         goto out;
1054         }
1055
1056         /* Fallback to software copy. */
1057         ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1058         if (ret == 0)
1059                 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1060
1061 out:
1062         if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1063                 if (ret)
1064                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1065                 else
1066                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1067         }
1068
1069         return ret;
1070 }
1071
1072 static int
1073 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1074 {
1075         struct nouveau_bo *nvbo = nouveau_bo(bo);
1076
1077         return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1078                                           filp->private_data);
1079 }
1080
1081 static int
1082 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1083 {
1084         struct nouveau_drm *drm = nouveau_bdev(bdev);
1085         struct nvkm_device *device = nvxx_device(&drm->client.device);
1086         struct nouveau_mem *mem = nouveau_mem(reg);
1087
1088         reg->bus.addr = NULL;
1089         reg->bus.offset = 0;
1090         reg->bus.size = reg->num_pages << PAGE_SHIFT;
1091         reg->bus.base = 0;
1092         reg->bus.is_iomem = false;
1093
1094         switch (reg->mem_type) {
1095         case TTM_PL_SYSTEM:
1096                 /* System memory */
1097                 return 0;
1098         case TTM_PL_TT:
1099 #if IS_ENABLED(CONFIG_AGP)
1100                 if (drm->agp.bridge) {
1101                         reg->bus.offset = reg->start << PAGE_SHIFT;
1102                         reg->bus.base = drm->agp.base;
1103                         reg->bus.is_iomem = !drm->agp.cma;
1104                 }
1105 #endif
1106                 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
1107                         /* untiled */
1108                         break;
1109                 fallthrough;    /* tiled memory */
1110         case TTM_PL_VRAM:
1111                 reg->bus.offset = reg->start << PAGE_SHIFT;
1112                 reg->bus.base = device->func->resource_addr(device, 1);
1113                 reg->bus.is_iomem = true;
1114                 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1115                         union {
1116                                 struct nv50_mem_map_v0 nv50;
1117                                 struct gf100_mem_map_v0 gf100;
1118                         } args;
1119                         u64 handle, length;
1120                         u32 argc = 0;
1121                         int ret;
1122
1123                         switch (mem->mem.object.oclass) {
1124                         case NVIF_CLASS_MEM_NV50:
1125                                 args.nv50.version = 0;
1126                                 args.nv50.ro = 0;
1127                                 args.nv50.kind = mem->kind;
1128                                 args.nv50.comp = mem->comp;
1129                                 argc = sizeof(args.nv50);
1130                                 break;
1131                         case NVIF_CLASS_MEM_GF100:
1132                                 args.gf100.version = 0;
1133                                 args.gf100.ro = 0;
1134                                 args.gf100.kind = mem->kind;
1135                                 argc = sizeof(args.gf100);
1136                                 break;
1137                         default:
1138                                 WARN_ON(1);
1139                                 break;
1140                         }
1141
1142                         ret = nvif_object_map_handle(&mem->mem.object,
1143                                                      &args, argc,
1144                                                      &handle, &length);
1145                         if (ret != 1) {
1146                                 if (WARN_ON(ret == 0))
1147                                         return -EINVAL;
1148                                 return ret;
1149                         }
1150
1151                         reg->bus.base = 0;
1152                         reg->bus.offset = handle;
1153                 }
1154                 break;
1155         default:
1156                 return -EINVAL;
1157         }
1158         return 0;
1159 }
1160
1161 static void
1162 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1163 {
1164         struct nouveau_drm *drm = nouveau_bdev(bdev);
1165         struct nouveau_mem *mem = nouveau_mem(reg);
1166
1167         if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1168                 switch (reg->mem_type) {
1169                 case TTM_PL_TT:
1170                         if (mem->kind)
1171                                 nvif_object_unmap_handle(&mem->mem.object);
1172                         break;
1173                 case TTM_PL_VRAM:
1174                         nvif_object_unmap_handle(&mem->mem.object);
1175                         break;
1176                 default:
1177                         break;
1178                 }
1179         }
1180 }
1181
1182 static int
1183 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1184 {
1185         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1186         struct nouveau_bo *nvbo = nouveau_bo(bo);
1187         struct nvkm_device *device = nvxx_device(&drm->client.device);
1188         u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1189         int i, ret;
1190
1191         /* as long as the bo isn't in vram, and isn't tiled, we've got
1192          * nothing to do here.
1193          */
1194         if (bo->mem.mem_type != TTM_PL_VRAM) {
1195                 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1196                     !nvbo->kind)
1197                         return 0;
1198
1199                 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1200                         nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1201
1202                         ret = nouveau_bo_validate(nvbo, false, false);
1203                         if (ret)
1204                                 return ret;
1205                 }
1206                 return 0;
1207         }
1208
1209         /* make sure bo is in mappable vram */
1210         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1211             bo->mem.start + bo->mem.num_pages < mappable)
1212                 return 0;
1213
1214         for (i = 0; i < nvbo->placement.num_placement; ++i) {
1215                 nvbo->placements[i].fpfn = 0;
1216                 nvbo->placements[i].lpfn = mappable;
1217         }
1218
1219         for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1220                 nvbo->busy_placements[i].fpfn = 0;
1221                 nvbo->busy_placements[i].lpfn = mappable;
1222         }
1223
1224         nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1225         return nouveau_bo_validate(nvbo, false, false);
1226 }
1227
1228 static int
1229 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1230 {
1231         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1232         struct nouveau_drm *drm;
1233         struct device *dev;
1234         unsigned i;
1235         int r;
1236         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1237
1238         if (ttm->state != tt_unpopulated)
1239                 return 0;
1240
1241         if (slave && ttm->sg) {
1242                 /* make userspace faulting work */
1243                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1244                                                  ttm_dma->dma_address, ttm->num_pages);
1245                 ttm->state = tt_unbound;
1246                 return 0;
1247         }
1248
1249         drm = nouveau_bdev(ttm->bdev);
1250         dev = drm->dev->dev;
1251
1252 #if IS_ENABLED(CONFIG_AGP)
1253         if (drm->agp.bridge) {
1254                 return ttm_agp_tt_populate(ttm, ctx);
1255         }
1256 #endif
1257
1258 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1259         if (swiotlb_nr_tbl()) {
1260                 return ttm_dma_populate((void *)ttm, dev, ctx);
1261         }
1262 #endif
1263
1264         r = ttm_pool_populate(ttm, ctx);
1265         if (r) {
1266                 return r;
1267         }
1268
1269         for (i = 0; i < ttm->num_pages; i++) {
1270                 dma_addr_t addr;
1271
1272                 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE,
1273                                     DMA_BIDIRECTIONAL);
1274
1275                 if (dma_mapping_error(dev, addr)) {
1276                         while (i--) {
1277                                 dma_unmap_page(dev, ttm_dma->dma_address[i],
1278                                                PAGE_SIZE, DMA_BIDIRECTIONAL);
1279                                 ttm_dma->dma_address[i] = 0;
1280                         }
1281                         ttm_pool_unpopulate(ttm);
1282                         return -EFAULT;
1283                 }
1284
1285                 ttm_dma->dma_address[i] = addr;
1286         }
1287         return 0;
1288 }
1289
1290 static void
1291 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1292 {
1293         struct ttm_dma_tt *ttm_dma = (void *)ttm;
1294         struct nouveau_drm *drm;
1295         struct device *dev;
1296         unsigned i;
1297         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1298
1299         if (slave)
1300                 return;
1301
1302         drm = nouveau_bdev(ttm->bdev);
1303         dev = drm->dev->dev;
1304
1305 #if IS_ENABLED(CONFIG_AGP)
1306         if (drm->agp.bridge) {
1307                 ttm_agp_tt_unpopulate(ttm);
1308                 return;
1309         }
1310 #endif
1311
1312 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1313         if (swiotlb_nr_tbl()) {
1314                 ttm_dma_unpopulate((void *)ttm, dev);
1315                 return;
1316         }
1317 #endif
1318
1319         for (i = 0; i < ttm->num_pages; i++) {
1320                 if (ttm_dma->dma_address[i]) {
1321                         dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE,
1322                                        DMA_BIDIRECTIONAL);
1323                 }
1324         }
1325
1326         ttm_pool_unpopulate(ttm);
1327 }
1328
1329 void
1330 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1331 {
1332         struct dma_resv *resv = nvbo->bo.base.resv;
1333
1334         if (exclusive)
1335                 dma_resv_add_excl_fence(resv, &fence->base);
1336         else if (fence)
1337                 dma_resv_add_shared_fence(resv, &fence->base);
1338 }
1339
1340 struct ttm_bo_driver nouveau_bo_driver = {
1341         .ttm_tt_create = &nouveau_ttm_tt_create,
1342         .ttm_tt_populate = &nouveau_ttm_tt_populate,
1343         .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1344         .init_mem_type = nouveau_bo_init_mem_type,
1345         .eviction_valuable = ttm_bo_eviction_valuable,
1346         .evict_flags = nouveau_bo_evict_flags,
1347         .move_notify = nouveau_bo_move_ntfy,
1348         .move = nouveau_bo_move,
1349         .verify_access = nouveau_bo_verify_access,
1350         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1351         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1352         .io_mem_free = &nouveau_ttm_io_mem_free,
1353 };