2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <linux/dma-mapping.h>
32 #include "nouveau_drv.h"
33 #include "nouveau_chan.h"
34 #include "nouveau_fence.h"
36 #include "nouveau_bo.h"
37 #include "nouveau_ttm.h"
38 #include "nouveau_gem.h"
39 #include "nouveau_mem.h"
40 #include "nouveau_vmm.h"
42 #include <nvif/class.h>
43 #include <nvif/if500b.h>
44 #include <nvif/if900b.h>
46 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
47 struct ttm_resource *reg);
48 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
51 * NV10-NV40 tiling helpers
55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63 nouveau_fence_unref(®->fence);
66 nvkm_fb_tile_fini(fb, i, tile);
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71 nvkm_fb_tile_prog(fb, i, tile);
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80 spin_lock(&drm->tile.lock);
83 (!tile->fence || nouveau_fence_done(tile->fence)))
88 spin_unlock(&drm->tile.lock);
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
96 struct nouveau_drm *drm = nouveau_drm(dev);
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 spin_unlock(&drm->tile.lock);
106 static struct nouveau_drm_tile *
107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
118 if (pitch && !found) {
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
127 nv10_bo_put_tile_region(dev, tile, NULL);
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
142 WARN_ON(nvbo->bo.pin_count > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
151 drm_gem_object_release(&bo->base);
153 dma_resv_fini(&bo->base._resv);
159 roundup_64(u64 x, u32 y)
167 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
169 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
170 struct nvif_device *device = &drm->client.device;
172 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
174 if (device->info.chipset >= 0x40) {
176 *size = roundup_64(*size, 64 * nvbo->mode);
178 } else if (device->info.chipset >= 0x30) {
180 *size = roundup_64(*size, 64 * nvbo->mode);
182 } else if (device->info.chipset >= 0x20) {
184 *size = roundup_64(*size, 64 * nvbo->mode);
186 } else if (device->info.chipset >= 0x10) {
188 *size = roundup_64(*size, 32 * nvbo->mode);
192 *size = roundup_64(*size, (1 << nvbo->page));
193 *align = max((1 << nvbo->page), *align);
196 *size = roundup_64(*size, PAGE_SIZE);
200 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
201 u32 tile_mode, u32 tile_flags)
203 struct nouveau_drm *drm = cli->drm;
204 struct nouveau_bo *nvbo;
205 struct nvif_mmu *mmu = &cli->mmu;
206 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
210 NV_WARN(drm, "skipped size %016llx\n", *size);
211 return ERR_PTR(-EINVAL);
214 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
216 return ERR_PTR(-ENOMEM);
217 INIT_LIST_HEAD(&nvbo->head);
218 INIT_LIST_HEAD(&nvbo->entry);
219 INIT_LIST_HEAD(&nvbo->vma_list);
220 nvbo->bo.bdev = &drm->ttm.bdev;
222 /* This is confusing, and doesn't actually mean we want an uncached
223 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
224 * into in nouveau_gem_new().
226 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
227 /* Determine if we can get a cache-coherent map, forcing
228 * uncached mapping if we can't.
230 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
231 nvbo->force_coherent = true;
234 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
235 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
236 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
238 return ERR_PTR(-EINVAL);
241 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
243 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
244 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
245 nvbo->comp = (tile_flags & 0x00030000) >> 16;
246 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
248 return ERR_PTR(-EINVAL);
251 nvbo->zeta = (tile_flags & 0x00000007);
253 nvbo->mode = tile_mode;
254 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
256 /* Determine the desirable target GPU page size for the buffer. */
257 for (i = 0; i < vmm->page_nr; i++) {
258 /* Because we cannot currently allow VMM maps to fail
259 * during buffer migration, we need to determine page
260 * size for the buffer up-front, and pre-allocate its
263 * Skip page sizes that can't support needed domains.
265 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
266 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
268 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
269 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
272 /* Select this page size if it's the first that supports
273 * the potential memory domains, or when it's compatible
274 * with the requested compression settings.
276 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
279 /* Stop once the buffer is larger than the current page size. */
280 if (*size >= 1ULL << vmm->page[i].shift)
285 return ERR_PTR(-EINVAL);
287 /* Disable compression if suitable settings couldn't be found. */
288 if (nvbo->comp && !vmm->page[pi].comp) {
289 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
290 nvbo->kind = mmu->kind[nvbo->kind];
293 nvbo->page = vmm->page[pi].shift;
295 nouveau_bo_fixup_align(nvbo, align, size);
301 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
302 struct sg_table *sg, struct dma_resv *robj)
304 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
307 nouveau_bo_placement_set(nvbo, domain, 0);
308 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
310 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
311 &nvbo->placement, align >> PAGE_SHIFT, false, sg,
312 robj, nouveau_bo_del_ttm);
314 /* ttm will call nouveau_bo_del_ttm if it fails.. */
322 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
323 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
324 struct sg_table *sg, struct dma_resv *robj,
325 struct nouveau_bo **pnvbo)
327 struct nouveau_bo *nvbo;
330 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
333 return PTR_ERR(nvbo);
335 nvbo->bo.base.size = size;
336 dma_resv_init(&nvbo->bo.base._resv);
337 drm_vma_node_reset(&nvbo->bo.base.vma_node);
339 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
348 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
352 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
353 pl[*n].mem_type = TTM_PL_VRAM;
357 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
358 pl[*n].mem_type = TTM_PL_TT;
362 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
363 pl[*n].mem_type = TTM_PL_SYSTEM;
364 pl[(*n)++].flags = 0;
369 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
371 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
372 u64 vram_size = drm->client.device.info.ram_size;
373 unsigned i, fpfn, lpfn;
375 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
376 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
377 nvbo->bo.base.size < vram_size / 4) {
379 * Make sure that the color and depth buffers are handled
380 * by independent memory controller units. Up to a 9x
381 * speed up when alpha-blending and depth-test are enabled
385 fpfn = (vram_size / 2) >> PAGE_SHIFT;
389 lpfn = (vram_size / 2) >> PAGE_SHIFT;
391 for (i = 0; i < nvbo->placement.num_placement; ++i) {
392 nvbo->placements[i].fpfn = fpfn;
393 nvbo->placements[i].lpfn = lpfn;
395 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
396 nvbo->busy_placements[i].fpfn = fpfn;
397 nvbo->busy_placements[i].lpfn = lpfn;
403 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
406 struct ttm_placement *pl = &nvbo->placement;
408 pl->placement = nvbo->placements;
409 set_placement_list(nvbo->placements, &pl->num_placement, domain);
411 pl->busy_placement = nvbo->busy_placements;
412 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
415 set_placement_range(nvbo, domain);
419 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
421 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
422 struct ttm_buffer_object *bo = &nvbo->bo;
423 bool force = false, evict = false;
426 ret = ttm_bo_reserve(bo, false, false, NULL);
430 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
431 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
439 if (nvbo->bo.pin_count) {
442 switch (bo->resource->mem_type) {
444 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
447 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
454 NV_ERROR(drm, "bo %p pinned elsewhere: "
455 "0x%08x vs 0x%08x\n", bo,
456 bo->resource->mem_type, domain);
459 ttm_bo_pin(&nvbo->bo);
464 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
465 ret = nouveau_bo_validate(nvbo, false, false);
470 nouveau_bo_placement_set(nvbo, domain, 0);
471 ret = nouveau_bo_validate(nvbo, false, false);
475 ttm_bo_pin(&nvbo->bo);
477 switch (bo->resource->mem_type) {
479 drm->gem.vram_available -= bo->base.size;
482 drm->gem.gart_available -= bo->base.size;
490 nvbo->contig = false;
491 ttm_bo_unreserve(bo);
496 nouveau_bo_unpin(struct nouveau_bo *nvbo)
498 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
499 struct ttm_buffer_object *bo = &nvbo->bo;
502 ret = ttm_bo_reserve(bo, false, false, NULL);
506 ttm_bo_unpin(&nvbo->bo);
507 if (!nvbo->bo.pin_count) {
508 switch (bo->resource->mem_type) {
510 drm->gem.vram_available += bo->base.size;
513 drm->gem.gart_available += bo->base.size;
520 ttm_bo_unreserve(bo);
525 nouveau_bo_map(struct nouveau_bo *nvbo)
529 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
533 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.resource->num_pages, &nvbo->kmap);
535 ttm_bo_unreserve(&nvbo->bo);
540 nouveau_bo_unmap(struct nouveau_bo *nvbo)
545 ttm_bo_kunmap(&nvbo->kmap);
549 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
551 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
552 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
555 if (!ttm_dma || !ttm_dma->dma_address)
557 if (!ttm_dma->pages) {
558 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
562 /* Don't waste time looping if the object is coherent */
563 if (nvbo->force_coherent)
567 while (i < ttm_dma->num_pages) {
568 struct page *p = ttm_dma->pages[i];
569 size_t num_pages = 1;
571 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
572 if (++p != ttm_dma->pages[j])
577 dma_sync_single_for_device(drm->dev->dev,
578 ttm_dma->dma_address[i],
579 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
585 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
587 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
588 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
591 if (!ttm_dma || !ttm_dma->dma_address)
593 if (!ttm_dma->pages) {
594 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
598 /* Don't waste time looping if the object is coherent */
599 if (nvbo->force_coherent)
603 while (i < ttm_dma->num_pages) {
604 struct page *p = ttm_dma->pages[i];
605 size_t num_pages = 1;
607 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
608 if (++p != ttm_dma->pages[j])
614 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
615 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
620 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
622 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
623 struct nouveau_bo *nvbo = nouveau_bo(bo);
625 mutex_lock(&drm->ttm.io_reserve_mutex);
626 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
627 mutex_unlock(&drm->ttm.io_reserve_mutex);
630 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
632 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
633 struct nouveau_bo *nvbo = nouveau_bo(bo);
635 mutex_lock(&drm->ttm.io_reserve_mutex);
636 list_del_init(&nvbo->io_reserve_lru);
637 mutex_unlock(&drm->ttm.io_reserve_mutex);
641 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
644 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
647 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
651 nouveau_bo_sync_for_device(nvbo);
657 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
660 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
665 iowrite16_native(val, (void __force __iomem *)mem);
671 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
674 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
679 return ioread32_native((void __force __iomem *)mem);
685 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
688 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
693 iowrite32_native(val, (void __force __iomem *)mem);
698 static struct ttm_tt *
699 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
701 #if IS_ENABLED(CONFIG_AGP)
702 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
704 if (drm->agp.bridge) {
705 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
709 return nouveau_sgdma_create_ttm(bo, page_flags);
713 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
714 struct ttm_resource *reg)
716 #if IS_ENABLED(CONFIG_AGP)
717 struct nouveau_drm *drm = nouveau_bdev(bdev);
721 #if IS_ENABLED(CONFIG_AGP)
723 return ttm_agp_bind(ttm, reg);
725 return nouveau_sgdma_bind(bdev, ttm, reg);
729 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
731 #if IS_ENABLED(CONFIG_AGP)
732 struct nouveau_drm *drm = nouveau_bdev(bdev);
734 if (drm->agp.bridge) {
739 nouveau_sgdma_unbind(bdev, ttm);
743 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
745 struct nouveau_bo *nvbo = nouveau_bo(bo);
747 switch (bo->resource->mem_type) {
749 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
750 NOUVEAU_GEM_DOMAIN_CPU);
753 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
757 *pl = nvbo->placement;
761 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
762 struct ttm_resource *reg)
764 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
765 struct nouveau_mem *new_mem = nouveau_mem(reg);
766 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
769 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
770 old_mem->mem.size, &old_mem->vma[0]);
774 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
775 new_mem->mem.size, &old_mem->vma[1]);
779 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
783 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
786 nvif_vmm_put(vmm, &old_mem->vma[1]);
787 nvif_vmm_put(vmm, &old_mem->vma[0]);
793 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
794 struct ttm_operation_ctx *ctx,
795 struct ttm_resource *new_reg)
797 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
798 struct nouveau_channel *chan = drm->ttm.chan;
799 struct nouveau_cli *cli = (void *)chan->user.client;
800 struct nouveau_fence *fence;
803 /* create temporary vmas for the transfer and attach them to the
804 * old nvkm_mem node, these will get cleaned up after ttm has
805 * destroyed the ttm_resource
807 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
808 ret = nouveau_bo_move_prep(drm, bo, new_reg);
813 if (drm_drv_uses_atomic_modeset(drm->dev))
814 mutex_lock(&cli->mutex);
816 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
817 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
819 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
821 ret = nouveau_fence_new(chan, false, &fence);
823 ret = ttm_bo_move_accel_cleanup(bo,
827 nouveau_fence_unref(&fence);
831 mutex_unlock(&cli->mutex);
836 nouveau_bo_move_init(struct nouveau_drm *drm)
838 static const struct _method_table {
842 int (*exec)(struct nouveau_channel *,
843 struct ttm_buffer_object *,
844 struct ttm_resource *, struct ttm_resource *);
845 int (*init)(struct nouveau_channel *, u32 handle);
847 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
848 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
849 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
850 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
851 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
852 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
853 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
854 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
855 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
856 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
857 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
858 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
859 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
860 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
861 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
862 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
863 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
864 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
865 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
866 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
869 const struct _method_table *mthd = _methods;
870 const char *name = "CPU";
874 struct nouveau_channel *chan;
883 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
884 mthd->oclass | (mthd->engine << 16),
885 mthd->oclass, NULL, 0,
888 ret = mthd->init(chan, drm->ttm.copy.handle);
890 nvif_object_dtor(&drm->ttm.copy);
894 drm->ttm.move = mthd->exec;
895 drm->ttm.chan = chan;
899 } while ((++mthd)->exec);
901 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
904 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
905 struct ttm_resource *new_reg)
907 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
908 struct nouveau_bo *nvbo = nouveau_bo(bo);
909 struct nouveau_vma *vma;
911 /* ttm can now (stupidly) pass the driver bos it didn't create... */
912 if (bo->destroy != nouveau_bo_del_ttm)
915 nouveau_bo_del_io_reserve_lru(bo);
917 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
918 mem->mem.page == nvbo->page) {
919 list_for_each_entry(vma, &nvbo->vma_list, head) {
920 nouveau_vma_map(vma, mem);
923 list_for_each_entry(vma, &nvbo->vma_list, head) {
924 WARN_ON(ttm_bo_wait(bo, false, false));
925 nouveau_vma_unmap(vma);
930 nvbo->offset = (new_reg->start << PAGE_SHIFT);
935 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
936 struct nouveau_drm_tile **new_tile)
938 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
939 struct drm_device *dev = drm->dev;
940 struct nouveau_bo *nvbo = nouveau_bo(bo);
941 u64 offset = new_reg->start << PAGE_SHIFT;
944 if (new_reg->mem_type != TTM_PL_VRAM)
947 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
948 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
949 nvbo->mode, nvbo->zeta);
956 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
957 struct nouveau_drm_tile *new_tile,
958 struct nouveau_drm_tile **old_tile)
960 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
961 struct drm_device *dev = drm->dev;
962 struct dma_fence *fence;
965 /* TODO: This is actually a memory management dependency */
966 ret = dma_resv_get_singleton(bo->base.resv, false, &fence);
968 dma_resv_wait_timeout(bo->base.resv, false, false,
969 MAX_SCHEDULE_TIMEOUT);
971 nv10_bo_put_tile_region(dev, *old_tile, fence);
972 *old_tile = new_tile;
976 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
977 struct ttm_operation_ctx *ctx,
978 struct ttm_resource *new_reg,
979 struct ttm_place *hop)
981 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
982 struct nouveau_bo *nvbo = nouveau_bo(bo);
983 struct ttm_resource *old_reg = bo->resource;
984 struct nouveau_drm_tile *new_tile = NULL;
988 if (new_reg->mem_type == TTM_PL_TT) {
989 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
994 nouveau_bo_move_ntfy(bo, new_reg);
995 ret = ttm_bo_wait_ctx(bo, ctx);
999 if (nvbo->bo.pin_count)
1000 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1002 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1003 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1009 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1010 ttm_bo_move_null(bo, new_reg);
1014 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1015 new_reg->mem_type == TTM_PL_TT) {
1016 ttm_bo_move_null(bo, new_reg);
1020 if (old_reg->mem_type == TTM_PL_TT &&
1021 new_reg->mem_type == TTM_PL_SYSTEM) {
1022 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1023 ttm_resource_free(bo, &bo->resource);
1024 ttm_bo_assign_mem(bo, new_reg);
1028 /* Hardware assisted copy. */
1029 if (drm->ttm.move) {
1030 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1031 new_reg->mem_type == TTM_PL_VRAM) ||
1032 (old_reg->mem_type == TTM_PL_VRAM &&
1033 new_reg->mem_type == TTM_PL_SYSTEM)) {
1036 hop->mem_type = TTM_PL_TT;
1040 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1046 /* Fallback to software copy. */
1047 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1051 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1053 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1055 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1059 nouveau_bo_move_ntfy(bo, bo->resource);
1065 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1066 struct ttm_resource *reg)
1068 struct nouveau_mem *mem = nouveau_mem(reg);
1070 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1071 switch (reg->mem_type) {
1074 nvif_object_unmap_handle(&mem->mem.object);
1077 nvif_object_unmap_handle(&mem->mem.object);
1086 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1088 struct nouveau_drm *drm = nouveau_bdev(bdev);
1089 struct nvkm_device *device = nvxx_device(&drm->client.device);
1090 struct nouveau_mem *mem = nouveau_mem(reg);
1091 struct nvif_mmu *mmu = &drm->client.mmu;
1094 mutex_lock(&drm->ttm.io_reserve_mutex);
1096 switch (reg->mem_type) {
1102 #if IS_ENABLED(CONFIG_AGP)
1103 if (drm->agp.bridge) {
1104 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1106 reg->bus.is_iomem = !drm->agp.cma;
1107 reg->bus.caching = ttm_write_combined;
1110 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1116 fallthrough; /* tiled memory */
1118 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1119 device->func->resource_addr(device, 1);
1120 reg->bus.is_iomem = true;
1122 /* Some BARs do not support being ioremapped WC */
1123 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1124 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1125 reg->bus.caching = ttm_uncached;
1127 reg->bus.caching = ttm_write_combined;
1129 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1131 struct nv50_mem_map_v0 nv50;
1132 struct gf100_mem_map_v0 gf100;
1137 switch (mem->mem.object.oclass) {
1138 case NVIF_CLASS_MEM_NV50:
1139 args.nv50.version = 0;
1141 args.nv50.kind = mem->kind;
1142 args.nv50.comp = mem->comp;
1143 argc = sizeof(args.nv50);
1145 case NVIF_CLASS_MEM_GF100:
1146 args.gf100.version = 0;
1148 args.gf100.kind = mem->kind;
1149 argc = sizeof(args.gf100);
1156 ret = nvif_object_map_handle(&mem->mem.object,
1160 if (WARN_ON(ret == 0))
1165 reg->bus.offset = handle;
1174 if (ret == -ENOSPC) {
1175 struct nouveau_bo *nvbo;
1177 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1181 list_del_init(&nvbo->io_reserve_lru);
1182 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1184 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1189 mutex_unlock(&drm->ttm.io_reserve_mutex);
1194 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1196 struct nouveau_drm *drm = nouveau_bdev(bdev);
1198 mutex_lock(&drm->ttm.io_reserve_mutex);
1199 nouveau_ttm_io_mem_free_locked(drm, reg);
1200 mutex_unlock(&drm->ttm.io_reserve_mutex);
1203 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1205 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1206 struct nouveau_bo *nvbo = nouveau_bo(bo);
1207 struct nvkm_device *device = nvxx_device(&drm->client.device);
1208 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1211 /* as long as the bo isn't in vram, and isn't tiled, we've got
1212 * nothing to do here.
1214 if (bo->resource->mem_type != TTM_PL_VRAM) {
1215 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1219 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1222 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1225 /* make sure bo is in mappable vram */
1226 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1227 bo->resource->start + bo->resource->num_pages < mappable)
1230 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1231 nvbo->placements[i].fpfn = 0;
1232 nvbo->placements[i].lpfn = mappable;
1235 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1236 nvbo->busy_placements[i].fpfn = 0;
1237 nvbo->busy_placements[i].lpfn = mappable;
1240 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1243 ret = nouveau_bo_validate(nvbo, false, false);
1244 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1245 return VM_FAULT_NOPAGE;
1246 else if (unlikely(ret))
1247 return VM_FAULT_SIGBUS;
1249 ttm_bo_move_to_lru_tail_unlocked(bo);
1254 nouveau_ttm_tt_populate(struct ttm_device *bdev,
1255 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1257 struct ttm_tt *ttm_dma = (void *)ttm;
1258 struct nouveau_drm *drm;
1259 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1261 if (ttm_tt_is_populated(ttm))
1264 if (slave && ttm->sg) {
1265 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1270 drm = nouveau_bdev(bdev);
1272 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1276 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1279 struct nouveau_drm *drm;
1280 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1285 nouveau_ttm_tt_unbind(bdev, ttm);
1287 drm = nouveau_bdev(bdev);
1289 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1293 nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1296 #if IS_ENABLED(CONFIG_AGP)
1297 struct nouveau_drm *drm = nouveau_bdev(bdev);
1298 if (drm->agp.bridge) {
1299 ttm_agp_destroy(ttm);
1303 nouveau_sgdma_destroy(bdev, ttm);
1307 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1309 struct dma_resv *resv = nvbo->bo.base.resv;
1312 dma_resv_add_excl_fence(resv, &fence->base);
1314 dma_resv_add_shared_fence(resv, &fence->base);
1318 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1320 nouveau_bo_move_ntfy(bo, NULL);
1323 struct ttm_device_funcs nouveau_bo_driver = {
1324 .ttm_tt_create = &nouveau_ttm_tt_create,
1325 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1326 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1327 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1328 .eviction_valuable = ttm_bo_eviction_valuable,
1329 .evict_flags = nouveau_bo_evict_flags,
1330 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1331 .move = nouveau_bo_move,
1332 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1333 .io_mem_free = &nouveau_ttm_io_mem_free,