2 * Copyright 2007 Dave Airlied
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
30 #include <linux/dma-mapping.h>
31 #include <linux/swiotlb.h>
33 #include "nouveau_drv.h"
34 #include "nouveau_chan.h"
35 #include "nouveau_fence.h"
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40 #include "nouveau_mem.h"
41 #include "nouveau_vmm.h"
43 #include <nvif/class.h>
44 #include <nvif/if500b.h>
45 #include <nvif/if900b.h>
47 static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
48 struct ttm_resource *reg);
51 * NV10-NV40 tiling helpers
55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
63 nouveau_fence_unref(®->fence);
66 nvkm_fb_tile_fini(fb, i, tile);
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
71 nvkm_fb_tile_prog(fb, i, tile);
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
80 spin_lock(&drm->tile.lock);
83 (!tile->fence || nouveau_fence_done(tile->fence)))
88 spin_unlock(&drm->tile.lock);
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
96 struct nouveau_drm *drm = nouveau_drm(dev);
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
102 spin_unlock(&drm->tile.lock);
106 static struct nouveau_drm_tile *
107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
118 if (pitch && !found) {
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
127 nv10_bo_put_tile_region(dev, tile, NULL);
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
142 WARN_ON(nvbo->pin_refcnt > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
151 drm_gem_object_release(&bo->base);
157 roundup_64(u64 x, u32 y)
165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
168 struct nvif_device *device = &drm->client.device;
170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
172 if (device->info.chipset >= 0x40) {
174 *size = roundup_64(*size, 64 * nvbo->mode);
176 } else if (device->info.chipset >= 0x30) {
178 *size = roundup_64(*size, 64 * nvbo->mode);
180 } else if (device->info.chipset >= 0x20) {
182 *size = roundup_64(*size, 64 * nvbo->mode);
184 } else if (device->info.chipset >= 0x10) {
186 *size = roundup_64(*size, 32 * nvbo->mode);
190 *size = roundup_64(*size, (1 << nvbo->page));
191 *align = max((1 << nvbo->page), *align);
194 *size = roundup_64(*size, PAGE_SIZE);
198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
199 u32 tile_mode, u32 tile_flags)
201 struct nouveau_drm *drm = cli->drm;
202 struct nouveau_bo *nvbo;
203 struct nvif_mmu *mmu = &cli->mmu;
204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
208 NV_WARN(drm, "skipped size %016llx\n", *size);
209 return ERR_PTR(-EINVAL);
212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
214 return ERR_PTR(-ENOMEM);
215 INIT_LIST_HEAD(&nvbo->head);
216 INIT_LIST_HEAD(&nvbo->entry);
217 INIT_LIST_HEAD(&nvbo->vma_list);
218 nvbo->bo.bdev = &drm->ttm.bdev;
220 /* This is confusing, and doesn't actually mean we want an uncached
221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
222 * into in nouveau_gem_new().
224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
225 /* Determine if we can get a cache-coherent map, forcing
226 * uncached mapping if we can't.
228 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
229 nvbo->force_coherent = true;
232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
236 return ERR_PTR(-EINVAL);
239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
242 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
243 nvbo->comp = (tile_flags & 0x00030000) >> 16;
244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
246 return ERR_PTR(-EINVAL);
249 nvbo->zeta = (tile_flags & 0x00000007);
251 nvbo->mode = tile_mode;
252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
254 /* Determine the desirable target GPU page size for the buffer. */
255 for (i = 0; i < vmm->page_nr; i++) {
256 /* Because we cannot currently allow VMM maps to fail
257 * during buffer migration, we need to determine page
258 * size for the buffer up-front, and pre-allocate its
261 * Skip page sizes that can't support needed domains.
263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
270 /* Select this page size if it's the first that supports
271 * the potential memory domains, or when it's compatible
272 * with the requested compression settings.
274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
277 /* Stop once the buffer is larger than the current page size. */
278 if (*size >= 1ULL << vmm->page[i].shift)
283 return ERR_PTR(-EINVAL);
285 /* Disable compression if suitable settings couldn't be found. */
286 if (nvbo->comp && !vmm->page[pi].comp) {
287 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
288 nvbo->kind = mmu->kind[nvbo->kind];
291 nvbo->page = vmm->page[pi].shift;
293 nouveau_bo_fixup_align(nvbo, align, size);
299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
300 struct sg_table *sg, struct dma_resv *robj)
302 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
306 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
308 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
309 nouveau_bo_placement_set(nvbo, domain, 0);
310 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
312 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
313 &nvbo->placement, align >> PAGE_SHIFT, false,
314 acc_size, sg, robj, nouveau_bo_del_ttm);
316 /* ttm will call nouveau_bo_del_ttm if it fails.. */
324 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
325 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
326 struct sg_table *sg, struct dma_resv *robj,
327 struct nouveau_bo **pnvbo)
329 struct nouveau_bo *nvbo;
332 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
335 return PTR_ERR(nvbo);
337 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
346 set_placement_list(struct nouveau_drm *drm, struct ttm_place *pl, unsigned *n,
347 uint32_t domain, uint32_t flags)
351 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
352 struct nvif_mmu *mmu = &drm->client.mmu;
354 pl[*n].mem_type = TTM_PL_VRAM;
355 pl[*n].flags = flags & ~TTM_PL_FLAG_CACHED;
357 /* Some BARs do not support being ioremapped WC */
358 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
359 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
360 pl[*n].flags &= ~TTM_PL_FLAG_WC;
364 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
365 pl[*n].mem_type = TTM_PL_TT;
366 pl[*n].flags = flags;
369 pl[*n].flags &= ~TTM_PL_FLAG_CACHED;
373 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
374 pl[*n].mem_type = TTM_PL_SYSTEM;
375 pl[(*n)++].flags = flags;
380 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
382 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
383 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
384 unsigned i, fpfn, lpfn;
386 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
387 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
388 nvbo->bo.mem.num_pages < vram_pages / 4) {
390 * Make sure that the color and depth buffers are handled
391 * by independent memory controller units. Up to a 9x
392 * speed up when alpha-blending and depth-test are enabled
396 fpfn = vram_pages / 2;
400 lpfn = vram_pages / 2;
402 for (i = 0; i < nvbo->placement.num_placement; ++i) {
403 nvbo->placements[i].fpfn = fpfn;
404 nvbo->placements[i].lpfn = lpfn;
406 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
407 nvbo->busy_placements[i].fpfn = fpfn;
408 nvbo->busy_placements[i].lpfn = lpfn;
414 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
417 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
418 struct ttm_placement *pl = &nvbo->placement;
419 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
420 TTM_PL_MASK_CACHING) |
421 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
423 pl->placement = nvbo->placements;
424 set_placement_list(drm, nvbo->placements, &pl->num_placement,
427 pl->busy_placement = nvbo->busy_placements;
428 set_placement_list(drm, nvbo->busy_placements, &pl->num_busy_placement,
429 domain | busy, flags);
431 set_placement_range(nvbo, domain);
435 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
437 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
438 struct ttm_buffer_object *bo = &nvbo->bo;
439 bool force = false, evict = false;
442 ret = ttm_bo_reserve(bo, false, false, NULL);
446 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
447 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
455 if (nvbo->pin_refcnt) {
458 switch (bo->mem.mem_type) {
460 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
463 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
469 NV_ERROR(drm, "bo %p pinned elsewhere: "
470 "0x%08x vs 0x%08x\n", bo,
471 bo->mem.mem_type, domain);
479 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
480 ret = nouveau_bo_validate(nvbo, false, false);
486 nouveau_bo_placement_set(nvbo, domain, 0);
488 /* drop pin_refcnt temporarily, so we don't trip the assertion
489 * in nouveau_bo_move() that makes sure we're not trying to
490 * move a pinned buffer
493 ret = nouveau_bo_validate(nvbo, false, false);
498 switch (bo->mem.mem_type) {
500 drm->gem.vram_available -= bo->mem.size;
503 drm->gem.gart_available -= bo->mem.size;
511 nvbo->contig = false;
512 ttm_bo_unreserve(bo);
517 nouveau_bo_unpin(struct nouveau_bo *nvbo)
519 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
520 struct ttm_buffer_object *bo = &nvbo->bo;
523 ret = ttm_bo_reserve(bo, false, false, NULL);
527 ref = --nvbo->pin_refcnt;
528 WARN_ON_ONCE(ref < 0);
532 switch (bo->mem.mem_type) {
534 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
537 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
543 ret = nouveau_bo_validate(nvbo, false, false);
545 switch (bo->mem.mem_type) {
547 drm->gem.vram_available += bo->mem.size;
550 drm->gem.gart_available += bo->mem.size;
558 ttm_bo_unreserve(bo);
563 nouveau_bo_map(struct nouveau_bo *nvbo)
567 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
571 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
573 ttm_bo_unreserve(&nvbo->bo);
578 nouveau_bo_unmap(struct nouveau_bo *nvbo)
583 ttm_bo_kunmap(&nvbo->kmap);
587 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
589 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
590 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
596 /* Don't waste time looping if the object is coherent */
597 if (nvbo->force_coherent)
600 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
601 dma_sync_single_for_device(drm->dev->dev,
602 ttm_dma->dma_address[i],
603 PAGE_SIZE, DMA_TO_DEVICE);
607 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
609 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
610 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
616 /* Don't waste time looping if the object is coherent */
617 if (nvbo->force_coherent)
620 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
621 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
622 PAGE_SIZE, DMA_FROM_DEVICE);
625 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
627 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
628 struct nouveau_bo *nvbo = nouveau_bo(bo);
630 mutex_lock(&drm->ttm.io_reserve_mutex);
631 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
632 mutex_unlock(&drm->ttm.io_reserve_mutex);
635 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
637 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
638 struct nouveau_bo *nvbo = nouveau_bo(bo);
640 mutex_lock(&drm->ttm.io_reserve_mutex);
641 list_del_init(&nvbo->io_reserve_lru);
642 mutex_unlock(&drm->ttm.io_reserve_mutex);
646 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
649 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
652 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
656 nouveau_bo_sync_for_device(nvbo);
662 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
665 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
670 iowrite16_native(val, (void __force __iomem *)mem);
676 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
679 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
684 return ioread32_native((void __force __iomem *)mem);
690 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
693 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
698 iowrite32_native(val, (void __force __iomem *)mem);
703 static struct ttm_tt *
704 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
706 #if IS_ENABLED(CONFIG_AGP)
707 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
709 if (drm->agp.bridge) {
710 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
714 return nouveau_sgdma_create_ttm(bo, page_flags);
718 nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm,
719 struct ttm_resource *reg)
721 #if IS_ENABLED(CONFIG_AGP)
722 struct nouveau_drm *drm = nouveau_bdev(bdev);
726 #if IS_ENABLED(CONFIG_AGP)
728 return ttm_agp_bind(ttm, reg);
730 return nouveau_sgdma_bind(bdev, ttm, reg);
734 nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
736 #if IS_ENABLED(CONFIG_AGP)
737 struct nouveau_drm *drm = nouveau_bdev(bdev);
739 if (drm->agp.bridge) {
744 nouveau_sgdma_unbind(bdev, ttm);
748 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
750 struct nouveau_bo *nvbo = nouveau_bo(bo);
752 switch (bo->mem.mem_type) {
754 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
755 NOUVEAU_GEM_DOMAIN_CPU);
758 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
762 *pl = nvbo->placement;
766 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
767 struct ttm_resource *reg)
769 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
770 struct nouveau_mem *new_mem = nouveau_mem(reg);
771 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
774 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
775 old_mem->mem.size, &old_mem->vma[0]);
779 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
780 new_mem->mem.size, &old_mem->vma[1]);
784 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
788 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
791 nvif_vmm_put(vmm, &old_mem->vma[1]);
792 nvif_vmm_put(vmm, &old_mem->vma[0]);
798 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
799 bool no_wait_gpu, struct ttm_resource *new_reg)
801 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
802 struct nouveau_channel *chan = drm->ttm.chan;
803 struct nouveau_cli *cli = (void *)chan->user.client;
804 struct nouveau_fence *fence;
807 /* create temporary vmas for the transfer and attach them to the
808 * old nvkm_mem node, these will get cleaned up after ttm has
809 * destroyed the ttm_resource
811 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
812 ret = nouveau_bo_move_prep(drm, bo, new_reg);
817 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
818 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
820 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
822 ret = nouveau_fence_new(chan, false, &fence);
824 ret = ttm_bo_move_accel_cleanup(bo,
828 nouveau_fence_unref(&fence);
832 mutex_unlock(&cli->mutex);
837 nouveau_bo_move_init(struct nouveau_drm *drm)
839 static const struct _method_table {
843 int (*exec)(struct nouveau_channel *,
844 struct ttm_buffer_object *,
845 struct ttm_resource *, struct ttm_resource *);
846 int (*init)(struct nouveau_channel *, u32 handle);
848 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
849 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
850 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
851 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
852 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
853 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
854 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
855 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
856 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
857 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
858 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
859 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
860 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
861 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
862 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
863 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
864 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
865 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
866 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
869 const struct _method_table *mthd = _methods;
870 const char *name = "CPU";
874 struct nouveau_channel *chan;
883 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
884 mthd->oclass | (mthd->engine << 16),
885 mthd->oclass, NULL, 0,
888 ret = mthd->init(chan, drm->ttm.copy.handle);
890 nvif_object_dtor(&drm->ttm.copy);
894 drm->ttm.move = mthd->exec;
895 drm->ttm.chan = chan;
899 } while ((++mthd)->exec);
901 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
905 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
906 bool no_wait_gpu, struct ttm_resource *new_reg)
908 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
909 struct ttm_place placement_memtype = {
912 .mem_type = TTM_PL_TT,
913 .flags = TTM_PL_MASK_CACHING
915 struct ttm_placement placement;
916 struct ttm_resource tmp_reg;
919 placement.num_placement = placement.num_busy_placement = 1;
920 placement.placement = placement.busy_placement = &placement_memtype;
923 tmp_reg.mm_node = NULL;
924 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
928 ret = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
932 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, &tmp_reg);
936 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
940 ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
942 ttm_resource_free(bo, &tmp_reg);
947 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
948 bool no_wait_gpu, struct ttm_resource *new_reg)
950 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
951 struct ttm_place placement_memtype = {
954 .mem_type = TTM_PL_TT,
955 .flags = TTM_PL_MASK_CACHING
957 struct ttm_placement placement;
958 struct ttm_resource tmp_reg;
961 placement.num_placement = placement.num_busy_placement = 1;
962 placement.placement = placement.busy_placement = &placement_memtype;
965 tmp_reg.mm_node = NULL;
966 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
970 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
974 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
979 ttm_resource_free(bo, &tmp_reg);
984 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
985 struct ttm_resource *new_reg)
987 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
988 struct nouveau_bo *nvbo = nouveau_bo(bo);
989 struct nouveau_vma *vma;
991 /* ttm can now (stupidly) pass the driver bos it didn't create... */
992 if (bo->destroy != nouveau_bo_del_ttm)
995 nouveau_bo_del_io_reserve_lru(bo);
997 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
998 mem->mem.page == nvbo->page) {
999 list_for_each_entry(vma, &nvbo->vma_list, head) {
1000 nouveau_vma_map(vma, mem);
1003 list_for_each_entry(vma, &nvbo->vma_list, head) {
1004 WARN_ON(ttm_bo_wait(bo, false, false));
1005 nouveau_vma_unmap(vma);
1010 if (new_reg->mm_node)
1011 nvbo->offset = (new_reg->start << PAGE_SHIFT);
1019 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
1020 struct nouveau_drm_tile **new_tile)
1022 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1023 struct drm_device *dev = drm->dev;
1024 struct nouveau_bo *nvbo = nouveau_bo(bo);
1025 u64 offset = new_reg->start << PAGE_SHIFT;
1028 if (new_reg->mem_type != TTM_PL_VRAM)
1031 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1032 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1033 nvbo->mode, nvbo->zeta);
1040 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1041 struct nouveau_drm_tile *new_tile,
1042 struct nouveau_drm_tile **old_tile)
1044 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1045 struct drm_device *dev = drm->dev;
1046 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
1048 nv10_bo_put_tile_region(dev, *old_tile, fence);
1049 *old_tile = new_tile;
1053 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1054 struct ttm_operation_ctx *ctx,
1055 struct ttm_resource *new_reg)
1057 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1058 struct nouveau_bo *nvbo = nouveau_bo(bo);
1059 struct ttm_resource *old_reg = &bo->mem;
1060 struct nouveau_drm_tile *new_tile = NULL;
1063 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1067 if (nvbo->pin_refcnt)
1068 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1070 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1071 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1077 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1078 ttm_bo_move_null(bo, new_reg);
1082 /* Hardware assisted copy. */
1083 if (drm->ttm.move) {
1084 if (new_reg->mem_type == TTM_PL_SYSTEM)
1085 ret = nouveau_bo_move_flipd(bo, evict,
1087 ctx->no_wait_gpu, new_reg);
1088 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1089 ret = nouveau_bo_move_flips(bo, evict,
1091 ctx->no_wait_gpu, new_reg);
1093 ret = nouveau_bo_move_m2mf(bo, evict,
1095 ctx->no_wait_gpu, new_reg);
1100 /* Fallback to software copy. */
1101 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1103 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1106 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1108 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1110 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1117 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1119 struct nouveau_bo *nvbo = nouveau_bo(bo);
1121 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
1122 filp->private_data);
1126 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1127 struct ttm_resource *reg)
1129 struct nouveau_mem *mem = nouveau_mem(reg);
1131 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1132 switch (reg->mem_type) {
1135 nvif_object_unmap_handle(&mem->mem.object);
1138 nvif_object_unmap_handle(&mem->mem.object);
1147 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1149 struct nouveau_drm *drm = nouveau_bdev(bdev);
1150 struct nvkm_device *device = nvxx_device(&drm->client.device);
1151 struct nouveau_mem *mem = nouveau_mem(reg);
1154 mutex_lock(&drm->ttm.io_reserve_mutex);
1156 switch (reg->mem_type) {
1162 #if IS_ENABLED(CONFIG_AGP)
1163 if (drm->agp.bridge) {
1164 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1166 reg->bus.is_iomem = !drm->agp.cma;
1169 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1175 fallthrough; /* tiled memory */
1177 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1178 device->func->resource_addr(device, 1);
1179 reg->bus.is_iomem = true;
1180 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1182 struct nv50_mem_map_v0 nv50;
1183 struct gf100_mem_map_v0 gf100;
1188 switch (mem->mem.object.oclass) {
1189 case NVIF_CLASS_MEM_NV50:
1190 args.nv50.version = 0;
1192 args.nv50.kind = mem->kind;
1193 args.nv50.comp = mem->comp;
1194 argc = sizeof(args.nv50);
1196 case NVIF_CLASS_MEM_GF100:
1197 args.gf100.version = 0;
1199 args.gf100.kind = mem->kind;
1200 argc = sizeof(args.gf100);
1207 ret = nvif_object_map_handle(&mem->mem.object,
1211 if (WARN_ON(ret == 0))
1216 reg->bus.offset = handle;
1225 if (ret == -ENOSPC) {
1226 struct nouveau_bo *nvbo;
1228 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1232 list_del_init(&nvbo->io_reserve_lru);
1233 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1235 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem);
1240 mutex_unlock(&drm->ttm.io_reserve_mutex);
1245 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg)
1247 struct nouveau_drm *drm = nouveau_bdev(bdev);
1249 mutex_lock(&drm->ttm.io_reserve_mutex);
1250 nouveau_ttm_io_mem_free_locked(drm, reg);
1251 mutex_unlock(&drm->ttm.io_reserve_mutex);
1255 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1257 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1258 struct nouveau_bo *nvbo = nouveau_bo(bo);
1259 struct nvkm_device *device = nvxx_device(&drm->client.device);
1260 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1263 /* as long as the bo isn't in vram, and isn't tiled, we've got
1264 * nothing to do here.
1266 if (bo->mem.mem_type != TTM_PL_VRAM) {
1267 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1271 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1272 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
1275 ret = nouveau_bo_validate(nvbo, false, false);
1282 /* make sure bo is in mappable vram */
1283 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1284 bo->mem.start + bo->mem.num_pages < mappable)
1287 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1288 nvbo->placements[i].fpfn = 0;
1289 nvbo->placements[i].lpfn = mappable;
1292 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1293 nvbo->busy_placements[i].fpfn = 0;
1294 nvbo->busy_placements[i].lpfn = mappable;
1297 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1298 return nouveau_bo_validate(nvbo, false, false);
1302 nouveau_ttm_tt_populate(struct ttm_bo_device *bdev,
1303 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1305 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1306 struct nouveau_drm *drm;
1308 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1310 if (ttm_tt_is_populated(ttm))
1313 if (slave && ttm->sg) {
1314 /* make userspace faulting work */
1315 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1316 ttm_dma->dma_address, ttm->num_pages);
1317 ttm_tt_set_populated(ttm);
1321 drm = nouveau_bdev(bdev);
1322 dev = drm->dev->dev;
1324 #if IS_ENABLED(CONFIG_AGP)
1325 if (drm->agp.bridge) {
1326 return ttm_pool_populate(ttm, ctx);
1330 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1331 if (swiotlb_nr_tbl()) {
1332 return ttm_dma_populate((void *)ttm, dev, ctx);
1335 return ttm_populate_and_map_pages(dev, ttm_dma, ctx);
1339 nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev,
1342 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1343 struct nouveau_drm *drm;
1345 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1350 drm = nouveau_bdev(bdev);
1351 dev = drm->dev->dev;
1353 #if IS_ENABLED(CONFIG_AGP)
1354 if (drm->agp.bridge) {
1355 ttm_pool_unpopulate(ttm);
1360 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1361 if (swiotlb_nr_tbl()) {
1362 ttm_dma_unpopulate((void *)ttm, dev);
1367 ttm_unmap_and_unpopulate_pages(dev, ttm_dma);
1371 nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev,
1374 #if IS_ENABLED(CONFIG_AGP)
1375 struct nouveau_drm *drm = nouveau_bdev(bdev);
1376 if (drm->agp.bridge) {
1377 ttm_agp_unbind(ttm);
1378 ttm_tt_destroy_common(bdev, ttm);
1379 ttm_agp_destroy(ttm);
1383 nouveau_sgdma_destroy(bdev, ttm);
1387 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1389 struct dma_resv *resv = nvbo->bo.base.resv;
1392 dma_resv_add_excl_fence(resv, &fence->base);
1394 dma_resv_add_shared_fence(resv, &fence->base);
1397 struct ttm_bo_driver nouveau_bo_driver = {
1398 .ttm_tt_create = &nouveau_ttm_tt_create,
1399 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1400 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1401 .ttm_tt_bind = &nouveau_ttm_tt_bind,
1402 .ttm_tt_unbind = &nouveau_ttm_tt_unbind,
1403 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1404 .eviction_valuable = ttm_bo_eviction_valuable,
1405 .evict_flags = nouveau_bo_evict_flags,
1406 .move_notify = nouveau_bo_move_ntfy,
1407 .move = nouveau_bo_move,
1408 .verify_access = nouveau_bo_verify_access,
1409 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1410 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1411 .io_mem_free = &nouveau_ttm_io_mem_free,