1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
7 * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8 * SPDX-License-Identifier: MIT
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11 * copy of this software and associated documentation files (the "Software"),
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14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
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29 #define GMMU_FMT_MAX_LEVELS 6U
31 #define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */
33 typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
35 * [in] GPU sub-device handle - this API only supports unicast.
36 * Pass 0 to use subDeviceId instead.
41 * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
46 * [in] Page size (VA coverage) of the level to reserve.
47 * This need not be a leaf (page table) page size - it can be
48 * the coverage of an arbitrary level (including root page directory).
50 NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
53 * [in] First GPU virtual address of the range to reserve.
54 * This must be aligned to pageSize.
56 NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
59 * [in] Last GPU virtual address of the range to reserve.
60 * This (+1) must be aligned to pageSize.
62 NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
65 * [in] Number of PDE levels to copy.
67 NvU32 numLevelsToCopy;
70 * [in] Per-level information.
74 * Physical address of this page level instance.
76 NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
79 * Size in bytes allocated for this level instance.
81 NV_DECLARE_ALIGNED(NvU64 size, 8);
84 * Aperture in which this page level instance resides.
89 * Page shift corresponding to the level
92 } levels[GMMU_FMT_MAX_LEVELS];
93 } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;