drivers/gpu/drm/nouveau/include/nvfw/sec2.h

   1 #ifndef __NVFW_SEC2_H__
   2 #define __NVFW_SEC2_H__
   3
   4 struct nv_sec2_args {
   5         u32 freq_hz;
   6         u32 falc_trace_size;
   7         u32 falc_trace_dma_base;
   8         u32 falc_trace_dma_idx;
   9         bool secure_mode;
  10 };
  11
  12 #define NV_SEC2_UNIT_INIT                                                  0x01
  13 #define NV_SEC2_UNIT_UNLOAD                                                0x06
  14 #define NV_SEC2_UNIT_ACR                                                   0x08
  15
  16 struct nv_sec2_init_msg {
  17         struct nvfw_falcon_msg hdr;
  18 #define NV_SEC2_INIT_MSG_INIT                                              0x00
  19         u8 msg_type;
  20
  21         u8 num_queues;
  22         u16 os_debug_entry_point;
  23
  24         struct {
  25                 u32 offset;
  26                 u16 size;
  27                 u8 index;
  28 #define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ                                     0x00
  29 #define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ                                     0x01
  30                 u8 id;
  31         } queue_info[2];
  32
  33         u32 sw_managed_area_offset;
  34         u16 sw_managed_area_size;
  35 };
  36
  37 struct nv_sec2_init_msg_v1 {
  38         struct nvfw_falcon_msg hdr;
  39 #define NV_SEC2_INIT_MSG_INIT                                              0x00
  40         u8 msg_type;
  41
  42         u8 num_queues;
  43         u16 os_debug_entry_point;
  44
  45         struct {
  46                 u32 offset;
  47                 u16 size;
  48                 u8 index;
  49 #define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ                                     0x00
  50 #define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ                                     0x01
  51                 u8 id;
  52         } queue_info[2];
  53
  54         u32 sw_managed_area_offset;
  55         u16 sw_managed_area_size;
  56
  57         u32 unkn[8];
  58 };
  59
  60 struct nv_sec2_acr_cmd {
  61         struct nvfw_falcon_cmd hdr;
  62 #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON                                   0x00
  63         u8 cmd_type;
  64 };
  65
  66 struct nv_sec2_acr_msg {
  67         struct nvfw_falcon_cmd hdr;
  68         u8 msg_type;
  69 };
  70
  71 struct nv_sec2_acr_bootstrap_falcon_cmd {
  72         struct nv_sec2_acr_cmd cmd;
  73 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES                 0x00000000
  74 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO                  0x00000001
  75         u32 flags;
  76         u32 falcon_id;
  77 };
  78
  79 struct nv_sec2_acr_bootstrap_falcon_msg {
  80         struct nv_sec2_acr_msg msg;
  81         u32 error_code;
  82         u32 falcon_id;
  83 };
  84
  85 #define NV_SEC2_UNIT_V2_INIT   0x01
  86 #define NV_SEC2_UNIT_V2_UNLOAD 0x05
  87 #define NV_SEC2_UNIT_V2_ACR    0x07
  88
  89 struct nv_sec2_acr_bootstrap_falcon_cmd_v1 {
  90         struct nv_sec2_acr_cmd cmd;
  91 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES                 0x00000000
  92 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO                  0x00000001
  93         u32 flags;
  94         u32 falcon_id;
  95         u32 unkn08;
  96         u32 unkn0c;
  97 };
  98
  99 struct nv_sec2_acr_bootstrap_falcon_msg_v1 {
 100         struct nv_sec2_acr_msg msg;
 101         u32 error_code;
 102         u32 falcon_id;
 103         u32 unkn08;
 104 };
 105 #endif