1 #ifndef __NVFW_SEC2_H__
2 #define __NVFW_SEC2_H__
7 u32 falc_trace_dma_base;
8 u32 falc_trace_dma_idx;
12 #define NV_SEC2_UNIT_INIT 0x01
13 #define NV_SEC2_UNIT_UNLOAD 0x06
14 #define NV_SEC2_UNIT_ACR 0x08
16 struct nv_sec2_init_msg {
17 struct nvfw_falcon_msg hdr;
18 #define NV_SEC2_INIT_MSG_INIT 0x00
22 u16 os_debug_entry_point;
28 #define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
29 #define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
33 u32 sw_managed_area_offset;
34 u16 sw_managed_area_size;
37 struct nv_sec2_init_msg_v1 {
38 struct nvfw_falcon_msg hdr;
39 #define NV_SEC2_INIT_MSG_INIT 0x00
43 u16 os_debug_entry_point;
49 #define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
50 #define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
54 u32 sw_managed_area_offset;
55 u16 sw_managed_area_size;
60 struct nv_sec2_acr_cmd {
61 struct nvfw_falcon_cmd hdr;
62 #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00
66 struct nv_sec2_acr_msg {
67 struct nvfw_falcon_cmd hdr;
71 struct nv_sec2_acr_bootstrap_falcon_cmd {
72 struct nv_sec2_acr_cmd cmd;
73 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
74 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
79 struct nv_sec2_acr_bootstrap_falcon_msg {
80 struct nv_sec2_acr_msg msg;
85 #define NV_SEC2_UNIT_V2_INIT 0x01
86 #define NV_SEC2_UNIT_V2_UNLOAD 0x05
87 #define NV_SEC2_UNIT_V2_ACR 0x07
89 struct nv_sec2_acr_bootstrap_falcon_cmd_v1 {
90 struct nv_sec2_acr_cmd cmd;
91 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
92 #define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
99 struct nv_sec2_acr_bootstrap_falcon_msg_v1 {
100 struct nv_sec2_acr_msg msg;