2 * Copyright 2018 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_plane_helper.h>
27 #include <nouveau_bo.h>
29 #include <nvif/clc37e.h>
30 #include <nvif/pushc37b.h>
32 #include <nvhw/class/clc57e.h>
35 wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
37 struct nvif_push *push = wndw->wndw.push;
40 if ((ret = PUSH_WAIT(push, 17)))
43 PUSH_NVSQ(push, NVC57E, 0x0308, asyw->image.mode << 4 |
44 asyw->image.interval);
45 PUSH_NVSQ(push, NVC57E, 0x0224, asyw->image.h << 16 | asyw->image.w,
46 0x0228, asyw->image.layout << 4 |
48 0x022c, asyw->image.colorspace << 8 |
50 0x0230, asyw->image.blocks[0] |
51 (asyw->image.pitch[0] >> 6));
52 PUSH_NVSQ(push, NVC57E, 0x0240, asyw->image.handle[0]);
53 PUSH_NVSQ(push, NVC57E, 0x0260, asyw->image.offset[0] >> 8);
54 PUSH_NVSQ(push, NVC57E, 0x0290,(asyw->state.src_y >> 16) << 16 |
55 (asyw->state.src_x >> 16));
56 PUSH_NVSQ(push, NVC57E, 0x0298,(asyw->state.src_h >> 16) << 16 |
57 (asyw->state.src_w >> 16));
58 PUSH_NVSQ(push, NVC57E, 0x02a4, asyw->state.crtc_h << 16 |
64 wndwc57e_csc_clr(struct nv50_wndw *wndw)
66 struct nvif_push *push = wndw->wndw.push;
67 const u32 identity[12] = {
68 0x00010000, 0x00000000, 0x00000000, 0x00000000,
69 0x00000000, 0x00010000, 0x00000000, 0x00000000,
70 0x00000000, 0x00000000, 0x00010000, 0x00000000,
74 if ((ret = PUSH_WAIT(push, 1 + ARRAY_SIZE(identity))))
77 PUSH_NVSQ(push, NVC57E, 0x0400, identity, ARRAY_SIZE(identity));
82 wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
84 struct nvif_push *push = wndw->wndw.push;
87 if ((ret = PUSH_WAIT(push, 13)))
90 PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12);
95 wndwc57e_ilut_clr(struct nv50_wndw *wndw)
97 struct nvif_push *push = wndw->wndw.push;
100 if ((ret = PUSH_WAIT(push, 2)))
103 PUSH_NVSQ(push, NVC57E, 0x0444, 0x00000000);
108 wndwc57e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
110 struct nvif_push *push = wndw->wndw.push;
113 if ((ret = PUSH_WAIT(push, 4)))
116 PUSH_NVSQ(push, NVC57E, 0x0440, asyw->xlut.i.size << 8 |
117 asyw->xlut.i.mode << 2 |
118 asyw->xlut.i.output_mode,
119 0x0444, asyw->xlut.handle,
120 0x0448, asyw->xlut.i.offset >> 8);
125 fixedU0_16_FP16(u16 fixed)
127 int sign = 0, exp = 0, man = 0;
129 while (--exp && !(fixed & 0x8000))
131 man = ((fixed << 1) & 0xffc0) >> 6;
134 return (sign << 15) | (exp << 10) | man;
138 wndwc57e_ilut_load(struct drm_color_lut *in, int size, void __iomem *mem)
140 memset_io(mem, 0x00, 0x20); /* VSS header. */
143 for (; size--; in++, mem += 0x08) {
144 u16 r = fixedU0_16_FP16(drm_color_lut_extract(in-> red, 16));
145 u16 g = fixedU0_16_FP16(drm_color_lut_extract(in->green, 16));
146 u16 b = fixedU0_16_FP16(drm_color_lut_extract(in-> blue, 16));
152 /* INTERPOLATE modes require a "next" entry to interpolate with,
153 * so we replicate the last entry to deal with this for now.
155 writew(readw(mem - 8), mem + 0);
156 writew(readw(mem - 6), mem + 2);
157 writew(readw(mem - 4), mem + 4);
161 wndwc57e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
163 if (size = size ? size : 1024, size != 256 && size != 1024)
167 asyw->xlut.i.mode = 1; /* DIRECT8. */
169 asyw->xlut.i.mode = 2; /* DIRECT10. */
171 asyw->xlut.i.size = 4 /* VSS header. */ + size + 1 /* Entries. */;
172 asyw->xlut.i.output_mode = 0; /* INTERPOLATE_DISABLE. */
173 asyw->xlut.i.load = wndwc57e_ilut_load;
177 /****************************************************************
178 * Log2(block height) ----------------------------+ *
179 * Page Kind ----------------------------------+ | *
180 * Gob Height/Page Kind Generation ------+ | | *
181 * Sector layout -------+ | | | *
182 * Compression ------+ | | | | */
183 const u64 wndwc57e_modifiers[] = { /* | | | | | */
184 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 0),
185 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 1),
186 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 2),
187 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 3),
188 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 4),
189 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 2, 0x06, 5),
190 DRM_FORMAT_MOD_LINEAR,
191 DRM_FORMAT_MOD_INVALID
194 static const struct nv50_wndw_func
196 .acquire = wndwc37e_acquire,
197 .release = wndwc37e_release,
198 .sema_set = wndwc37e_sema_set,
199 .sema_clr = wndwc37e_sema_clr,
200 .ntfy_set = wndwc37e_ntfy_set,
201 .ntfy_clr = wndwc37e_ntfy_clr,
202 .ntfy_reset = corec37d_ntfy_init,
203 .ntfy_wait_begun = base507c_ntfy_wait_begun,
204 .ilut = wndwc57e_ilut,
205 .ilut_identity = true,
207 .xlut_set = wndwc57e_ilut_set,
208 .xlut_clr = wndwc57e_ilut_clr,
210 .csc_set = wndwc57e_csc_set,
211 .csc_clr = wndwc57e_csc_clr,
212 .image_set = wndwc57e_image_set,
213 .image_clr = wndwc37e_image_clr,
214 .blend_set = wndwc37e_blend_set,
215 .update = wndwc37e_update,
219 wndwc57e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
220 s32 oclass, struct nv50_wndw **pwndw)
222 return wndwc37e_new_(&wndwc57e, drm, type, index, oclass,
223 BIT(index >> 1), pwndw);