2 * Copyright 2018 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <nvif/class.h>
27 #include <nvif/cl0002.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_fourcc.h>
32 #include "nouveau_bo.h"
33 #include "nouveau_gem.h"
36 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
38 nvif_object_fini(&ctxdma->object);
39 list_del(&ctxdma->head);
43 static struct nv50_wndw_ctxdma *
44 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb)
46 struct nouveau_drm *drm = nouveau_drm(fb->dev);
47 struct nv50_wndw_ctxdma *ctxdma;
52 struct nv_dma_v0 base;
54 struct nv50_dma_v0 nv50;
55 struct gf100_dma_v0 gf100;
56 struct gf119_dma_v0 gf119;
59 u32 argc = sizeof(args.base);
62 nouveau_framebuffer_get_layout(fb, &unused, &kind);
63 handle = NV50_DISP_HANDLE_WNDW_CTX(kind);
65 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) {
66 if (ctxdma->object.handle == handle)
70 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
71 return ERR_PTR(-ENOMEM);
72 list_add(&ctxdma->head, &wndw->ctxdma.list);
74 args.base.target = NV_DMA_V0_TARGET_VRAM;
75 args.base.access = NV_DMA_V0_ACCESS_RDWR;
77 args.base.limit = drm->client.device.info.ram_user - 1;
79 if (drm->client.device.info.chipset < 0x80) {
80 args.nv50.part = NV50_DMA_V0_PART_256;
81 argc += sizeof(args.nv50);
83 if (drm->client.device.info.chipset < 0xc0) {
84 args.nv50.part = NV50_DMA_V0_PART_256;
85 args.nv50.kind = kind;
86 argc += sizeof(args.nv50);
88 if (drm->client.device.info.chipset < 0xd0) {
89 args.gf100.kind = kind;
90 argc += sizeof(args.gf100);
92 args.gf119.page = GF119_DMA_V0_PAGE_LP;
93 args.gf119.kind = kind;
94 argc += sizeof(args.gf119);
97 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY,
98 &args, argc, &ctxdma->object);
100 nv50_wndw_ctxdma_del(ctxdma);
108 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
110 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
111 if (asyw->set.ntfy) {
112 return wndw->func->ntfy_wait_begun(disp->sync,
114 wndw->wndw.base.device);
120 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
121 struct nv50_wndw_atom *asyw)
123 union nv50_wndw_atom_mask clr = {
124 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask),
126 if (clr.sema ) wndw->func-> sema_clr(wndw);
127 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw);
128 if (clr.xlut ) wndw->func-> xlut_clr(wndw);
129 if (clr.csc ) wndw->func-> csc_clr(wndw);
130 if (clr.image) wndw->func->image_clr(wndw);
132 interlock[wndw->interlock.type] |= wndw->interlock.data;
136 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
137 struct nv50_wndw_atom *asyw)
139 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
140 asyw->image.mode = 0;
141 asyw->image.interval = 1;
144 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
145 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
146 if (asyw->set.image) wndw->func->image_set(wndw, asyw);
148 if (asyw->set.xlut ) {
150 asyw->xlut.i.offset =
151 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer,
152 asyw->ilut, asyw->xlut.i.load);
154 wndw->func->xlut_set(wndw, asyw);
157 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw);
158 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw);
159 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw);
160 if (asyw->set.point) {
161 if (asyw->set.point = false, asyw->set.mask)
162 interlock[wndw->interlock.type] |= wndw->interlock.data;
163 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm;
165 wndw->immd->point(wndw, asyw);
166 wndw->immd->update(wndw, interlock);
168 interlock[wndw->interlock.type] |= wndw->interlock.data;
173 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
175 struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
177 asyw->ntfy.handle = wndw->wndw.sync.handle;
178 asyw->ntfy.offset = wndw->ntfy;
179 asyw->ntfy.awaken = false;
180 asyw->set.ntfy = true;
182 wndw->func->ntfy_reset(disp->sync, wndw->ntfy);
187 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
188 struct nv50_wndw_atom *asyw,
189 struct nv50_head_atom *asyh)
191 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
192 NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
193 wndw->func->release(wndw, asyw, asyh);
194 asyw->ntfy.handle = 0;
195 asyw->sema.handle = 0;
196 asyw->xlut.handle = 0;
197 memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle));
201 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw)
203 switch (asyw->state.fb->format->format) {
204 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break;
205 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break;
210 asyw->image.colorspace = 1;
215 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw)
217 switch (asyw->state.fb->format->format) {
218 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break;
219 case DRM_FORMAT_XRGB8888 :
220 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break;
221 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break;
222 case DRM_FORMAT_XRGB1555 :
223 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break;
224 case DRM_FORMAT_XBGR2101010 :
225 case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break;
226 case DRM_FORMAT_XBGR8888 :
227 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break;
228 case DRM_FORMAT_XRGB2101010 :
229 case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break;
230 case DRM_FORMAT_XBGR16161616F:
231 case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break;
235 asyw->image.colorspace = 0;
240 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
241 struct nv50_wndw_atom *armw,
242 struct nv50_wndw_atom *asyw,
243 struct nv50_head_atom *asyh)
245 struct drm_framebuffer *fb = asyw->state.fb;
246 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
251 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
253 if (fb != armw->state.fb || !armw->visible || modeset) {
254 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind);
256 asyw->image.w = fb->width;
257 asyw->image.h = fb->height;
258 asyw->image.kind = kind;
260 ret = nv50_wndw_atomic_check_acquire_rgb(asyw);
262 ret = nv50_wndw_atomic_check_acquire_yuv(asyw);
267 if (asyw->image.kind) {
268 asyw->image.layout = 0;
269 if (drm->client.device.info.chipset >= 0xc0)
270 asyw->image.blockh = tile_mode >> 4;
272 asyw->image.blockh = tile_mode;
273 asyw->image.blocks[0] = fb->pitches[0] / 64;
274 asyw->image.pitch[0] = 0;
276 asyw->image.layout = 1;
277 asyw->image.blockh = 0;
278 asyw->image.blocks[0] = 0;
279 asyw->image.pitch[0] = fb->pitches[0];
282 if (!asyh->state.async_flip)
283 asyw->image.interval = 1;
285 asyw->image.interval = 0;
286 asyw->image.mode = asyw->image.interval ? 0 : 1;
287 asyw->set.image = wndw->func->image_set != NULL;
290 if (wndw->func->scale_set) {
291 asyw->scale.sx = asyw->state.src_x >> 16;
292 asyw->scale.sy = asyw->state.src_y >> 16;
293 asyw->scale.sw = asyw->state.src_w >> 16;
294 asyw->scale.sh = asyw->state.src_h >> 16;
295 asyw->scale.dw = asyw->state.crtc_w;
296 asyw->scale.dh = asyw->state.crtc_h;
297 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale)))
298 asyw->set.scale = true;
301 if (wndw->func->blend_set) {
302 asyw->blend.depth = 255 - asyw->state.normalized_zpos;
303 asyw->blend.k1 = asyw->state.alpha >> 8;
304 switch (asyw->state.pixel_blend_mode) {
305 case DRM_MODE_BLEND_PREMULTI:
306 asyw->blend.src_color = 2; /* K1 */
307 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
309 case DRM_MODE_BLEND_COVERAGE:
310 asyw->blend.src_color = 5; /* K1_TIMES_SRC */
311 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
313 case DRM_MODE_BLEND_PIXEL_NONE:
315 asyw->blend.src_color = 2; /* K1 */
316 asyw->blend.dst_color = 4; /* NEG_K1 */
319 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
320 asyw->set.blend = true;
324 asyw->point.x = asyw->state.crtc_x;
325 asyw->point.y = asyw->state.crtc_y;
326 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
327 asyw->set.point = true;
330 return wndw->func->acquire(wndw, asyw, asyh);
334 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw,
335 struct nv50_wndw_atom *armw,
336 struct nv50_wndw_atom *asyw,
337 struct nv50_head_atom *asyh)
339 struct drm_property_blob *ilut = asyh->state.degamma_lut;
341 /* I8 format without an input LUT makes no sense, and the
342 * HW error-checks for this.
344 * In order to handle legacy gamma, when there's no input
345 * LUT we need to steal the output LUT and use it instead.
347 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) {
348 /* This should be an error, but there's legacy clients
349 * that do a modeset before providing a gamma table.
351 * We keep the window disabled to avoid angering HW.
353 if (!(ilut = asyh->state.gamma_lut)) {
354 asyw->visible = false;
358 if (wndw->func->ilut)
359 asyh->wndw.olut |= BIT(wndw->id);
361 asyh->wndw.olut &= ~BIT(wndw->id);
364 if (!ilut && wndw->func->ilut_identity &&
365 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F &&
366 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) {
367 static struct drm_property_blob dummy = {};
371 /* Recalculate LUT state. */
372 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut));
373 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) {
374 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) {
375 DRM_DEBUG_KMS("Invalid ilut\n");
378 asyw->xlut.handle = wndw->wndw.vram.handle;
379 asyw->xlut.i.buffer = !asyw->xlut.i.buffer;
380 asyw->set.xlut = true;
382 asyw->clr.xlut = armw->xlut.handle != 0;
385 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */
386 if (wndw->func->olut_core &&
387 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle)))
388 asyw->set.xlut = true;
390 if (wndw->func->csc && asyh->state.ctm) {
391 const struct drm_color_ctm *ctm = asyh->state.ctm->data;
392 wndw->func->csc(wndw, asyw, ctm);
393 asyw->csc.valid = true;
394 asyw->set.csc = true;
396 asyw->csc.valid = false;
397 asyw->clr.csc = armw->csc.valid;
400 /* Can't do an immediate flip while changing the LUT. */
401 asyh->state.async_flip = false;
406 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
408 struct nouveau_drm *drm = nouveau_drm(plane->dev);
409 struct nv50_wndw *wndw = nv50_wndw(plane);
410 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
411 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
412 struct nv50_head_atom *harm = NULL, *asyh = NULL;
413 bool modeset = false;
416 NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
418 /* Fetch the assembly state for the head the window will belong to,
419 * and determine whether the window will be visible.
421 if (asyw->state.crtc) {
422 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
424 return PTR_ERR(asyh);
425 modeset = drm_atomic_crtc_needs_modeset(&asyh->state);
426 asyw->visible = asyh->state.active;
428 asyw->visible = false;
431 /* Fetch assembly state for the head the window used to belong to. */
432 if (armw->state.crtc) {
433 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
435 return PTR_ERR(harm);
438 /* LUT configuration can potentially cause the window to be disabled. */
439 if (asyw->visible && wndw->func->xlut_set &&
441 asyh->state.color_mgmt_changed ||
442 asyw->state.fb->format->format !=
443 armw->state.fb->format->format)) {
444 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh);
449 /* Calculate new window state. */
451 ret = nv50_wndw_atomic_check_acquire(wndw, modeset,
456 asyh->wndw.mask |= BIT(wndw->id);
459 nv50_wndw_atomic_check_release(wndw, asyw, harm);
460 harm->wndw.mask &= ~BIT(wndw->id);
465 /* Aside from the obvious case where the window is actively being
466 * disabled, we might also need to temporarily disable the window
467 * when performing certain modeset operations.
469 if (!asyw->visible || modeset) {
470 asyw->clr.ntfy = armw->ntfy.handle != 0;
471 asyw->clr.sema = armw->sema.handle != 0;
472 asyw->clr.xlut = armw->xlut.handle != 0;
473 if (asyw->clr.xlut && asyw->visible)
474 asyw->set.xlut = asyw->xlut.handle != 0;
475 asyw->clr.csc = armw->csc.valid;
476 if (wndw->func->image_clr)
477 asyw->clr.image = armw->image.handle[0] != 0;
484 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
486 struct nouveau_drm *drm = nouveau_drm(plane->dev);
487 struct nouveau_bo *nvbo;
489 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
493 nvbo = nouveau_gem_object(old_state->fb->obj[0]);
494 nouveau_bo_unpin(nvbo);
498 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
500 struct drm_framebuffer *fb = state->fb;
501 struct nouveau_drm *drm = nouveau_drm(plane->dev);
502 struct nv50_wndw *wndw = nv50_wndw(plane);
503 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
504 struct nouveau_bo *nvbo;
505 struct nv50_head_atom *asyh;
506 struct nv50_wndw_ctxdma *ctxdma;
509 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb);
513 nvbo = nouveau_gem_object(fb->obj[0]);
514 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
518 if (wndw->ctxdma.parent) {
519 ctxdma = nv50_wndw_ctxdma_new(wndw, fb);
520 if (IS_ERR(ctxdma)) {
521 nouveau_bo_unpin(nvbo);
522 return PTR_ERR(ctxdma);
526 asyw->image.handle[0] = ctxdma->object.handle;
529 asyw->state.fence = dma_resv_get_excl_rcu(nvbo->bo.base.resv);
530 asyw->image.offset[0] = nvbo->offset;
532 if (wndw->func->prepare) {
533 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
535 return PTR_ERR(asyh);
537 wndw->func->prepare(wndw, asyh, asyw);
543 static const struct drm_plane_helper_funcs
545 .prepare_fb = nv50_wndw_prepare_fb,
546 .cleanup_fb = nv50_wndw_cleanup_fb,
547 .atomic_check = nv50_wndw_atomic_check,
551 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
552 struct drm_plane_state *state)
554 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
555 __drm_atomic_helper_plane_destroy_state(&asyw->state);
559 static struct drm_plane_state *
560 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
562 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
563 struct nv50_wndw_atom *asyw;
564 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
566 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
567 asyw->sema = armw->sema;
568 asyw->ntfy = armw->ntfy;
570 asyw->xlut = armw->xlut;
571 asyw->csc = armw->csc;
572 asyw->image = armw->image;
573 asyw->point = armw->point;
580 nv50_wndw_zpos_default(struct drm_plane *plane)
582 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 :
583 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255;
587 nv50_wndw_reset(struct drm_plane *plane)
589 struct nv50_wndw_atom *asyw;
591 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
595 plane->funcs->atomic_destroy_state(plane, plane->state);
597 __drm_atomic_helper_plane_reset(plane, &asyw->state);
598 plane->state->zpos = nv50_wndw_zpos_default(plane);
599 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane);
603 nv50_wndw_destroy(struct drm_plane *plane)
605 struct nv50_wndw *wndw = nv50_wndw(plane);
606 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp;
608 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) {
609 nv50_wndw_ctxdma_del(ctxdma);
612 nvif_notify_fini(&wndw->notify);
613 nv50_dmac_destroy(&wndw->wimm);
614 nv50_dmac_destroy(&wndw->wndw);
616 nv50_lut_fini(&wndw->ilut);
618 drm_plane_cleanup(&wndw->plane);
622 /* This function assumes the format has already been validated against the plane
623 * and the modifier was validated against the device-wides modifier list at FB
626 static bool nv50_plane_format_mod_supported(struct drm_plane *plane,
627 u32 format, u64 modifier)
629 struct nouveau_drm *drm = nouveau_drm(plane->dev);
632 if (drm->client.device.info.chipset < 0xc0) {
633 const struct drm_format_info *info = drm_format_info(format);
634 const uint8_t kind = (modifier >> 12) & 0xff;
636 if (!format) return false;
638 for (i = 0; i < info->num_planes; i++)
639 if ((info->cpp[i] != 4) && kind != 0x70) return false;
645 const struct drm_plane_funcs
647 .update_plane = drm_atomic_helper_update_plane,
648 .disable_plane = drm_atomic_helper_disable_plane,
649 .destroy = nv50_wndw_destroy,
650 .reset = nv50_wndw_reset,
651 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
652 .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
653 .format_mod_supported = nv50_plane_format_mod_supported,
657 nv50_wndw_notify(struct nvif_notify *notify)
659 return NVIF_NOTIFY_KEEP;
663 nv50_wndw_fini(struct nv50_wndw *wndw)
665 nvif_notify_put(&wndw->notify);
669 nv50_wndw_init(struct nv50_wndw *wndw)
671 nvif_notify_get(&wndw->notify);
675 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
676 enum drm_plane_type type, const char *name, int index,
677 const u32 *format, u32 heads,
678 enum nv50_disp_interlock_type interlock_type, u32 interlock_data,
679 struct nv50_wndw **pwndw)
681 struct nouveau_drm *drm = nouveau_drm(dev);
682 struct nvif_mmu *mmu = &drm->client.mmu;
683 struct nv50_disp *disp = nv50_disp(dev);
684 struct nv50_wndw *wndw;
688 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL)))
692 wndw->interlock.type = interlock_type;
693 wndw->interlock.data = interlock_data;
695 wndw->ctxdma.parent = &wndw->wndw.base.user;
696 INIT_LIST_HEAD(&wndw->ctxdma.list);
698 for (nformat = 0; format[nformat]; nformat++);
700 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw,
702 nouveau_display(dev)->format_modifiers,
703 type, "%s-%d", name, index);
710 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
712 if (wndw->func->ilut) {
713 ret = nv50_lut_init(disp, mmu, &wndw->ilut);
718 wndw->notify.func = nv50_wndw_notify;
720 if (wndw->func->blend_set) {
721 ret = drm_plane_create_zpos_property(&wndw->plane,
722 nv50_wndw_zpos_default(&wndw->plane), 0, 254);
726 ret = drm_plane_create_alpha_property(&wndw->plane);
730 ret = drm_plane_create_blend_mode_property(&wndw->plane,
731 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
732 BIT(DRM_MODE_BLEND_PREMULTI) |
733 BIT(DRM_MODE_BLEND_COVERAGE));
737 ret = drm_plane_create_zpos_immutable_property(&wndw->plane,
738 nv50_wndw_zpos_default(&wndw->plane));
747 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
748 struct nv50_wndw **pwndw)
753 int (*new)(struct nouveau_drm *, enum drm_plane_type,
754 int, s32, struct nv50_wndw **);
756 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
757 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
760 struct nv50_disp *disp = nv50_disp(drm->dev);
763 cid = nvif_mclass(&disp->disp->object, wndws);
765 NV_ERROR(drm, "No supported window class\n");
769 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw);
773 return nv50_wimm_init(drm, *pwndw);