drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_edid.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 u32 *
 202 evo_wait(struct nv50_dmac *evoc, int nr)
 203 {
 204         struct nv50_dmac *dmac = evoc;
 205         struct nvif_device *device = dmac->base.device;
 206         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 207
 208         mutex_lock(&dmac->lock);
 209         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 210                 dmac->ptr[put] = 0x20000000;
 211
 212                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 213                 if (nvif_msec(device, 2000,
 214                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 215                                 break;
 216                 ) < 0) {
 217                         mutex_unlock(&dmac->lock);
 218                         pr_err("nouveau: evo channel stalled\n");
 219                         return NULL;
 220                 }
 221
 222                 put = 0;
 223         }
 224
 225         return dmac->ptr + put;
 226 }
 227
 228 void
 229 evo_kick(u32 *push, struct nv50_dmac *evoc)
 230 {
 231         struct nv50_dmac *dmac = evoc;
 232
 233         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 234          * writes have been flushed right through to VRAM before writing PUT.
 235          */
 236         if (dmac->push.type & NVIF_MEM_VRAM) {
 237                 struct nvif_device *device = dmac->base.device;
 238                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 239                 nvif_msec(device, 2000,
 240                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 241                                 break;
 242                 );
 243         }
 244
 245         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 246         mutex_unlock(&dmac->lock);
 247 }
 248
 249 /******************************************************************************
 250  * Output path helpers
 251  *****************************************************************************/
 252 static void
 253 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 254 {
 255         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 256         struct {
 257                 struct nv50_disp_mthd_v1 base;
 258         } args = {
 259                 .base.version = 1,
 260                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 261                 .base.hasht  = nv_encoder->dcb->hasht,
 262                 .base.hashm  = nv_encoder->dcb->hashm,
 263         };
 264
 265         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 266         nv_encoder->or = -1;
 267         nv_encoder->link = 0;
 268 }
 269
 270 static int
 271 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 272 {
 273         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 274         struct nv50_disp *disp = nv50_disp(drm->dev);
 275         struct {
 276                 struct nv50_disp_mthd_v1 base;
 277                 struct nv50_disp_acquire_v0 info;
 278         } args = {
 279                 .base.version = 1,
 280                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 281                 .base.hasht  = nv_encoder->dcb->hasht,
 282                 .base.hashm  = nv_encoder->dcb->hashm,
 283         };
 284         int ret;
 285
 286         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 287         if (ret) {
 288                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 289                 return ret;
 290         }
 291
 292         nv_encoder->or = args.info.or;
 293         nv_encoder->link = args.info.link;
 294         return 0;
 295 }
 296
 297 static int
 298 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 299                             struct drm_crtc_state *crtc_state,
 300                             struct drm_connector_state *conn_state,
 301                             struct drm_display_mode *native_mode)
 302 {
 303         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 304         struct drm_display_mode *mode = &crtc_state->mode;
 305         struct drm_connector *connector = conn_state->connector;
 306         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 307         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 308
 309         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 310         asyc->scaler.full = false;
 311         if (!native_mode)
 312                 return 0;
 313
 314         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 315                 switch (connector->connector_type) {
 316                 case DRM_MODE_CONNECTOR_LVDS:
 317                 case DRM_MODE_CONNECTOR_eDP:
 318                         /* Force use of scaler for non-EDID modes. */
 319                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 320                                 break;
 321                         mode = native_mode;
 322                         asyc->scaler.full = true;
 323                         break;
 324                 default:
 325                         break;
 326                 }
 327         } else {
 328                 mode = native_mode;
 329         }
 330
 331         if (!drm_mode_equal(adjusted_mode, mode)) {
 332                 drm_mode_copy(adjusted_mode, mode);
 333                 crtc_state->mode_changed = true;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int
 340 nv50_outp_atomic_check(struct drm_encoder *encoder,
 341                        struct drm_crtc_state *crtc_state,
 342                        struct drm_connector_state *conn_state)
 343 {
 344         struct nouveau_connector *nv_connector =
 345                 nouveau_connector(conn_state->connector);
 346         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 347                                            nv_connector->native_mode);
 348 }
 349
 350 /******************************************************************************
 351  * DAC
 352  *****************************************************************************/
 353 static void
 354 nv50_dac_disable(struct drm_encoder *encoder)
 355 {
 356         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 357         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 358         if (nv_encoder->crtc)
 359                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 360         nv_encoder->crtc = NULL;
 361         nv50_outp_release(nv_encoder);
 362 }
 363
 364 static void
 365 nv50_dac_enable(struct drm_encoder *encoder)
 366 {
 367         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 368         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 369         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 370         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 371
 372         nv50_outp_acquire(nv_encoder);
 373
 374         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 375         asyh->or.depth = 0;
 376
 377         nv_encoder->crtc = encoder->crtc;
 378 }
 379
 380 static enum drm_connector_status
 381 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 382 {
 383         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 384         struct nv50_disp *disp = nv50_disp(encoder->dev);
 385         struct {
 386                 struct nv50_disp_mthd_v1 base;
 387                 struct nv50_disp_dac_load_v0 load;
 388         } args = {
 389                 .base.version = 1,
 390                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 391                 .base.hasht  = nv_encoder->dcb->hasht,
 392                 .base.hashm  = nv_encoder->dcb->hashm,
 393         };
 394         int ret;
 395
 396         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 397         if (args.load.data == 0)
 398                 args.load.data = 340;
 399
 400         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 401         if (ret || !args.load.load)
 402                 return connector_status_disconnected;
 403
 404         return connector_status_connected;
 405 }
 406
 407 static const struct drm_encoder_helper_funcs
 408 nv50_dac_help = {
 409         .atomic_check = nv50_outp_atomic_check,
 410         .enable = nv50_dac_enable,
 411         .disable = nv50_dac_disable,
 412         .detect = nv50_dac_detect
 413 };
 414
 415 static void
 416 nv50_dac_destroy(struct drm_encoder *encoder)
 417 {
 418         drm_encoder_cleanup(encoder);
 419         kfree(encoder);
 420 }
 421
 422 static const struct drm_encoder_funcs
 423 nv50_dac_func = {
 424         .destroy = nv50_dac_destroy,
 425 };
 426
 427 static int
 428 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 429 {
 430         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 431         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 432         struct nvkm_i2c_bus *bus;
 433         struct nouveau_encoder *nv_encoder;
 434         struct drm_encoder *encoder;
 435         int type = DRM_MODE_ENCODER_DAC;
 436
 437         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 438         if (!nv_encoder)
 439                 return -ENOMEM;
 440         nv_encoder->dcb = dcbe;
 441
 442         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 443         if (bus)
 444                 nv_encoder->i2c = &bus->i2c;
 445
 446         encoder = to_drm_encoder(nv_encoder);
 447         encoder->possible_crtcs = dcbe->heads;
 448         encoder->possible_clones = 0;
 449         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 450                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 451         drm_encoder_helper_add(encoder, &nv50_dac_help);
 452
 453         drm_connector_attach_encoder(connector, encoder);
 454         return 0;
 455 }
 456
 457 /******************************************************************************
 458  * Audio
 459  *****************************************************************************/
 460 static void
 461 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 462 {
 463         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 464         struct nv50_disp *disp = nv50_disp(encoder->dev);
 465         struct {
 466                 struct nv50_disp_mthd_v1 base;
 467                 struct nv50_disp_sor_hda_eld_v0 eld;
 468         } args = {
 469                 .base.version = 1,
 470                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 471                 .base.hasht   = nv_encoder->dcb->hasht,
 472                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 473                                 (0x0100 << nv_crtc->index),
 474         };
 475
 476         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 477 }
 478
 479 static void
 480 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 481 {
 482         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 483         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 484         struct nouveau_connector *nv_connector;
 485         struct nv50_disp *disp = nv50_disp(encoder->dev);
 486         struct __packed {
 487                 struct {
 488                         struct nv50_disp_mthd_v1 mthd;
 489                         struct nv50_disp_sor_hda_eld_v0 eld;
 490                 } base;
 491                 u8 data[sizeof(nv_connector->base.eld)];
 492         } args = {
 493                 .base.mthd.version = 1,
 494                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 495                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 496                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 497                                      (0x0100 << nv_crtc->index),
 498         };
 499
 500         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 501         if (!drm_detect_monitor_audio(nv_connector->edid))
 502                 return;
 503
 504         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 505
 506         nvif_mthd(&disp->disp->object, 0, &args,
 507                   sizeof(args.base) + drm_eld_size(args.data));
 508 }
 509
 510 /******************************************************************************
 511  * HDMI
 512  *****************************************************************************/
 513 static void
 514 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 515 {
 516         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 517         struct nv50_disp *disp = nv50_disp(encoder->dev);
 518         struct {
 519                 struct nv50_disp_mthd_v1 base;
 520                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 521         } args = {
 522                 .base.version = 1,
 523                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 524                 .base.hasht  = nv_encoder->dcb->hasht,
 525                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 526                                (0x0100 << nv_crtc->index),
 527         };
 528
 529         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 530 }
 531
 532 static void
 533 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 534 {
 535         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 536         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 537         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 538         struct nv50_disp *disp = nv50_disp(encoder->dev);
 539         struct {
 540                 struct nv50_disp_mthd_v1 base;
 541                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 542                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 543         } args = {
 544                 .base.version = 1,
 545                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 546                 .base.hasht  = nv_encoder->dcb->hasht,
 547                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 548                                (0x0100 << nv_crtc->index),
 549                 .pwr.state = 1,
 550                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 551         };
 552         struct nouveau_connector *nv_connector;
 553         struct drm_hdmi_info *hdmi;
 554         u32 max_ac_packet;
 555         union hdmi_infoframe avi_frame;
 556         union hdmi_infoframe vendor_frame;
 557         bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false;
 558         u8 config;
 559         int ret;
 560         int size;
 561
 562         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 563         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 564                 return;
 565
 566         hdmi = &nv_connector->base.display_info.hdmi;
 567         scdc_supported = hdmi->scdc.supported;
 568
 569         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
 570                                                        scdc_supported);
 571         if (!ret) {
 572                 /* We have an AVI InfoFrame, populate it to the display */
 573                 args.pwr.avi_infoframe_length
 574                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 575         }
 576
 577         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 578                                                           &nv_connector->base, mode);
 579         if (!ret) {
 580                 /* We have a Vendor InfoFrame, populate it to the display */
 581                 args.pwr.vendor_infoframe_length
 582                         = hdmi_infoframe_pack(&vendor_frame,
 583                                               args.infoframes
 584                                               + args.pwr.avi_infoframe_length,
 585                                               17);
 586         }
 587
 588         max_ac_packet  = mode->htotal - mode->hdisplay;
 589         max_ac_packet -= args.pwr.rekey;
 590         max_ac_packet -= 18; /* constant from tegra */
 591         args.pwr.max_ac_packet = max_ac_packet / 32;
 592
 593         if (hdmi->scdc.scrambling.supported) {
 594                 high_tmds_clock_ratio = mode->clock > 340000;
 595                 scrambling = high_tmds_clock_ratio ||
 596                         hdmi->scdc.scrambling.low_rates;
 597         }
 598
 599         args.pwr.scdc =
 600                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 601                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 602
 603         size = sizeof(args.base)
 604                 + sizeof(args.pwr)
 605                 + args.pwr.avi_infoframe_length
 606                 + args.pwr.vendor_infoframe_length;
 607         nvif_mthd(&disp->disp->object, 0, &args, size);
 608
 609         nv50_audio_enable(encoder, mode);
 610
 611         /* If SCDC is supported by the downstream monitor, update
 612          * divider / scrambling settings to what we programmed above.
 613          */
 614         if (!hdmi->scdc.scrambling.supported)
 615                 return;
 616
 617         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 618         if (ret < 0) {
 619                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 620                 return;
 621         }
 622         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 623         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 624         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 625         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 626         if (ret < 0)
 627                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 628                          config, ret);
 629 }
 630
 631 /******************************************************************************
 632  * MST
 633  *****************************************************************************/
 634 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 635 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 636 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 637
 638 struct nv50_mstm {
 639         struct nouveau_encoder *outp;
 640
 641         struct drm_dp_mst_topology_mgr mgr;
 642         struct nv50_msto *msto[4];
 643
 644         bool modified;
 645         bool disabled;
 646         int links;
 647 };
 648
 649 struct nv50_mstc {
 650         struct nv50_mstm *mstm;
 651         struct drm_dp_mst_port *port;
 652         struct drm_connector connector;
 653
 654         struct drm_display_mode *native;
 655         struct edid *edid;
 656
 657         int pbn;
 658 };
 659
 660 struct nv50_msto {
 661         struct drm_encoder encoder;
 662
 663         struct nv50_head *head;
 664         struct nv50_mstc *mstc;
 665         bool disabled;
 666 };
 667
 668 static struct drm_dp_payload *
 669 nv50_msto_payload(struct nv50_msto *msto)
 670 {
 671         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 672         struct nv50_mstc *mstc = msto->mstc;
 673         struct nv50_mstm *mstm = mstc->mstm;
 674         int vcpi = mstc->port->vcpi.vcpi, i;
 675
 676         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 677         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 678                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 679                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 680                           mstm->outp->base.base.name, i, payload->vcpi,
 681                           payload->start_slot, payload->num_slots);
 682         }
 683
 684         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 685                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 686                 if (payload->vcpi == vcpi)
 687                         return payload;
 688         }
 689
 690         return NULL;
 691 }
 692
 693 static void
 694 nv50_msto_cleanup(struct nv50_msto *msto)
 695 {
 696         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 697         struct nv50_mstc *mstc = msto->mstc;
 698         struct nv50_mstm *mstm = mstc->mstm;
 699
 700         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 701         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
 702                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 703         if (msto->disabled) {
 704                 msto->mstc = NULL;
 705                 msto->head = NULL;
 706                 msto->disabled = false;
 707         }
 708 }
 709
 710 static void
 711 nv50_msto_prepare(struct nv50_msto *msto)
 712 {
 713         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 714         struct nv50_mstc *mstc = msto->mstc;
 715         struct nv50_mstm *mstm = mstc->mstm;
 716         struct {
 717                 struct nv50_disp_mthd_v1 base;
 718                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 719         } args = {
 720                 .base.version = 1,
 721                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 722                 .base.hasht  = mstm->outp->dcb->hasht,
 723                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 724                                (0x0100 << msto->head->base.index),
 725         };
 726
 727         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 728         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
 729                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 730                 if (payload) {
 731                         args.vcpi.start_slot = payload->start_slot;
 732                         args.vcpi.num_slots = payload->num_slots;
 733                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 734                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 735                 }
 736         }
 737
 738         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 739                   msto->encoder.name, msto->head->base.base.name,
 740                   args.vcpi.start_slot, args.vcpi.num_slots,
 741                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 742         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 743 }
 744
 745 static int
 746 nv50_msto_atomic_check(struct drm_encoder *encoder,
 747                        struct drm_crtc_state *crtc_state,
 748                        struct drm_connector_state *conn_state)
 749 {
 750         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
 751         struct nv50_mstm *mstm = mstc->mstm;
 752         int bpp = conn_state->connector->display_info.bpc * 3;
 753         int slots;
 754
 755         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
 756
 757         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 758         if (slots < 0)
 759                 return slots;
 760
 761         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 762                                            mstc->native);
 763 }
 764
 765 static void
 766 nv50_msto_enable(struct drm_encoder *encoder)
 767 {
 768         struct nv50_head *head = nv50_head(encoder->crtc);
 769         struct nv50_msto *msto = nv50_msto(encoder);
 770         struct nv50_mstc *mstc = NULL;
 771         struct nv50_mstm *mstm = NULL;
 772         struct drm_connector *connector;
 773         struct drm_connector_list_iter conn_iter;
 774         u8 proto, depth;
 775         int slots;
 776         bool r;
 777
 778         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 779         drm_for_each_connector_iter(connector, &conn_iter) {
 780                 if (connector->state->best_encoder == &msto->encoder) {
 781                         mstc = nv50_mstc(connector);
 782                         mstm = mstc->mstm;
 783                         break;
 784                 }
 785         }
 786         drm_connector_list_iter_end(&conn_iter);
 787
 788         if (WARN_ON(!mstc))
 789                 return;
 790
 791         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 792         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
 793         WARN_ON(!r);
 794
 795         if (!mstm->links++)
 796                 nv50_outp_acquire(mstm->outp);
 797
 798         if (mstm->outp->link & 1)
 799                 proto = 0x8;
 800         else
 801                 proto = 0x9;
 802
 803         switch (mstc->connector.display_info.bpc) {
 804         case  6: depth = 0x2; break;
 805         case  8: depth = 0x5; break;
 806         case 10:
 807         default: depth = 0x6; break;
 808         }
 809
 810         mstm->outp->update(mstm->outp, head->base.index,
 811                            nv50_head_atom(head->base.base.state), proto, depth);
 812
 813         msto->head = head;
 814         msto->mstc = mstc;
 815         mstm->modified = true;
 816 }
 817
 818 static void
 819 nv50_msto_disable(struct drm_encoder *encoder)
 820 {
 821         struct nv50_msto *msto = nv50_msto(encoder);
 822         struct nv50_mstc *mstc = msto->mstc;
 823         struct nv50_mstm *mstm = mstc->mstm;
 824
 825         if (mstc->port)
 826                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 827
 828         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 829         mstm->modified = true;
 830         if (!--mstm->links)
 831                 mstm->disabled = true;
 832         msto->disabled = true;
 833 }
 834
 835 static const struct drm_encoder_helper_funcs
 836 nv50_msto_help = {
 837         .disable = nv50_msto_disable,
 838         .enable = nv50_msto_enable,
 839         .atomic_check = nv50_msto_atomic_check,
 840 };
 841
 842 static void
 843 nv50_msto_destroy(struct drm_encoder *encoder)
 844 {
 845         struct nv50_msto *msto = nv50_msto(encoder);
 846         drm_encoder_cleanup(&msto->encoder);
 847         kfree(msto);
 848 }
 849
 850 static const struct drm_encoder_funcs
 851 nv50_msto = {
 852         .destroy = nv50_msto_destroy,
 853 };
 854
 855 static int
 856 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 857               struct nv50_msto **pmsto)
 858 {
 859         struct nv50_msto *msto;
 860         int ret;
 861
 862         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 863                 return -ENOMEM;
 864
 865         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 866                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 867         if (ret) {
 868                 kfree(*pmsto);
 869                 *pmsto = NULL;
 870                 return ret;
 871         }
 872
 873         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 874         msto->encoder.possible_crtcs = heads;
 875         return 0;
 876 }
 877
 878 static struct drm_encoder *
 879 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 880                               struct drm_connector_state *connector_state)
 881 {
 882         struct nv50_head *head = nv50_head(connector_state->crtc);
 883         struct nv50_mstc *mstc = nv50_mstc(connector);
 884
 885         return &mstc->mstm->msto[head->base.index]->encoder;
 886 }
 887
 888 static struct drm_encoder *
 889 nv50_mstc_best_encoder(struct drm_connector *connector)
 890 {
 891         struct nv50_mstc *mstc = nv50_mstc(connector);
 892
 893         return &mstc->mstm->msto[0]->encoder;
 894 }
 895
 896 static enum drm_mode_status
 897 nv50_mstc_mode_valid(struct drm_connector *connector,
 898                      struct drm_display_mode *mode)
 899 {
 900         return MODE_OK;
 901 }
 902
 903 static int
 904 nv50_mstc_get_modes(struct drm_connector *connector)
 905 {
 906         struct nv50_mstc *mstc = nv50_mstc(connector);
 907         int ret = 0;
 908
 909         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 910         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 911         if (mstc->edid)
 912                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 913
 914         if (!mstc->connector.display_info.bpc)
 915                 mstc->connector.display_info.bpc = 8;
 916
 917         if (mstc->native)
 918                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 919         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 920         return ret;
 921 }
 922
 923 static const struct drm_connector_helper_funcs
 924 nv50_mstc_help = {
 925         .get_modes = nv50_mstc_get_modes,
 926         .mode_valid = nv50_mstc_mode_valid,
 927         .best_encoder = nv50_mstc_best_encoder,
 928         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
 929 };
 930
 931 static enum drm_connector_status
 932 nv50_mstc_detect(struct drm_connector *connector, bool force)
 933 {
 934         struct nv50_mstc *mstc = nv50_mstc(connector);
 935         if (!mstc->port)
 936                 return connector_status_disconnected;
 937         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
 938 }
 939
 940 static void
 941 nv50_mstc_destroy(struct drm_connector *connector)
 942 {
 943         struct nv50_mstc *mstc = nv50_mstc(connector);
 944         drm_connector_cleanup(&mstc->connector);
 945         kfree(mstc);
 946 }
 947
 948 static const struct drm_connector_funcs
 949 nv50_mstc = {
 950         .reset = nouveau_conn_reset,
 951         .detect = nv50_mstc_detect,
 952         .fill_modes = drm_helper_probe_single_connector_modes,
 953         .destroy = nv50_mstc_destroy,
 954         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
 955         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
 956         .atomic_set_property = nouveau_conn_atomic_set_property,
 957         .atomic_get_property = nouveau_conn_atomic_get_property,
 958 };
 959
 960 static int
 961 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
 962               const char *path, struct nv50_mstc **pmstc)
 963 {
 964         struct drm_device *dev = mstm->outp->base.base.dev;
 965         struct nv50_mstc *mstc;
 966         int ret, i;
 967
 968         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
 969                 return -ENOMEM;
 970         mstc->mstm = mstm;
 971         mstc->port = port;
 972
 973         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
 974                                  DRM_MODE_CONNECTOR_DisplayPort);
 975         if (ret) {
 976                 kfree(*pmstc);
 977                 *pmstc = NULL;
 978                 return ret;
 979         }
 980
 981         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
 982
 983         mstc->connector.funcs->reset(&mstc->connector);
 984         nouveau_conn_attach_properties(&mstc->connector);
 985
 986         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
 987                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
 988
 989         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
 990         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
 991         drm_connector_set_path_property(&mstc->connector, path);
 992         return 0;
 993 }
 994
 995 static void
 996 nv50_mstm_cleanup(struct nv50_mstm *mstm)
 997 {
 998         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
 999         struct drm_encoder *encoder;
1000         int ret;
1001
1002         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1003         ret = drm_dp_check_act_status(&mstm->mgr);
1004
1005         ret = drm_dp_update_payload_part2(&mstm->mgr);
1006
1007         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1008                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1009                         struct nv50_msto *msto = nv50_msto(encoder);
1010                         struct nv50_mstc *mstc = msto->mstc;
1011                         if (mstc && mstc->mstm == mstm)
1012                                 nv50_msto_cleanup(msto);
1013                 }
1014         }
1015
1016         mstm->modified = false;
1017 }
1018
1019 static void
1020 nv50_mstm_prepare(struct nv50_mstm *mstm)
1021 {
1022         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1023         struct drm_encoder *encoder;
1024         int ret;
1025
1026         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1027         ret = drm_dp_update_payload_part1(&mstm->mgr);
1028
1029         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1030                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1031                         struct nv50_msto *msto = nv50_msto(encoder);
1032                         struct nv50_mstc *mstc = msto->mstc;
1033                         if (mstc && mstc->mstm == mstm)
1034                                 nv50_msto_prepare(msto);
1035                 }
1036         }
1037
1038         if (mstm->disabled) {
1039                 if (!mstm->links)
1040                         nv50_outp_release(mstm->outp);
1041                 mstm->disabled = false;
1042         }
1043 }
1044
1045 static void
1046 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1047 {
1048         struct nv50_mstm *mstm = nv50_mstm(mgr);
1049         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1050 }
1051
1052 static void
1053 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1054                             struct drm_connector *connector)
1055 {
1056         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1057         struct nv50_mstc *mstc = nv50_mstc(connector);
1058
1059         drm_connector_unregister(&mstc->connector);
1060
1061         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1062
1063         drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1064         mstc->port = NULL;
1065         drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1066
1067         drm_connector_put(&mstc->connector);
1068 }
1069
1070 static void
1071 nv50_mstm_register_connector(struct drm_connector *connector)
1072 {
1073         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1074
1075         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1076
1077         drm_connector_register(connector);
1078 }
1079
1080 static struct drm_connector *
1081 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1082                         struct drm_dp_mst_port *port, const char *path)
1083 {
1084         struct nv50_mstm *mstm = nv50_mstm(mgr);
1085         struct nv50_mstc *mstc;
1086         int ret;
1087
1088         ret = nv50_mstc_new(mstm, port, path, &mstc);
1089         if (ret) {
1090                 if (mstc)
1091                         mstc->connector.funcs->destroy(&mstc->connector);
1092                 return NULL;
1093         }
1094
1095         return &mstc->connector;
1096 }
1097
1098 static const struct drm_dp_mst_topology_cbs
1099 nv50_mstm = {
1100         .add_connector = nv50_mstm_add_connector,
1101         .register_connector = nv50_mstm_register_connector,
1102         .destroy_connector = nv50_mstm_destroy_connector,
1103         .hotplug = nv50_mstm_hotplug,
1104 };
1105
1106 void
1107 nv50_mstm_service(struct nv50_mstm *mstm)
1108 {
1109         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1110         bool handled = true;
1111         int ret;
1112         u8 esi[8] = {};
1113
1114         if (!aux)
1115                 return;
1116
1117         while (handled) {
1118                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1119                 if (ret != 8) {
1120                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1121                         return;
1122                 }
1123
1124                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1125                 if (!handled)
1126                         break;
1127
1128                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1129         }
1130 }
1131
1132 void
1133 nv50_mstm_remove(struct nv50_mstm *mstm)
1134 {
1135         if (mstm)
1136                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1137 }
1138
1139 static int
1140 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1141 {
1142         struct nouveau_encoder *outp = mstm->outp;
1143         struct {
1144                 struct nv50_disp_mthd_v1 base;
1145                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1146         } args = {
1147                 .base.version = 1,
1148                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1149                 .base.hasht = outp->dcb->hasht,
1150                 .base.hashm = outp->dcb->hashm,
1151                 .mst.state = state,
1152         };
1153         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1154         struct nvif_object *disp = &drm->display->disp.object;
1155         int ret;
1156
1157         if (dpcd >= 0x12) {
1158                 /* Even if we're enabling MST, start with disabling the
1159                  * branching unit to clear any sink-side MST topology state
1160                  * that wasn't set by us
1161                  */
1162                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1163                 if (ret < 0)
1164                         return ret;
1165
1166                 if (state) {
1167                         /* Now, start initializing */
1168                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1169                                                  DP_MST_EN);
1170                         if (ret < 0)
1171                                 return ret;
1172                 }
1173         }
1174
1175         return nvif_mthd(disp, 0, &args, sizeof(args));
1176 }
1177
1178 int
1179 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1180 {
1181         struct drm_dp_aux *aux;
1182         int ret;
1183         bool old_state, new_state;
1184         u8 mstm_ctrl;
1185
1186         if (!mstm)
1187                 return 0;
1188
1189         mutex_lock(&mstm->mgr.lock);
1190
1191         old_state = mstm->mgr.mst_state;
1192         new_state = old_state;
1193         aux = mstm->mgr.aux;
1194
1195         if (old_state) {
1196                 /* Just check that the MST hub is still as we expect it */
1197                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1198                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1199                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1200                         new_state = false;
1201                 }
1202         } else if (dpcd[0] >= 0x12) {
1203                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1204                 if (ret < 0)
1205                         goto probe_error;
1206
1207                 if (!(dpcd[1] & DP_MST_CAP))
1208                         dpcd[0] = 0x11;
1209                 else
1210                         new_state = allow;
1211         }
1212
1213         if (new_state == old_state) {
1214                 mutex_unlock(&mstm->mgr.lock);
1215                 return new_state;
1216         }
1217
1218         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1219         if (ret)
1220                 goto probe_error;
1221
1222         mutex_unlock(&mstm->mgr.lock);
1223
1224         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1225         if (ret)
1226                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1227
1228         return new_state;
1229
1230 probe_error:
1231         mutex_unlock(&mstm->mgr.lock);
1232         return ret;
1233 }
1234
1235 static void
1236 nv50_mstm_fini(struct nv50_mstm *mstm)
1237 {
1238         if (mstm && mstm->mgr.mst_state)
1239                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1240 }
1241
1242 static void
1243 nv50_mstm_init(struct nv50_mstm *mstm)
1244 {
1245         if (mstm && mstm->mgr.mst_state)
1246                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1247 }
1248
1249 static void
1250 nv50_mstm_del(struct nv50_mstm **pmstm)
1251 {
1252         struct nv50_mstm *mstm = *pmstm;
1253         if (mstm) {
1254                 kfree(*pmstm);
1255                 *pmstm = NULL;
1256         }
1257 }
1258
1259 static int
1260 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1261               int conn_base_id, struct nv50_mstm **pmstm)
1262 {
1263         const int max_payloads = hweight8(outp->dcb->heads);
1264         struct drm_device *dev = outp->base.base.dev;
1265         struct nv50_mstm *mstm;
1266         int ret, i;
1267         u8 dpcd;
1268
1269         /* This is a workaround for some monitors not functioning
1270          * correctly in MST mode on initial module load.  I think
1271          * some bad interaction with the VBIOS may be responsible.
1272          *
1273          * A good ol' off and on again seems to work here ;)
1274          */
1275         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1276         if (ret >= 0 && dpcd >= 0x12)
1277                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1278
1279         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1280                 return -ENOMEM;
1281         mstm->outp = outp;
1282         mstm->mgr.cbs = &nv50_mstm;
1283
1284         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1285                                            max_payloads, conn_base_id);
1286         if (ret)
1287                 return ret;
1288
1289         for (i = 0; i < max_payloads; i++) {
1290                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1291                                     i, &mstm->msto[i]);
1292                 if (ret)
1293                         return ret;
1294         }
1295
1296         return 0;
1297 }
1298
1299 /******************************************************************************
1300  * SOR
1301  *****************************************************************************/
1302 static void
1303 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1304                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1305 {
1306         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1307         struct nv50_core *core = disp->core;
1308
1309         if (!asyh) {
1310                 nv_encoder->ctrl &= ~BIT(head);
1311                 if (!(nv_encoder->ctrl & 0x0000000f))
1312                         nv_encoder->ctrl = 0;
1313         } else {
1314                 nv_encoder->ctrl |= proto << 8;
1315                 nv_encoder->ctrl |= BIT(head);
1316                 asyh->or.depth = depth;
1317         }
1318
1319         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1320 }
1321
1322 static void
1323 nv50_sor_disable(struct drm_encoder *encoder)
1324 {
1325         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1326         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1327
1328         nv_encoder->crtc = NULL;
1329
1330         if (nv_crtc) {
1331                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1332                 u8 pwr;
1333
1334                 if (aux) {
1335                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1336                         if (ret == 0) {
1337                                 pwr &= ~DP_SET_POWER_MASK;
1338                                 pwr |=  DP_SET_POWER_D3;
1339                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1340                         }
1341                 }
1342
1343                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1344                 nv50_audio_disable(encoder, nv_crtc);
1345                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1346                 nv50_outp_release(nv_encoder);
1347         }
1348 }
1349
1350 static void
1351 nv50_sor_enable(struct drm_encoder *encoder)
1352 {
1353         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1354         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1355         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1356         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1357         struct {
1358                 struct nv50_disp_mthd_v1 base;
1359                 struct nv50_disp_sor_lvds_script_v0 lvds;
1360         } lvds = {
1361                 .base.version = 1,
1362                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1363                 .base.hasht   = nv_encoder->dcb->hasht,
1364                 .base.hashm   = nv_encoder->dcb->hashm,
1365         };
1366         struct nv50_disp *disp = nv50_disp(encoder->dev);
1367         struct drm_device *dev = encoder->dev;
1368         struct nouveau_drm *drm = nouveau_drm(dev);
1369         struct nouveau_connector *nv_connector;
1370         struct nvbios *bios = &drm->vbios;
1371         u8 proto = 0xf;
1372         u8 depth = 0x0;
1373
1374         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1375         nv_encoder->crtc = encoder->crtc;
1376         nv50_outp_acquire(nv_encoder);
1377
1378         switch (nv_encoder->dcb->type) {
1379         case DCB_OUTPUT_TMDS:
1380                 if (nv_encoder->link & 1) {
1381                         proto = 0x1;
1382                         /* Only enable dual-link if:
1383                          *  - Need to (i.e. rate > 165MHz)
1384                          *  - DCB says we can
1385                          *  - Not an HDMI monitor, since there's no dual-link
1386                          *    on HDMI.
1387                          */
1388                         if (mode->clock >= 165000 &&
1389                             nv_encoder->dcb->duallink_possible &&
1390                             !drm_detect_hdmi_monitor(nv_connector->edid))
1391                                 proto |= 0x4;
1392                 } else {
1393                         proto = 0x2;
1394                 }
1395
1396                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1397                 break;
1398         case DCB_OUTPUT_LVDS:
1399                 proto = 0x0;
1400
1401                 if (bios->fp_no_ddc) {
1402                         if (bios->fp.dual_link)
1403                                 lvds.lvds.script |= 0x0100;
1404                         if (bios->fp.if_is_24bit)
1405                                 lvds.lvds.script |= 0x0200;
1406                 } else {
1407                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1408                                 if (((u8 *)nv_connector->edid)[121] == 2)
1409                                         lvds.lvds.script |= 0x0100;
1410                         } else
1411                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1412                                 lvds.lvds.script |= 0x0100;
1413                         }
1414
1415                         if (lvds.lvds.script & 0x0100) {
1416                                 if (bios->fp.strapless_is_24bit & 2)
1417                                         lvds.lvds.script |= 0x0200;
1418                         } else {
1419                                 if (bios->fp.strapless_is_24bit & 1)
1420                                         lvds.lvds.script |= 0x0200;
1421                         }
1422
1423                         if (nv_connector->base.display_info.bpc == 8)
1424                                 lvds.lvds.script |= 0x0200;
1425                 }
1426
1427                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1428                 break;
1429         case DCB_OUTPUT_DP:
1430                 if (nv_connector->base.display_info.bpc == 6)
1431                         depth = 0x2;
1432                 else
1433                 if (nv_connector->base.display_info.bpc == 8)
1434                         depth = 0x5;
1435                 else
1436                         depth = 0x6;
1437
1438                 if (nv_encoder->link & 1)
1439                         proto = 0x8;
1440                 else
1441                         proto = 0x9;
1442
1443                 nv50_audio_enable(encoder, mode);
1444                 break;
1445         default:
1446                 BUG();
1447                 break;
1448         }
1449
1450         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1451 }
1452
1453 static const struct drm_encoder_helper_funcs
1454 nv50_sor_help = {
1455         .atomic_check = nv50_outp_atomic_check,
1456         .enable = nv50_sor_enable,
1457         .disable = nv50_sor_disable,
1458 };
1459
1460 static void
1461 nv50_sor_destroy(struct drm_encoder *encoder)
1462 {
1463         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1464         nv50_mstm_del(&nv_encoder->dp.mstm);
1465         drm_encoder_cleanup(encoder);
1466         kfree(encoder);
1467 }
1468
1469 static const struct drm_encoder_funcs
1470 nv50_sor_func = {
1471         .destroy = nv50_sor_destroy,
1472 };
1473
1474 static int
1475 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1476 {
1477         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1478         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1479         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1480         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1481         struct nouveau_encoder *nv_encoder;
1482         struct drm_encoder *encoder;
1483         u8 ver, hdr, cnt, len;
1484         u32 data;
1485         int type, ret;
1486
1487         switch (dcbe->type) {
1488         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1489         case DCB_OUTPUT_TMDS:
1490         case DCB_OUTPUT_DP:
1491         default:
1492                 type = DRM_MODE_ENCODER_TMDS;
1493                 break;
1494         }
1495
1496         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1497         if (!nv_encoder)
1498                 return -ENOMEM;
1499         nv_encoder->dcb = dcbe;
1500         nv_encoder->update = nv50_sor_update;
1501
1502         encoder = to_drm_encoder(nv_encoder);
1503         encoder->possible_crtcs = dcbe->heads;
1504         encoder->possible_clones = 0;
1505         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1506                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1507         drm_encoder_helper_add(encoder, &nv50_sor_help);
1508
1509         drm_connector_attach_encoder(connector, encoder);
1510
1511         if (dcbe->type == DCB_OUTPUT_DP) {
1512                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1513                 struct nvkm_i2c_aux *aux =
1514                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1515                 if (aux) {
1516                         if (disp->disp->object.oclass < GF110_DISP) {
1517                                 /* HW has no support for address-only
1518                                  * transactions, so we're required to
1519                                  * use custom I2C-over-AUX code.
1520                                  */
1521                                 nv_encoder->i2c = &aux->i2c;
1522                         } else {
1523                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1524                         }
1525                         nv_encoder->aux = aux;
1526                 }
1527
1528                 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1529                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1530                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1531                                             nv_connector->base.base.id,
1532                                             &nv_encoder->dp.mstm);
1533                         if (ret)
1534                                 return ret;
1535                 }
1536         } else {
1537                 struct nvkm_i2c_bus *bus =
1538                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1539                 if (bus)
1540                         nv_encoder->i2c = &bus->i2c;
1541         }
1542
1543         return 0;
1544 }
1545
1546 /******************************************************************************
1547  * PIOR
1548  *****************************************************************************/
1549 static int
1550 nv50_pior_atomic_check(struct drm_encoder *encoder,
1551                        struct drm_crtc_state *crtc_state,
1552                        struct drm_connector_state *conn_state)
1553 {
1554         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1555         if (ret)
1556                 return ret;
1557         crtc_state->adjusted_mode.clock *= 2;
1558         return 0;
1559 }
1560
1561 static void
1562 nv50_pior_disable(struct drm_encoder *encoder)
1563 {
1564         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1565         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1566         if (nv_encoder->crtc)
1567                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1568         nv_encoder->crtc = NULL;
1569         nv50_outp_release(nv_encoder);
1570 }
1571
1572 static void
1573 nv50_pior_enable(struct drm_encoder *encoder)
1574 {
1575         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1576         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1577         struct nouveau_connector *nv_connector;
1578         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1579         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1580         u8 owner = 1 << nv_crtc->index;
1581         u8 proto;
1582
1583         nv50_outp_acquire(nv_encoder);
1584
1585         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1586         switch (nv_connector->base.display_info.bpc) {
1587         case 10: asyh->or.depth = 0x6; break;
1588         case  8: asyh->or.depth = 0x5; break;
1589         case  6: asyh->or.depth = 0x2; break;
1590         default: asyh->or.depth = 0x0; break;
1591         }
1592
1593         switch (nv_encoder->dcb->type) {
1594         case DCB_OUTPUT_TMDS:
1595         case DCB_OUTPUT_DP:
1596                 proto = 0x0;
1597                 break;
1598         default:
1599                 BUG();
1600                 break;
1601         }
1602
1603         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1604         nv_encoder->crtc = encoder->crtc;
1605 }
1606
1607 static const struct drm_encoder_helper_funcs
1608 nv50_pior_help = {
1609         .atomic_check = nv50_pior_atomic_check,
1610         .enable = nv50_pior_enable,
1611         .disable = nv50_pior_disable,
1612 };
1613
1614 static void
1615 nv50_pior_destroy(struct drm_encoder *encoder)
1616 {
1617         drm_encoder_cleanup(encoder);
1618         kfree(encoder);
1619 }
1620
1621 static const struct drm_encoder_funcs
1622 nv50_pior_func = {
1623         .destroy = nv50_pior_destroy,
1624 };
1625
1626 static int
1627 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1628 {
1629         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1630         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1631         struct nvkm_i2c_bus *bus = NULL;
1632         struct nvkm_i2c_aux *aux = NULL;
1633         struct i2c_adapter *ddc;
1634         struct nouveau_encoder *nv_encoder;
1635         struct drm_encoder *encoder;
1636         int type;
1637
1638         switch (dcbe->type) {
1639         case DCB_OUTPUT_TMDS:
1640                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1641                 ddc  = bus ? &bus->i2c : NULL;
1642                 type = DRM_MODE_ENCODER_TMDS;
1643                 break;
1644         case DCB_OUTPUT_DP:
1645                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1646                 ddc  = aux ? &aux->i2c : NULL;
1647                 type = DRM_MODE_ENCODER_TMDS;
1648                 break;
1649         default:
1650                 return -ENODEV;
1651         }
1652
1653         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1654         if (!nv_encoder)
1655                 return -ENOMEM;
1656         nv_encoder->dcb = dcbe;
1657         nv_encoder->i2c = ddc;
1658         nv_encoder->aux = aux;
1659
1660         encoder = to_drm_encoder(nv_encoder);
1661         encoder->possible_crtcs = dcbe->heads;
1662         encoder->possible_clones = 0;
1663         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1664                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1665         drm_encoder_helper_add(encoder, &nv50_pior_help);
1666
1667         drm_connector_attach_encoder(connector, encoder);
1668         return 0;
1669 }
1670
1671 /******************************************************************************
1672  * Atomic
1673  *****************************************************************************/
1674
1675 static void
1676 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1677 {
1678         struct nouveau_drm *drm = nouveau_drm(state->dev);
1679         struct nv50_disp *disp = nv50_disp(drm->dev);
1680         struct nv50_core *core = disp->core;
1681         struct nv50_mstm *mstm;
1682         struct drm_encoder *encoder;
1683
1684         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1685
1686         drm_for_each_encoder(encoder, drm->dev) {
1687                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1688                         mstm = nouveau_encoder(encoder)->dp.mstm;
1689                         if (mstm && mstm->modified)
1690                                 nv50_mstm_prepare(mstm);
1691                 }
1692         }
1693
1694         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1695         core->func->update(core, interlock, true);
1696         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1697                                        disp->core->chan.base.device))
1698                 NV_ERROR(drm, "core notifier timeout\n");
1699
1700         drm_for_each_encoder(encoder, drm->dev) {
1701                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1702                         mstm = nouveau_encoder(encoder)->dp.mstm;
1703                         if (mstm && mstm->modified)
1704                                 nv50_mstm_cleanup(mstm);
1705                 }
1706         }
1707 }
1708
1709 static void
1710 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1711 {
1712         struct drm_plane_state *new_plane_state;
1713         struct drm_plane *plane;
1714         int i;
1715
1716         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1717                 struct nv50_wndw *wndw = nv50_wndw(plane);
1718                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1719                         if (wndw->func->update)
1720                                 wndw->func->update(wndw, interlock);
1721                 }
1722         }
1723 }
1724
1725 static void
1726 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1727 {
1728         struct drm_device *dev = state->dev;
1729         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1730         struct drm_crtc *crtc;
1731         struct drm_plane_state *new_plane_state;
1732         struct drm_plane *plane;
1733         struct nouveau_drm *drm = nouveau_drm(dev);
1734         struct nv50_disp *disp = nv50_disp(dev);
1735         struct nv50_atom *atom = nv50_atom(state);
1736         struct nv50_outp_atom *outp, *outt;
1737         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1738         int i;
1739
1740         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1741         drm_atomic_helper_wait_for_fences(dev, state, false);
1742         drm_atomic_helper_wait_for_dependencies(state);
1743         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1744
1745         if (atom->lock_core)
1746                 mutex_lock(&disp->mutex);
1747
1748         /* Disable head(s). */
1749         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1750                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1751                 struct nv50_head *head = nv50_head(crtc);
1752
1753                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1754                           asyh->clr.mask, asyh->set.mask);
1755                 if (old_crtc_state->active && !new_crtc_state->active)
1756                         drm_crtc_vblank_off(crtc);
1757
1758                 if (asyh->clr.mask) {
1759                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1760                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1761                 }
1762         }
1763
1764         /* Disable plane(s). */
1765         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1766                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1767                 struct nv50_wndw *wndw = nv50_wndw(plane);
1768
1769                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1770                           asyw->clr.mask, asyw->set.mask);
1771                 if (!asyw->clr.mask)
1772                         continue;
1773
1774                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1775         }
1776
1777         /* Disable output path(s). */
1778         list_for_each_entry(outp, &atom->outp, head) {
1779                 const struct drm_encoder_helper_funcs *help;
1780                 struct drm_encoder *encoder;
1781
1782                 encoder = outp->encoder;
1783                 help = encoder->helper_private;
1784
1785                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1786                           outp->clr.mask, outp->set.mask);
1787
1788                 if (outp->clr.mask) {
1789                         help->disable(encoder);
1790                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1791                         if (outp->flush_disable) {
1792                                 nv50_disp_atomic_commit_wndw(state, interlock);
1793                                 nv50_disp_atomic_commit_core(state, interlock);
1794                                 memset(interlock, 0x00, sizeof(interlock));
1795                         }
1796                 }
1797         }
1798
1799         /* Flush disable. */
1800         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1801                 if (atom->flush_disable) {
1802                         nv50_disp_atomic_commit_wndw(state, interlock);
1803                         nv50_disp_atomic_commit_core(state, interlock);
1804                         memset(interlock, 0x00, sizeof(interlock));
1805                 }
1806         }
1807
1808         /* Update output path(s). */
1809         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1810                 const struct drm_encoder_helper_funcs *help;
1811                 struct drm_encoder *encoder;
1812
1813                 encoder = outp->encoder;
1814                 help = encoder->helper_private;
1815
1816                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1817                           outp->set.mask, outp->clr.mask);
1818
1819                 if (outp->set.mask) {
1820                         help->enable(encoder);
1821                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1822                 }
1823
1824                 list_del(&outp->head);
1825                 kfree(outp);
1826         }
1827
1828         /* Update head(s). */
1829         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1830                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1831                 struct nv50_head *head = nv50_head(crtc);
1832
1833                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1834                           asyh->set.mask, asyh->clr.mask);
1835
1836                 if (asyh->set.mask) {
1837                         nv50_head_flush_set(head, asyh);
1838                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1839                 }
1840
1841                 if (new_crtc_state->active) {
1842                         if (!old_crtc_state->active)
1843                                 drm_crtc_vblank_on(crtc);
1844                         if (new_crtc_state->event)
1845                                 drm_crtc_vblank_get(crtc);
1846                 }
1847         }
1848
1849         /* Update plane(s). */
1850         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1851                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1852                 struct nv50_wndw *wndw = nv50_wndw(plane);
1853
1854                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1855                           asyw->set.mask, asyw->clr.mask);
1856                 if ( !asyw->set.mask &&
1857                     (!asyw->clr.mask || atom->flush_disable))
1858                         continue;
1859
1860                 nv50_wndw_flush_set(wndw, interlock, asyw);
1861         }
1862
1863         /* Flush update. */
1864         nv50_disp_atomic_commit_wndw(state, interlock);
1865
1866         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1867                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1868                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1869                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1870                     !atom->state.legacy_cursor_update)
1871                         nv50_disp_atomic_commit_core(state, interlock);
1872                 else
1873                         disp->core->func->update(disp->core, interlock, false);
1874         }
1875
1876         if (atom->lock_core)
1877                 mutex_unlock(&disp->mutex);
1878
1879         /* Wait for HW to signal completion. */
1880         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1881                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1882                 struct nv50_wndw *wndw = nv50_wndw(plane);
1883                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1884                 if (ret)
1885                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1886         }
1887
1888         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1889                 if (new_crtc_state->event) {
1890                         unsigned long flags;
1891                         /* Get correct count/ts if racing with vblank irq */
1892                         if (new_crtc_state->active)
1893                                 drm_crtc_accurate_vblank_count(crtc);
1894                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1895                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1896                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1897
1898                         new_crtc_state->event = NULL;
1899                         if (new_crtc_state->active)
1900                                 drm_crtc_vblank_put(crtc);
1901                 }
1902         }
1903
1904         drm_atomic_helper_commit_hw_done(state);
1905         drm_atomic_helper_cleanup_planes(dev, state);
1906         drm_atomic_helper_commit_cleanup_done(state);
1907         drm_atomic_state_put(state);
1908 }
1909
1910 static void
1911 nv50_disp_atomic_commit_work(struct work_struct *work)
1912 {
1913         struct drm_atomic_state *state =
1914                 container_of(work, typeof(*state), commit_work);
1915         nv50_disp_atomic_commit_tail(state);
1916 }
1917
1918 static int
1919 nv50_disp_atomic_commit(struct drm_device *dev,
1920                         struct drm_atomic_state *state, bool nonblock)
1921 {
1922         struct nouveau_drm *drm = nouveau_drm(dev);
1923         struct drm_plane_state *new_plane_state;
1924         struct drm_plane *plane;
1925         struct drm_crtc *crtc;
1926         bool active = false;
1927         int ret, i;
1928
1929         ret = pm_runtime_get_sync(dev->dev);
1930         if (ret < 0 && ret != -EACCES)
1931                 return ret;
1932
1933         ret = drm_atomic_helper_setup_commit(state, nonblock);
1934         if (ret)
1935                 goto done;
1936
1937         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1938
1939         ret = drm_atomic_helper_prepare_planes(dev, state);
1940         if (ret)
1941                 goto done;
1942
1943         if (!nonblock) {
1944                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1945                 if (ret)
1946                         goto err_cleanup;
1947         }
1948
1949         ret = drm_atomic_helper_swap_state(state, true);
1950         if (ret)
1951                 goto err_cleanup;
1952
1953         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1954                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1955                 struct nv50_wndw *wndw = nv50_wndw(plane);
1956
1957                 if (asyw->set.image)
1958                         nv50_wndw_ntfy_enable(wndw, asyw);
1959         }
1960
1961         drm_atomic_state_get(state);
1962
1963         if (nonblock)
1964                 queue_work(system_unbound_wq, &state->commit_work);
1965         else
1966                 nv50_disp_atomic_commit_tail(state);
1967
1968         drm_for_each_crtc(crtc, dev) {
1969                 if (crtc->state->active) {
1970                         if (!drm->have_disp_power_ref) {
1971                                 drm->have_disp_power_ref = true;
1972                                 return 0;
1973                         }
1974                         active = true;
1975                         break;
1976                 }
1977         }
1978
1979         if (!active && drm->have_disp_power_ref) {
1980                 pm_runtime_put_autosuspend(dev->dev);
1981                 drm->have_disp_power_ref = false;
1982         }
1983
1984 err_cleanup:
1985         if (ret)
1986                 drm_atomic_helper_cleanup_planes(dev, state);
1987 done:
1988         pm_runtime_put_autosuspend(dev->dev);
1989         return ret;
1990 }
1991
1992 static struct nv50_outp_atom *
1993 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
1994 {
1995         struct nv50_outp_atom *outp;
1996
1997         list_for_each_entry(outp, &atom->outp, head) {
1998                 if (outp->encoder == encoder)
1999                         return outp;
2000         }
2001
2002         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2003         if (!outp)
2004                 return ERR_PTR(-ENOMEM);
2005
2006         list_add(&outp->head, &atom->outp);
2007         outp->encoder = encoder;
2008         return outp;
2009 }
2010
2011 static int
2012 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2013                                 struct drm_connector_state *old_connector_state)
2014 {
2015         struct drm_encoder *encoder = old_connector_state->best_encoder;
2016         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2017         struct drm_crtc *crtc;
2018         struct nv50_outp_atom *outp;
2019
2020         if (!(crtc = old_connector_state->crtc))
2021                 return 0;
2022
2023         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2024         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2025         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2026                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2027                 if (IS_ERR(outp))
2028                         return PTR_ERR(outp);
2029
2030                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2031                         outp->flush_disable = true;
2032                         atom->flush_disable = true;
2033                 }
2034                 outp->clr.ctrl = true;
2035                 atom->lock_core = true;
2036         }
2037
2038         return 0;
2039 }
2040
2041 static int
2042 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2043                                 struct drm_connector_state *connector_state)
2044 {
2045         struct drm_encoder *encoder = connector_state->best_encoder;
2046         struct drm_crtc_state *new_crtc_state;
2047         struct drm_crtc *crtc;
2048         struct nv50_outp_atom *outp;
2049
2050         if (!(crtc = connector_state->crtc))
2051                 return 0;
2052
2053         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2054         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2055                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2056                 if (IS_ERR(outp))
2057                         return PTR_ERR(outp);
2058
2059                 outp->set.ctrl = true;
2060                 atom->lock_core = true;
2061         }
2062
2063         return 0;
2064 }
2065
2066 static int
2067 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2068 {
2069         struct nv50_atom *atom = nv50_atom(state);
2070         struct drm_connector_state *old_connector_state, *new_connector_state;
2071         struct drm_connector *connector;
2072         struct drm_crtc_state *new_crtc_state;
2073         struct drm_crtc *crtc;
2074         int ret, i;
2075
2076         /* We need to handle colour management on a per-plane basis. */
2077         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2078                 if (new_crtc_state->color_mgmt_changed) {
2079                         ret = drm_atomic_add_affected_planes(state, crtc);
2080                         if (ret)
2081                                 return ret;
2082                 }
2083         }
2084
2085         ret = drm_atomic_helper_check(dev, state);
2086         if (ret)
2087                 return ret;
2088
2089         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2090                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2091                 if (ret)
2092                         return ret;
2093
2094                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2095                 if (ret)
2096                         return ret;
2097         }
2098
2099         return 0;
2100 }
2101
2102 static void
2103 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2104 {
2105         struct nv50_atom *atom = nv50_atom(state);
2106         struct nv50_outp_atom *outp, *outt;
2107
2108         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2109                 list_del(&outp->head);
2110                 kfree(outp);
2111         }
2112
2113         drm_atomic_state_default_clear(state);
2114 }
2115
2116 static void
2117 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2118 {
2119         struct nv50_atom *atom = nv50_atom(state);
2120         drm_atomic_state_default_release(&atom->state);
2121         kfree(atom);
2122 }
2123
2124 static struct drm_atomic_state *
2125 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2126 {
2127         struct nv50_atom *atom;
2128         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2129             drm_atomic_state_init(dev, &atom->state) < 0) {
2130                 kfree(atom);
2131                 return NULL;
2132         }
2133         INIT_LIST_HEAD(&atom->outp);
2134         return &atom->state;
2135 }
2136
2137 static const struct drm_mode_config_funcs
2138 nv50_disp_func = {
2139         .fb_create = nouveau_user_framebuffer_create,
2140         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2141         .atomic_check = nv50_disp_atomic_check,
2142         .atomic_commit = nv50_disp_atomic_commit,
2143         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2144         .atomic_state_clear = nv50_disp_atomic_state_clear,
2145         .atomic_state_free = nv50_disp_atomic_state_free,
2146 };
2147
2148 /******************************************************************************
2149  * Init
2150  *****************************************************************************/
2151
2152 void
2153 nv50_display_fini(struct drm_device *dev)
2154 {
2155         struct nouveau_encoder *nv_encoder;
2156         struct drm_encoder *encoder;
2157         struct drm_plane *plane;
2158
2159         drm_for_each_plane(plane, dev) {
2160                 struct nv50_wndw *wndw = nv50_wndw(plane);
2161                 if (plane->funcs != &nv50_wndw)
2162                         continue;
2163                 nv50_wndw_fini(wndw);
2164         }
2165
2166         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2167                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2168                         nv_encoder = nouveau_encoder(encoder);
2169                         nv50_mstm_fini(nv_encoder->dp.mstm);
2170                 }
2171         }
2172 }
2173
2174 int
2175 nv50_display_init(struct drm_device *dev)
2176 {
2177         struct nv50_core *core = nv50_disp(dev)->core;
2178         struct drm_encoder *encoder;
2179         struct drm_plane *plane;
2180
2181         core->func->init(core);
2182
2183         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2184                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2185                         struct nouveau_encoder *nv_encoder =
2186                                 nouveau_encoder(encoder);
2187                         nv50_mstm_init(nv_encoder->dp.mstm);
2188                 }
2189         }
2190
2191         drm_for_each_plane(plane, dev) {
2192                 struct nv50_wndw *wndw = nv50_wndw(plane);
2193                 if (plane->funcs != &nv50_wndw)
2194                         continue;
2195                 nv50_wndw_init(wndw);
2196         }
2197
2198         return 0;
2199 }
2200
2201 void
2202 nv50_display_destroy(struct drm_device *dev)
2203 {
2204         struct nv50_disp *disp = nv50_disp(dev);
2205
2206         nv50_core_del(&disp->core);
2207
2208         nouveau_bo_unmap(disp->sync);
2209         if (disp->sync)
2210                 nouveau_bo_unpin(disp->sync);
2211         nouveau_bo_ref(NULL, &disp->sync);
2212
2213         nouveau_display(dev)->priv = NULL;
2214         kfree(disp);
2215 }
2216
2217 int
2218 nv50_display_create(struct drm_device *dev)
2219 {
2220         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2221         struct nouveau_drm *drm = nouveau_drm(dev);
2222         struct dcb_table *dcb = &drm->vbios.dcb;
2223         struct drm_connector *connector, *tmp;
2224         struct nv50_disp *disp;
2225         struct dcb_output *dcbe;
2226         int crtcs, ret, i;
2227
2228         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2229         if (!disp)
2230                 return -ENOMEM;
2231
2232         mutex_init(&disp->mutex);
2233
2234         nouveau_display(dev)->priv = disp;
2235         nouveau_display(dev)->dtor = nv50_display_destroy;
2236         nouveau_display(dev)->init = nv50_display_init;
2237         nouveau_display(dev)->fini = nv50_display_fini;
2238         disp->disp = &nouveau_display(dev)->disp;
2239         dev->mode_config.funcs = &nv50_disp_func;
2240         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2241
2242         /* small shared memory area we use for notifiers and semaphores */
2243         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2244                              0, 0x0000, NULL, NULL, &disp->sync);
2245         if (!ret) {
2246                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2247                 if (!ret) {
2248                         ret = nouveau_bo_map(disp->sync);
2249                         if (ret)
2250                                 nouveau_bo_unpin(disp->sync);
2251                 }
2252                 if (ret)
2253                         nouveau_bo_ref(NULL, &disp->sync);
2254         }
2255
2256         if (ret)
2257                 goto out;
2258
2259         /* allocate master evo channel */
2260         ret = nv50_core_new(drm, &disp->core);
2261         if (ret)
2262                 goto out;
2263
2264         /* create crtc objects to represent the hw heads */
2265         if (disp->disp->object.oclass >= GV100_DISP)
2266                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2267         else
2268         if (disp->disp->object.oclass >= GF110_DISP)
2269                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2270         else
2271                 crtcs = 0x3;
2272
2273         for (i = 0; i < fls(crtcs); i++) {
2274                 if (!(crtcs & (1 << i)))
2275                         continue;
2276                 ret = nv50_head_create(dev, i);
2277                 if (ret)
2278                         goto out;
2279         }
2280
2281         /* create encoder/connector objects based on VBIOS DCB table */
2282         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2283                 connector = nouveau_connector_create(dev, dcbe->connector);
2284                 if (IS_ERR(connector))
2285                         continue;
2286
2287                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2288                         switch (dcbe->type) {
2289                         case DCB_OUTPUT_TMDS:
2290                         case DCB_OUTPUT_LVDS:
2291                         case DCB_OUTPUT_DP:
2292                                 ret = nv50_sor_create(connector, dcbe);
2293                                 break;
2294                         case DCB_OUTPUT_ANALOG:
2295                                 ret = nv50_dac_create(connector, dcbe);
2296                                 break;
2297                         default:
2298                                 ret = -ENODEV;
2299                                 break;
2300                         }
2301                 } else {
2302                         ret = nv50_pior_create(connector, dcbe);
2303                 }
2304
2305                 if (ret) {
2306                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2307                                      dcbe->location, dcbe->type,
2308                                      ffs(dcbe->or) - 1, ret);
2309                         ret = 0;
2310                 }
2311         }
2312
2313         /* cull any connectors we created that don't have an encoder */
2314         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2315                 if (connector->encoder_ids[0])
2316                         continue;
2317
2318                 NV_WARN(drm, "%s has no encoders, removing\n",
2319                         connector->name);
2320                 connector->funcs->destroy(connector);
2321         }
2322
2323         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2324         dev->vblank_disable_immediate = true;
2325
2326 out:
2327         if (ret)
2328                 nv50_display_destroy(dev);
2329         return ret;
2330 }