2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
31 #include <linux/dma-mapping.h>
32 #include <linux/hdmi.h>
33 #include <linux/component.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_fb_helper.h>
39 #include <drm/drm_plane_helper.h>
40 #include <drm/drm_probe_helper.h>
41 #include <drm/drm_scdc_helper.h>
42 #include <drm/drm_vblank.h>
44 #include <nvif/push507c.h>
46 #include <nvif/class.h>
47 #include <nvif/cl0002.h>
48 #include <nvif/cl5070.h>
49 #include <nvif/cl507d.h>
50 #include <nvif/event.h>
51 #include <nvif/timer.h>
53 #include <nvhw/class/cl507c.h>
54 #include <nvhw/class/cl507d.h>
55 #include <nvhw/class/cl837d.h>
56 #include <nvhw/class/cl887d.h>
57 #include <nvhw/class/cl907d.h>
58 #include <nvhw/class/cl917d.h>
60 #include "nouveau_drv.h"
61 #include "nouveau_dma.h"
62 #include "nouveau_gem.h"
63 #include "nouveau_connector.h"
64 #include "nouveau_encoder.h"
65 #include "nouveau_fence.h"
66 #include "nouveau_fbcon.h"
68 #include <subdev/bios/dp.h>
70 /******************************************************************************
72 *****************************************************************************/
75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
76 const s32 *oclass, u8 head, void *data, u32 size,
77 struct nv50_chan *chan)
79 struct nvif_sclass *sclass;
82 chan->device = device;
84 ret = n = nvif_object_sclass_get(disp, &sclass);
89 for (i = 0; i < n; i++) {
90 if (sclass[i].oclass == oclass[0]) {
91 ret = nvif_object_ctor(disp, "kmsChan", 0,
92 oclass[0], data, size,
95 nvif_object_map(&chan->user, NULL, 0);
96 nvif_object_sclass_put(&sclass);
103 nvif_object_sclass_put(&sclass);
108 nv50_chan_destroy(struct nv50_chan *chan)
110 nvif_object_dtor(&chan->user);
113 /******************************************************************************
115 *****************************************************************************/
118 nv50_dmac_destroy(struct nv50_dmac *dmac)
120 nvif_object_dtor(&dmac->vram);
121 nvif_object_dtor(&dmac->sync);
123 nv50_chan_destroy(&dmac->base);
125 nvif_mem_dtor(&dmac->_push.mem);
129 nv50_dmac_kick(struct nvif_push *push)
131 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
133 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
134 if (dmac->put != dmac->cur) {
135 /* Push buffer fetches are not coherent with BAR1, we need to ensure
136 * writes have been flushed right through to VRAM before writing PUT.
138 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
139 struct nvif_device *device = dmac->base.device;
140 nvif_wr32(&device->object, 0x070000, 0x00000001);
141 nvif_msec(device, 2000,
142 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
147 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
148 dmac->put = dmac->cur;
151 push->bgn = push->cur;
155 nv50_dmac_free(struct nv50_dmac *dmac)
157 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
158 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
159 return get - dmac->cur - 5;
160 return dmac->max - dmac->cur;
164 nv50_dmac_wind(struct nv50_dmac *dmac)
166 /* Wait for GET to depart from the beginning of the push buffer to
167 * prevent writing PUT == GET, which would be ignored by HW.
169 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
171 /* Corner-case, HW idle, but non-committed work pending. */
173 nv50_dmac_kick(dmac->push);
175 if (nvif_msec(dmac->base.device, 2000,
176 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
182 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
188 nv50_dmac_wait(struct nvif_push *push, u32 size)
190 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
193 if (WARN_ON(size > dmac->max))
196 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
197 if (dmac->cur + size >= dmac->max) {
198 int ret = nv50_dmac_wind(dmac);
202 push->cur = dmac->_push.mem.object.map.ptr;
203 push->cur = push->cur + dmac->cur;
204 nv50_dmac_kick(push);
207 if (nvif_msec(dmac->base.device, 2000,
208 if ((free = nv50_dmac_free(dmac)) >= size)
215 push->bgn = dmac->_push.mem.object.map.ptr;
216 push->bgn = push->bgn + dmac->cur;
217 push->cur = push->bgn;
218 push->end = push->cur + free;
223 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
224 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
225 struct nv50_dmac *dmac)
227 struct nouveau_cli *cli = (void *)device->object.client;
228 struct nv50_disp_core_channel_dma_v0 *args = data;
229 u8 type = NVIF_MEM_COHERENT;
232 mutex_init(&dmac->lock);
234 /* Pascal added support for 47-bit physical addresses, but some
235 * parts of EVO still only accept 40-bit PAs.
237 * To avoid issues on systems with large amounts of RAM, and on
238 * systems where an IOMMU maps pages at a high address, we need
239 * to allocate push buffers in VRAM instead.
241 * This appears to match NVIDIA's behaviour on Pascal.
243 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
244 type |= NVIF_MEM_VRAM;
246 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
251 dmac->ptr = dmac->_push.mem.object.map.ptr;
252 dmac->_push.wait = nv50_dmac_wait;
253 dmac->_push.kick = nv50_dmac_kick;
254 dmac->push = &dmac->_push;
255 dmac->push->bgn = dmac->_push.mem.object.map.ptr;
256 dmac->push->cur = dmac->push->bgn;
257 dmac->push->end = dmac->push->bgn;
258 dmac->max = 0x1000/4 - 1;
260 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
262 ret = nv50_chan_create(device, disp, oclass, head, data, size,
270 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
272 &(struct nv_dma_v0) {
273 .target = NV_DMA_V0_TARGET_VRAM,
274 .access = NV_DMA_V0_ACCESS_RDWR,
275 .start = syncbuf + 0x0000,
276 .limit = syncbuf + 0x0fff,
277 }, sizeof(struct nv_dma_v0),
282 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
284 &(struct nv_dma_v0) {
285 .target = NV_DMA_V0_TARGET_VRAM,
286 .access = NV_DMA_V0_ACCESS_RDWR,
288 .limit = device->info.ram_user - 1,
289 }, sizeof(struct nv_dma_v0),
297 /******************************************************************************
298 * Output path helpers
299 *****************************************************************************/
301 nv50_outp_release(struct nouveau_encoder *nv_encoder)
303 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
305 struct nv50_disp_mthd_v1 base;
308 .base.method = NV50_DISP_MTHD_V1_RELEASE,
309 .base.hasht = nv_encoder->dcb->hasht,
310 .base.hashm = nv_encoder->dcb->hashm,
313 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
315 nv_encoder->link = 0;
319 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
321 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
322 struct nv50_disp *disp = nv50_disp(drm->dev);
324 struct nv50_disp_mthd_v1 base;
325 struct nv50_disp_acquire_v0 info;
328 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
329 .base.hasht = nv_encoder->dcb->hasht,
330 .base.hashm = nv_encoder->dcb->hashm,
335 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
337 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
341 nv_encoder->or = args.info.or;
342 nv_encoder->link = args.info.link;
347 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
348 struct drm_crtc_state *crtc_state,
349 struct drm_connector_state *conn_state,
350 struct drm_display_mode *native_mode)
352 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
353 struct drm_display_mode *mode = &crtc_state->mode;
354 struct drm_connector *connector = conn_state->connector;
355 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
356 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
358 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
359 asyc->scaler.full = false;
363 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
364 switch (connector->connector_type) {
365 case DRM_MODE_CONNECTOR_LVDS:
366 case DRM_MODE_CONNECTOR_eDP:
367 /* Don't force scaler for EDID modes with
368 * same size as the native one (e.g. different
371 if (mode->hdisplay == native_mode->hdisplay &&
372 mode->vdisplay == native_mode->vdisplay &&
373 mode->type & DRM_MODE_TYPE_DRIVER)
376 asyc->scaler.full = true;
385 if (!drm_mode_equal(adjusted_mode, mode)) {
386 drm_mode_copy(adjusted_mode, mode);
387 crtc_state->mode_changed = true;
394 nv50_outp_atomic_check(struct drm_encoder *encoder,
395 struct drm_crtc_state *crtc_state,
396 struct drm_connector_state *conn_state)
398 struct drm_connector *connector = conn_state->connector;
399 struct nouveau_connector *nv_connector = nouveau_connector(connector);
400 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
403 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
404 nv_connector->native_mode);
408 if (crtc_state->mode_changed || crtc_state->connectors_changed)
409 asyh->or.bpc = connector->display_info.bpc;
414 /******************************************************************************
416 *****************************************************************************/
418 nv50_dac_disable(struct drm_encoder *encoder)
420 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
421 struct nv50_core *core = nv50_disp(encoder->dev)->core;
422 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
423 if (nv_encoder->crtc)
424 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
425 nv_encoder->crtc = NULL;
426 nv50_outp_release(nv_encoder);
430 nv50_dac_enable(struct drm_encoder *encoder)
432 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
433 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
434 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
435 struct nv50_core *core = nv50_disp(encoder->dev)->core;
438 switch (nv_crtc->index) {
439 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
440 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
441 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
442 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
448 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
450 nv50_outp_acquire(nv_encoder, false);
452 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
455 nv_encoder->crtc = encoder->crtc;
458 static enum drm_connector_status
459 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
461 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
462 struct nv50_disp *disp = nv50_disp(encoder->dev);
464 struct nv50_disp_mthd_v1 base;
465 struct nv50_disp_dac_load_v0 load;
468 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
469 .base.hasht = nv_encoder->dcb->hasht,
470 .base.hashm = nv_encoder->dcb->hashm,
474 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
475 if (args.load.data == 0)
476 args.load.data = 340;
478 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
479 if (ret || !args.load.load)
480 return connector_status_disconnected;
482 return connector_status_connected;
485 static const struct drm_encoder_helper_funcs
487 .atomic_check = nv50_outp_atomic_check,
488 .enable = nv50_dac_enable,
489 .disable = nv50_dac_disable,
490 .detect = nv50_dac_detect
494 nv50_dac_destroy(struct drm_encoder *encoder)
496 drm_encoder_cleanup(encoder);
500 static const struct drm_encoder_funcs
502 .destroy = nv50_dac_destroy,
506 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
508 struct nouveau_drm *drm = nouveau_drm(connector->dev);
509 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
510 struct nvkm_i2c_bus *bus;
511 struct nouveau_encoder *nv_encoder;
512 struct drm_encoder *encoder;
513 int type = DRM_MODE_ENCODER_DAC;
515 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
518 nv_encoder->dcb = dcbe;
520 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
522 nv_encoder->i2c = &bus->i2c;
524 encoder = to_drm_encoder(nv_encoder);
525 encoder->possible_crtcs = dcbe->heads;
526 encoder->possible_clones = 0;
527 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
528 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
529 drm_encoder_helper_add(encoder, &nv50_dac_help);
531 drm_connector_attach_encoder(connector, encoder);
536 * audio component binding for ELD notification
539 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
542 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
543 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
548 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
549 bool *enabled, unsigned char *buf, int max_bytes)
551 struct drm_device *drm_dev = dev_get_drvdata(kdev);
552 struct nouveau_drm *drm = nouveau_drm(drm_dev);
553 struct drm_encoder *encoder;
554 struct nouveau_encoder *nv_encoder;
555 struct nouveau_connector *nv_connector;
556 struct nouveau_crtc *nv_crtc;
560 drm_for_each_encoder(encoder, drm->dev) {
561 nv_encoder = nouveau_encoder(encoder);
562 nv_connector = nouveau_encoder_connector_get(nv_encoder);
563 nv_crtc = nouveau_crtc(encoder->crtc);
564 if (!nv_connector || !nv_crtc || nv_encoder->or != port ||
565 nv_crtc->index != dev_id)
567 *enabled = nv_encoder->audio;
569 ret = drm_eld_size(nv_connector->base.eld);
570 memcpy(buf, nv_connector->base.eld,
571 min(max_bytes, ret));
578 static const struct drm_audio_component_ops nv50_audio_component_ops = {
579 .get_eld = nv50_audio_component_get_eld,
583 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
586 struct drm_device *drm_dev = dev_get_drvdata(kdev);
587 struct nouveau_drm *drm = nouveau_drm(drm_dev);
588 struct drm_audio_component *acomp = data;
590 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
593 drm_modeset_lock_all(drm_dev);
594 acomp->ops = &nv50_audio_component_ops;
596 drm->audio.component = acomp;
597 drm_modeset_unlock_all(drm_dev);
602 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
605 struct drm_device *drm_dev = dev_get_drvdata(kdev);
606 struct nouveau_drm *drm = nouveau_drm(drm_dev);
607 struct drm_audio_component *acomp = data;
609 drm_modeset_lock_all(drm_dev);
610 drm->audio.component = NULL;
613 drm_modeset_unlock_all(drm_dev);
616 static const struct component_ops nv50_audio_component_bind_ops = {
617 .bind = nv50_audio_component_bind,
618 .unbind = nv50_audio_component_unbind,
622 nv50_audio_component_init(struct nouveau_drm *drm)
624 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
625 drm->audio.component_registered = true;
629 nv50_audio_component_fini(struct nouveau_drm *drm)
631 if (drm->audio.component_registered) {
632 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
633 drm->audio.component_registered = false;
637 /******************************************************************************
639 *****************************************************************************/
641 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
643 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
644 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
645 struct nv50_disp *disp = nv50_disp(encoder->dev);
647 struct nv50_disp_mthd_v1 base;
648 struct nv50_disp_sor_hda_eld_v0 eld;
651 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
652 .base.hasht = nv_encoder->dcb->hasht,
653 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
654 (0x0100 << nv_crtc->index),
657 if (!nv_encoder->audio)
660 nv_encoder->audio = false;
661 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
663 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
668 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
670 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
671 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
672 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
673 struct nouveau_connector *nv_connector;
674 struct nv50_disp *disp = nv50_disp(encoder->dev);
677 struct nv50_disp_mthd_v1 mthd;
678 struct nv50_disp_sor_hda_eld_v0 eld;
680 u8 data[sizeof(nv_connector->base.eld)];
682 .base.mthd.version = 1,
683 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
684 .base.mthd.hasht = nv_encoder->dcb->hasht,
685 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
686 (0x0100 << nv_crtc->index),
689 nv_connector = nouveau_encoder_connector_get(nv_encoder);
690 if (!drm_detect_monitor_audio(nv_connector->edid))
693 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
695 nvif_mthd(&disp->disp->object, 0, &args,
696 sizeof(args.base) + drm_eld_size(args.data));
697 nv_encoder->audio = true;
699 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
703 /******************************************************************************
705 *****************************************************************************/
707 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
709 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
710 struct nv50_disp *disp = nv50_disp(encoder->dev);
712 struct nv50_disp_mthd_v1 base;
713 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
716 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
717 .base.hasht = nv_encoder->dcb->hasht,
718 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
719 (0x0100 << nv_crtc->index),
722 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
726 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
728 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
729 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
730 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
731 struct nv50_disp *disp = nv50_disp(encoder->dev);
733 struct nv50_disp_mthd_v1 base;
734 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
735 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
738 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
739 .base.hasht = nv_encoder->dcb->hasht,
740 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
741 (0x0100 << nv_crtc->index),
743 .pwr.rekey = 56, /* binary driver, and tegra, constant */
745 struct nouveau_connector *nv_connector;
746 struct drm_hdmi_info *hdmi;
748 union hdmi_infoframe avi_frame;
749 union hdmi_infoframe vendor_frame;
750 bool high_tmds_clock_ratio = false, scrambling = false;
755 nv_connector = nouveau_encoder_connector_get(nv_encoder);
756 if (!drm_detect_hdmi_monitor(nv_connector->edid))
759 hdmi = &nv_connector->base.display_info.hdmi;
761 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
762 &nv_connector->base, mode);
764 /* We have an AVI InfoFrame, populate it to the display */
765 args.pwr.avi_infoframe_length
766 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
769 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
770 &nv_connector->base, mode);
772 /* We have a Vendor InfoFrame, populate it to the display */
773 args.pwr.vendor_infoframe_length
774 = hdmi_infoframe_pack(&vendor_frame,
776 + args.pwr.avi_infoframe_length,
780 max_ac_packet = mode->htotal - mode->hdisplay;
781 max_ac_packet -= args.pwr.rekey;
782 max_ac_packet -= 18; /* constant from tegra */
783 args.pwr.max_ac_packet = max_ac_packet / 32;
785 if (hdmi->scdc.scrambling.supported) {
786 high_tmds_clock_ratio = mode->clock > 340000;
787 scrambling = high_tmds_clock_ratio ||
788 hdmi->scdc.scrambling.low_rates;
792 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
793 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
795 size = sizeof(args.base)
797 + args.pwr.avi_infoframe_length
798 + args.pwr.vendor_infoframe_length;
799 nvif_mthd(&disp->disp->object, 0, &args, size);
801 nv50_audio_enable(encoder, mode);
803 /* If SCDC is supported by the downstream monitor, update
804 * divider / scrambling settings to what we programmed above.
806 if (!hdmi->scdc.scrambling.supported)
809 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
811 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
814 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
815 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
816 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
817 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
819 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
823 /******************************************************************************
825 *****************************************************************************/
826 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
827 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
828 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
831 struct nouveau_encoder *outp;
833 struct drm_dp_mst_topology_mgr mgr;
841 struct nv50_mstm *mstm;
842 struct drm_dp_mst_port *port;
843 struct drm_connector connector;
845 struct drm_display_mode *native;
850 struct drm_encoder encoder;
852 struct nv50_head *head;
853 struct nv50_mstc *mstc;
857 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
859 struct nv50_msto *msto;
861 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
862 return nouveau_encoder(encoder);
864 msto = nv50_msto(encoder);
867 return msto->mstc->mstm->outp;
870 static struct drm_dp_payload *
871 nv50_msto_payload(struct nv50_msto *msto)
873 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
874 struct nv50_mstc *mstc = msto->mstc;
875 struct nv50_mstm *mstm = mstc->mstm;
876 int vcpi = mstc->port->vcpi.vcpi, i;
878 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
880 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
881 for (i = 0; i < mstm->mgr.max_payloads; i++) {
882 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
883 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
884 mstm->outp->base.base.name, i, payload->vcpi,
885 payload->start_slot, payload->num_slots);
888 for (i = 0; i < mstm->mgr.max_payloads; i++) {
889 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
890 if (payload->vcpi == vcpi)
898 nv50_msto_cleanup(struct nv50_msto *msto)
900 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
901 struct nv50_mstc *mstc = msto->mstc;
902 struct nv50_mstm *mstm = mstc->mstm;
907 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
909 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
912 msto->disabled = false;
916 nv50_msto_prepare(struct nv50_msto *msto)
918 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
919 struct nv50_mstc *mstc = msto->mstc;
920 struct nv50_mstm *mstm = mstc->mstm;
922 struct nv50_disp_mthd_v1 base;
923 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
926 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
927 .base.hasht = mstm->outp->dcb->hasht,
928 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
929 (0x0100 << msto->head->base.index),
932 mutex_lock(&mstm->mgr.payload_lock);
934 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
935 if (mstc->port->vcpi.vcpi > 0) {
936 struct drm_dp_payload *payload = nv50_msto_payload(msto);
938 args.vcpi.start_slot = payload->start_slot;
939 args.vcpi.num_slots = payload->num_slots;
940 args.vcpi.pbn = mstc->port->vcpi.pbn;
941 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
945 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
946 msto->encoder.name, msto->head->base.base.name,
947 args.vcpi.start_slot, args.vcpi.num_slots,
948 args.vcpi.pbn, args.vcpi.aligned_pbn);
950 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
951 mutex_unlock(&mstm->mgr.payload_lock);
955 nv50_msto_atomic_check(struct drm_encoder *encoder,
956 struct drm_crtc_state *crtc_state,
957 struct drm_connector_state *conn_state)
959 struct drm_atomic_state *state = crtc_state->state;
960 struct drm_connector *connector = conn_state->connector;
961 struct nv50_mstc *mstc = nv50_mstc(connector);
962 struct nv50_mstm *mstm = mstc->mstm;
963 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
967 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
972 if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
976 * When restoring duplicated states, we need to make sure that the bw
977 * remains the same and avoid recalculating it, as the connector's bpc
978 * may have changed after the state was duplicated
980 if (!state->duplicated) {
981 const int clock = crtc_state->adjusted_mode.clock;
983 asyh->or.bpc = connector->display_info.bpc;
984 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
988 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
999 nv50_dp_bpc_to_depth(unsigned int bpc)
1002 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1003 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1005 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1010 nv50_msto_enable(struct drm_encoder *encoder)
1012 struct nv50_head *head = nv50_head(encoder->crtc);
1013 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
1014 struct nv50_msto *msto = nv50_msto(encoder);
1015 struct nv50_mstc *mstc = NULL;
1016 struct nv50_mstm *mstm = NULL;
1017 struct drm_connector *connector;
1018 struct drm_connector_list_iter conn_iter;
1022 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1023 drm_for_each_connector_iter(connector, &conn_iter) {
1024 if (connector->state->best_encoder == &msto->encoder) {
1025 mstc = nv50_mstc(connector);
1030 drm_connector_list_iter_end(&conn_iter);
1035 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
1038 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
1041 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
1043 if (mstm->outp->link & 1)
1044 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1046 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1048 mstm->outp->update(mstm->outp, head->base.index, armh, proto,
1049 nv50_dp_bpc_to_depth(armh->or.bpc));
1052 mstm->modified = true;
1056 nv50_msto_disable(struct drm_encoder *encoder)
1058 struct nv50_msto *msto = nv50_msto(encoder);
1059 struct nv50_mstc *mstc = msto->mstc;
1060 struct nv50_mstm *mstm = mstc->mstm;
1062 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
1064 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1065 mstm->modified = true;
1067 mstm->disabled = true;
1068 msto->disabled = true;
1071 static const struct drm_encoder_helper_funcs
1073 .disable = nv50_msto_disable,
1074 .enable = nv50_msto_enable,
1075 .atomic_check = nv50_msto_atomic_check,
1079 nv50_msto_destroy(struct drm_encoder *encoder)
1081 struct nv50_msto *msto = nv50_msto(encoder);
1082 drm_encoder_cleanup(&msto->encoder);
1086 static const struct drm_encoder_funcs
1088 .destroy = nv50_msto_destroy,
1091 static struct nv50_msto *
1092 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1094 struct nv50_msto *msto;
1097 msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1099 return ERR_PTR(-ENOMEM);
1101 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1102 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1105 return ERR_PTR(ret);
1108 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1109 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1114 static struct drm_encoder *
1115 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1116 struct drm_connector_state *connector_state)
1118 struct nv50_mstc *mstc = nv50_mstc(connector);
1119 struct drm_crtc *crtc = connector_state->crtc;
1121 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1124 return &nv50_head(crtc)->msto->encoder;
1127 static enum drm_mode_status
1128 nv50_mstc_mode_valid(struct drm_connector *connector,
1129 struct drm_display_mode *mode)
1131 struct nv50_mstc *mstc = nv50_mstc(connector);
1132 struct nouveau_encoder *outp = mstc->mstm->outp;
1134 /* TODO: calculate the PBN from the dotclock and validate against the
1135 * MSTB's max possible PBN
1138 return nv50_dp_mode_valid(connector, outp, mode, NULL);
1142 nv50_mstc_get_modes(struct drm_connector *connector)
1144 struct nv50_mstc *mstc = nv50_mstc(connector);
1147 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1148 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1150 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1153 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1154 * to 8 to save bandwidth on the topology. In the future, we'll want
1155 * to properly fix this by dynamically selecting the highest possible
1156 * bpc that would fit in the topology
1158 if (connector->display_info.bpc)
1159 connector->display_info.bpc =
1160 clamp(connector->display_info.bpc, 6U, 8U);
1162 connector->display_info.bpc = 8;
1165 drm_mode_destroy(mstc->connector.dev, mstc->native);
1166 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1171 nv50_mstc_atomic_check(struct drm_connector *connector,
1172 struct drm_atomic_state *state)
1174 struct nv50_mstc *mstc = nv50_mstc(connector);
1175 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1176 struct drm_connector_state *new_conn_state =
1177 drm_atomic_get_new_connector_state(state, connector);
1178 struct drm_connector_state *old_conn_state =
1179 drm_atomic_get_old_connector_state(state, connector);
1180 struct drm_crtc_state *crtc_state;
1181 struct drm_crtc *new_crtc = new_conn_state->crtc;
1183 if (!old_conn_state->crtc)
1186 /* We only want to free VCPI if this state disables the CRTC on this
1190 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1193 !drm_atomic_crtc_needs_modeset(crtc_state) ||
1198 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1202 nv50_mstc_detect(struct drm_connector *connector,
1203 struct drm_modeset_acquire_ctx *ctx, bool force)
1205 struct nv50_mstc *mstc = nv50_mstc(connector);
1208 if (drm_connector_is_unregistered(connector))
1209 return connector_status_disconnected;
1211 ret = pm_runtime_get_sync(connector->dev->dev);
1212 if (ret < 0 && ret != -EACCES) {
1213 pm_runtime_put_autosuspend(connector->dev->dev);
1214 return connector_status_disconnected;
1217 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1220 pm_runtime_mark_last_busy(connector->dev->dev);
1221 pm_runtime_put_autosuspend(connector->dev->dev);
1225 static const struct drm_connector_helper_funcs
1227 .get_modes = nv50_mstc_get_modes,
1228 .mode_valid = nv50_mstc_mode_valid,
1229 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1230 .atomic_check = nv50_mstc_atomic_check,
1231 .detect_ctx = nv50_mstc_detect,
1235 nv50_mstc_destroy(struct drm_connector *connector)
1237 struct nv50_mstc *mstc = nv50_mstc(connector);
1239 drm_connector_cleanup(&mstc->connector);
1240 drm_dp_mst_put_port_malloc(mstc->port);
1245 static const struct drm_connector_funcs
1247 .reset = nouveau_conn_reset,
1248 .fill_modes = drm_helper_probe_single_connector_modes,
1249 .destroy = nv50_mstc_destroy,
1250 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1251 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1252 .atomic_set_property = nouveau_conn_atomic_set_property,
1253 .atomic_get_property = nouveau_conn_atomic_get_property,
1257 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1258 const char *path, struct nv50_mstc **pmstc)
1260 struct drm_device *dev = mstm->outp->base.base.dev;
1261 struct drm_crtc *crtc;
1262 struct nv50_mstc *mstc;
1265 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1270 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1271 DRM_MODE_CONNECTOR_DisplayPort);
1278 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1280 mstc->connector.funcs->reset(&mstc->connector);
1281 nouveau_conn_attach_properties(&mstc->connector);
1283 drm_for_each_crtc(crtc, dev) {
1284 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1287 drm_connector_attach_encoder(&mstc->connector,
1288 &nv50_head(crtc)->msto->encoder);
1291 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1292 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1293 drm_connector_set_path_property(&mstc->connector, path);
1294 drm_dp_mst_get_port_malloc(port);
1299 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1301 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1302 struct drm_encoder *encoder;
1305 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1306 ret = drm_dp_check_act_status(&mstm->mgr);
1308 ret = drm_dp_update_payload_part2(&mstm->mgr);
1310 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1311 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1312 struct nv50_msto *msto = nv50_msto(encoder);
1313 struct nv50_mstc *mstc = msto->mstc;
1314 if (mstc && mstc->mstm == mstm)
1315 nv50_msto_cleanup(msto);
1319 mstm->modified = false;
1323 nv50_mstm_prepare(struct nv50_mstm *mstm)
1325 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1326 struct drm_encoder *encoder;
1329 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1330 ret = drm_dp_update_payload_part1(&mstm->mgr);
1332 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1333 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1334 struct nv50_msto *msto = nv50_msto(encoder);
1335 struct nv50_mstc *mstc = msto->mstc;
1336 if (mstc && mstc->mstm == mstm)
1337 nv50_msto_prepare(msto);
1341 if (mstm->disabled) {
1343 nv50_outp_release(mstm->outp);
1344 mstm->disabled = false;
1348 static struct drm_connector *
1349 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1350 struct drm_dp_mst_port *port, const char *path)
1352 struct nv50_mstm *mstm = nv50_mstm(mgr);
1353 struct nv50_mstc *mstc;
1356 ret = nv50_mstc_new(mstm, port, path, &mstc);
1360 return &mstc->connector;
1363 static const struct drm_dp_mst_topology_cbs
1365 .add_connector = nv50_mstm_add_connector,
1369 nv50_mstm_service(struct nv50_mstm *mstm)
1371 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1372 bool handled = true;
1380 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1382 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1386 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1390 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1395 nv50_mstm_remove(struct nv50_mstm *mstm)
1398 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1402 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1404 struct nouveau_encoder *outp = mstm->outp;
1406 struct nv50_disp_mthd_v1 base;
1407 struct nv50_disp_sor_dp_mst_link_v0 mst;
1410 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1411 .base.hasht = outp->dcb->hasht,
1412 .base.hashm = outp->dcb->hashm,
1415 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1416 struct nvif_object *disp = &drm->display->disp.object;
1420 /* Even if we're enabling MST, start with disabling the
1421 * branching unit to clear any sink-side MST topology state
1422 * that wasn't set by us
1424 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1429 /* Now, start initializing */
1430 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1437 return nvif_mthd(disp, 0, &args, sizeof(args));
1441 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1443 struct drm_dp_aux *aux;
1445 bool old_state, new_state;
1451 mutex_lock(&mstm->mgr.lock);
1453 old_state = mstm->mgr.mst_state;
1454 new_state = old_state;
1455 aux = mstm->mgr.aux;
1458 /* Just check that the MST hub is still as we expect it */
1459 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1460 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1461 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1464 } else if (dpcd[0] >= 0x12) {
1465 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1469 if (!(dpcd[1] & DP_MST_CAP))
1475 if (new_state == old_state) {
1476 mutex_unlock(&mstm->mgr.lock);
1480 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1484 mutex_unlock(&mstm->mgr.lock);
1486 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1488 return nv50_mstm_enable(mstm, dpcd[0], 0);
1493 mutex_unlock(&mstm->mgr.lock);
1498 nv50_mstm_fini(struct nv50_mstm *mstm)
1500 if (mstm && mstm->mgr.mst_state)
1501 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1505 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1509 if (!mstm || !mstm->mgr.mst_state)
1512 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1514 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1515 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1520 nv50_mstm_del(struct nv50_mstm **pmstm)
1522 struct nv50_mstm *mstm = *pmstm;
1524 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1531 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1532 int conn_base_id, struct nv50_mstm **pmstm)
1534 const int max_payloads = hweight8(outp->dcb->heads);
1535 struct drm_device *dev = outp->base.base.dev;
1536 struct nv50_mstm *mstm;
1540 /* This is a workaround for some monitors not functioning
1541 * correctly in MST mode on initial module load. I think
1542 * some bad interaction with the VBIOS may be responsible.
1544 * A good ol' off and on again seems to work here ;)
1546 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1547 if (ret >= 0 && dpcd >= 0x12)
1548 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1550 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1553 mstm->mgr.cbs = &nv50_mstm;
1555 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1556 max_payloads, conn_base_id);
1563 /******************************************************************************
1565 *****************************************************************************/
1567 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1568 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1570 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1571 struct nv50_core *core = disp->core;
1574 nv_encoder->ctrl &= ~BIT(head);
1575 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1576 nv_encoder->ctrl = 0;
1578 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1579 nv_encoder->ctrl |= BIT(head);
1580 asyh->or.depth = depth;
1583 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1587 nv50_sor_disable(struct drm_encoder *encoder)
1589 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1590 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1592 nv_encoder->crtc = NULL;
1595 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1599 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1601 pwr &= ~DP_SET_POWER_MASK;
1602 pwr |= DP_SET_POWER_D3;
1603 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1607 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1608 nv50_audio_disable(encoder, nv_crtc);
1609 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1610 nv50_outp_release(nv_encoder);
1615 nv50_sor_enable(struct drm_encoder *encoder)
1617 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1618 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1619 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1620 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1622 struct nv50_disp_mthd_v1 base;
1623 struct nv50_disp_sor_lvds_script_v0 lvds;
1626 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1627 .base.hasht = nv_encoder->dcb->hasht,
1628 .base.hashm = nv_encoder->dcb->hashm,
1630 struct nv50_disp *disp = nv50_disp(encoder->dev);
1631 struct drm_device *dev = encoder->dev;
1632 struct nouveau_drm *drm = nouveau_drm(dev);
1633 struct nouveau_connector *nv_connector;
1634 struct nvbios *bios = &drm->vbios;
1636 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1637 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1639 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1640 nv_encoder->crtc = encoder->crtc;
1642 if ((disp->disp->object.oclass == GT214_DISP ||
1643 disp->disp->object.oclass >= GF110_DISP) &&
1644 drm_detect_monitor_audio(nv_connector->edid))
1646 nv50_outp_acquire(nv_encoder, hda);
1648 switch (nv_encoder->dcb->type) {
1649 case DCB_OUTPUT_TMDS:
1650 if (nv_encoder->link & 1) {
1651 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1652 /* Only enable dual-link if:
1653 * - Need to (i.e. rate > 165MHz)
1655 * - Not an HDMI monitor, since there's no dual-link
1658 if (mode->clock >= 165000 &&
1659 nv_encoder->dcb->duallink_possible &&
1660 !drm_detect_hdmi_monitor(nv_connector->edid))
1661 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1663 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1666 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1668 case DCB_OUTPUT_LVDS:
1669 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1671 if (bios->fp_no_ddc) {
1672 if (bios->fp.dual_link)
1673 lvds.lvds.script |= 0x0100;
1674 if (bios->fp.if_is_24bit)
1675 lvds.lvds.script |= 0x0200;
1677 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1678 if (((u8 *)nv_connector->edid)[121] == 2)
1679 lvds.lvds.script |= 0x0100;
1681 if (mode->clock >= bios->fp.duallink_transition_clk) {
1682 lvds.lvds.script |= 0x0100;
1685 if (lvds.lvds.script & 0x0100) {
1686 if (bios->fp.strapless_is_24bit & 2)
1687 lvds.lvds.script |= 0x0200;
1689 if (bios->fp.strapless_is_24bit & 1)
1690 lvds.lvds.script |= 0x0200;
1693 if (asyh->or.bpc == 8)
1694 lvds.lvds.script |= 0x0200;
1697 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1700 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1702 if (nv_encoder->link & 1)
1703 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1705 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1707 nv50_audio_enable(encoder, mode);
1714 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1717 static const struct drm_encoder_helper_funcs
1719 .atomic_check = nv50_outp_atomic_check,
1720 .enable = nv50_sor_enable,
1721 .disable = nv50_sor_disable,
1725 nv50_sor_destroy(struct drm_encoder *encoder)
1727 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1728 nv50_mstm_del(&nv_encoder->dp.mstm);
1729 drm_encoder_cleanup(encoder);
1733 static const struct drm_encoder_funcs
1735 .destroy = nv50_sor_destroy,
1738 static bool nv50_has_mst(struct nouveau_drm *drm)
1740 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1742 u8 ver, hdr, cnt, len;
1744 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1745 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1749 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1751 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1752 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1753 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1754 struct nouveau_encoder *nv_encoder;
1755 struct drm_encoder *encoder;
1756 struct nv50_disp *disp = nv50_disp(connector->dev);
1759 switch (dcbe->type) {
1760 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1761 case DCB_OUTPUT_TMDS:
1764 type = DRM_MODE_ENCODER_TMDS;
1768 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1771 nv_encoder->dcb = dcbe;
1772 nv_encoder->update = nv50_sor_update;
1774 encoder = to_drm_encoder(nv_encoder);
1775 encoder->possible_crtcs = dcbe->heads;
1776 encoder->possible_clones = 0;
1777 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1778 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1779 drm_encoder_helper_add(encoder, &nv50_sor_help);
1781 drm_connector_attach_encoder(connector, encoder);
1783 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1785 if (dcbe->type == DCB_OUTPUT_DP) {
1786 struct nvkm_i2c_aux *aux =
1787 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1790 if (disp->disp->object.oclass < GF110_DISP) {
1791 /* HW has no support for address-only
1792 * transactions, so we're required to
1793 * use custom I2C-over-AUX code.
1795 nv_encoder->i2c = &aux->i2c;
1797 nv_encoder->i2c = &nv_connector->aux.ddc;
1799 nv_encoder->aux = aux;
1802 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1803 nv50_has_mst(drm)) {
1804 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1805 16, nv_connector->base.base.id,
1806 &nv_encoder->dp.mstm);
1811 struct nvkm_i2c_bus *bus =
1812 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1814 nv_encoder->i2c = &bus->i2c;
1820 /******************************************************************************
1822 *****************************************************************************/
1824 nv50_pior_atomic_check(struct drm_encoder *encoder,
1825 struct drm_crtc_state *crtc_state,
1826 struct drm_connector_state *conn_state)
1828 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1831 crtc_state->adjusted_mode.clock *= 2;
1836 nv50_pior_disable(struct drm_encoder *encoder)
1838 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1839 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1840 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1841 if (nv_encoder->crtc)
1842 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1843 nv_encoder->crtc = NULL;
1844 nv50_outp_release(nv_encoder);
1848 nv50_pior_enable(struct drm_encoder *encoder)
1850 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1851 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1852 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1853 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1856 switch (nv_crtc->index) {
1857 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1858 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1864 nv50_outp_acquire(nv_encoder, false);
1866 switch (asyh->or.bpc) {
1867 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1868 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1869 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1870 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1873 switch (nv_encoder->dcb->type) {
1874 case DCB_OUTPUT_TMDS:
1876 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1883 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
1884 nv_encoder->crtc = encoder->crtc;
1887 static const struct drm_encoder_helper_funcs
1889 .atomic_check = nv50_pior_atomic_check,
1890 .enable = nv50_pior_enable,
1891 .disable = nv50_pior_disable,
1895 nv50_pior_destroy(struct drm_encoder *encoder)
1897 drm_encoder_cleanup(encoder);
1901 static const struct drm_encoder_funcs
1903 .destroy = nv50_pior_destroy,
1907 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1909 struct drm_device *dev = connector->dev;
1910 struct nouveau_drm *drm = nouveau_drm(dev);
1911 struct nv50_disp *disp = nv50_disp(dev);
1912 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1913 struct nvkm_i2c_bus *bus = NULL;
1914 struct nvkm_i2c_aux *aux = NULL;
1915 struct i2c_adapter *ddc;
1916 struct nouveau_encoder *nv_encoder;
1917 struct drm_encoder *encoder;
1920 switch (dcbe->type) {
1921 case DCB_OUTPUT_TMDS:
1922 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1923 ddc = bus ? &bus->i2c : NULL;
1924 type = DRM_MODE_ENCODER_TMDS;
1927 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1928 ddc = aux ? &aux->i2c : NULL;
1929 type = DRM_MODE_ENCODER_TMDS;
1935 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1938 nv_encoder->dcb = dcbe;
1939 nv_encoder->i2c = ddc;
1940 nv_encoder->aux = aux;
1942 encoder = to_drm_encoder(nv_encoder);
1943 encoder->possible_crtcs = dcbe->heads;
1944 encoder->possible_clones = 0;
1945 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1946 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1947 drm_encoder_helper_add(encoder, &nv50_pior_help);
1949 drm_connector_attach_encoder(connector, encoder);
1951 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1956 /******************************************************************************
1958 *****************************************************************************/
1961 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1963 struct nouveau_drm *drm = nouveau_drm(state->dev);
1964 struct nv50_disp *disp = nv50_disp(drm->dev);
1965 struct nv50_core *core = disp->core;
1966 struct nv50_mstm *mstm;
1967 struct drm_encoder *encoder;
1969 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1971 drm_for_each_encoder(encoder, drm->dev) {
1972 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1973 mstm = nouveau_encoder(encoder)->dp.mstm;
1974 if (mstm && mstm->modified)
1975 nv50_mstm_prepare(mstm);
1979 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1980 core->func->update(core, interlock, true);
1981 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1982 disp->core->chan.base.device))
1983 NV_ERROR(drm, "core notifier timeout\n");
1985 drm_for_each_encoder(encoder, drm->dev) {
1986 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1987 mstm = nouveau_encoder(encoder)->dp.mstm;
1988 if (mstm && mstm->modified)
1989 nv50_mstm_cleanup(mstm);
1995 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1997 struct drm_plane_state *new_plane_state;
1998 struct drm_plane *plane;
2001 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2002 struct nv50_wndw *wndw = nv50_wndw(plane);
2003 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2004 if (wndw->func->update)
2005 wndw->func->update(wndw, interlock);
2011 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2013 struct drm_device *dev = state->dev;
2014 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2015 struct drm_crtc *crtc;
2016 struct drm_plane_state *new_plane_state;
2017 struct drm_plane *plane;
2018 struct nouveau_drm *drm = nouveau_drm(dev);
2019 struct nv50_disp *disp = nv50_disp(dev);
2020 struct nv50_atom *atom = nv50_atom(state);
2021 struct nv50_core *core = disp->core;
2022 struct nv50_outp_atom *outp, *outt;
2023 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2025 bool flushed = false;
2027 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2028 nv50_crc_atomic_stop_reporting(state);
2029 drm_atomic_helper_wait_for_fences(dev, state, false);
2030 drm_atomic_helper_wait_for_dependencies(state);
2031 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2033 if (atom->lock_core)
2034 mutex_lock(&disp->mutex);
2036 /* Disable head(s). */
2037 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2038 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2039 struct nv50_head *head = nv50_head(crtc);
2041 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2042 asyh->clr.mask, asyh->set.mask);
2044 if (old_crtc_state->active && !new_crtc_state->active) {
2045 pm_runtime_put_noidle(dev->dev);
2046 drm_crtc_vblank_off(crtc);
2049 if (asyh->clr.mask) {
2050 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2051 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2055 /* Disable plane(s). */
2056 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2057 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2058 struct nv50_wndw *wndw = nv50_wndw(plane);
2060 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2061 asyw->clr.mask, asyw->set.mask);
2062 if (!asyw->clr.mask)
2065 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2068 /* Disable output path(s). */
2069 list_for_each_entry(outp, &atom->outp, head) {
2070 const struct drm_encoder_helper_funcs *help;
2071 struct drm_encoder *encoder;
2073 encoder = outp->encoder;
2074 help = encoder->helper_private;
2076 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2077 outp->clr.mask, outp->set.mask);
2079 if (outp->clr.mask) {
2080 help->disable(encoder);
2081 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2082 if (outp->flush_disable) {
2083 nv50_disp_atomic_commit_wndw(state, interlock);
2084 nv50_disp_atomic_commit_core(state, interlock);
2085 memset(interlock, 0x00, sizeof(interlock));
2092 /* Flush disable. */
2093 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2094 if (atom->flush_disable) {
2095 nv50_disp_atomic_commit_wndw(state, interlock);
2096 nv50_disp_atomic_commit_core(state, interlock);
2097 memset(interlock, 0x00, sizeof(interlock));
2104 nv50_crc_atomic_release_notifier_contexts(state);
2105 nv50_crc_atomic_init_notifier_contexts(state);
2107 /* Update output path(s). */
2108 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2109 const struct drm_encoder_helper_funcs *help;
2110 struct drm_encoder *encoder;
2112 encoder = outp->encoder;
2113 help = encoder->helper_private;
2115 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2116 outp->set.mask, outp->clr.mask);
2118 if (outp->set.mask) {
2119 help->enable(encoder);
2120 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2123 list_del(&outp->head);
2127 /* Update head(s). */
2128 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2129 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2130 struct nv50_head *head = nv50_head(crtc);
2132 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2133 asyh->set.mask, asyh->clr.mask);
2135 if (asyh->set.mask) {
2136 nv50_head_flush_set(head, asyh);
2137 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2140 if (new_crtc_state->active) {
2141 if (!old_crtc_state->active) {
2142 drm_crtc_vblank_on(crtc);
2143 pm_runtime_get_noresume(dev->dev);
2145 if (new_crtc_state->event)
2146 drm_crtc_vblank_get(crtc);
2150 /* Update window->head assignment.
2152 * This has to happen in an update that's not interlocked with
2153 * any window channels to avoid hitting HW error checks.
2155 *TODO: Proper handling of window ownership (Turing apparently
2156 * supports non-fixed mappings).
2158 if (core->assign_windows) {
2159 core->func->wndw.owner(core);
2160 nv50_disp_atomic_commit_core(state, interlock);
2161 core->assign_windows = false;
2162 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2165 /* Update plane(s). */
2166 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2167 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2168 struct nv50_wndw *wndw = nv50_wndw(plane);
2170 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2171 asyw->set.mask, asyw->clr.mask);
2172 if ( !asyw->set.mask &&
2173 (!asyw->clr.mask || atom->flush_disable))
2176 nv50_wndw_flush_set(wndw, interlock, asyw);
2180 nv50_disp_atomic_commit_wndw(state, interlock);
2182 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2183 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2184 interlock[NV50_DISP_INTERLOCK_OVLY] ||
2185 interlock[NV50_DISP_INTERLOCK_WNDW] ||
2186 !atom->state.legacy_cursor_update)
2187 nv50_disp_atomic_commit_core(state, interlock);
2189 disp->core->func->update(disp->core, interlock, false);
2192 if (atom->lock_core)
2193 mutex_unlock(&disp->mutex);
2195 /* Wait for HW to signal completion. */
2196 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2197 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2198 struct nv50_wndw *wndw = nv50_wndw(plane);
2199 int ret = nv50_wndw_wait_armed(wndw, asyw);
2201 NV_ERROR(drm, "%s: timeout\n", plane->name);
2204 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2205 if (new_crtc_state->event) {
2206 unsigned long flags;
2207 /* Get correct count/ts if racing with vblank irq */
2208 if (new_crtc_state->active)
2209 drm_crtc_accurate_vblank_count(crtc);
2210 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2211 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2212 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2214 new_crtc_state->event = NULL;
2215 if (new_crtc_state->active)
2216 drm_crtc_vblank_put(crtc);
2220 nv50_crc_atomic_start_reporting(state);
2222 nv50_crc_atomic_release_notifier_contexts(state);
2223 drm_atomic_helper_commit_hw_done(state);
2224 drm_atomic_helper_cleanup_planes(dev, state);
2225 drm_atomic_helper_commit_cleanup_done(state);
2226 drm_atomic_state_put(state);
2228 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2229 pm_runtime_mark_last_busy(dev->dev);
2230 pm_runtime_put_autosuspend(dev->dev);
2234 nv50_disp_atomic_commit_work(struct work_struct *work)
2236 struct drm_atomic_state *state =
2237 container_of(work, typeof(*state), commit_work);
2238 nv50_disp_atomic_commit_tail(state);
2242 nv50_disp_atomic_commit(struct drm_device *dev,
2243 struct drm_atomic_state *state, bool nonblock)
2245 struct drm_plane_state *new_plane_state;
2246 struct drm_plane *plane;
2249 ret = pm_runtime_get_sync(dev->dev);
2250 if (ret < 0 && ret != -EACCES) {
2251 pm_runtime_put_autosuspend(dev->dev);
2255 ret = drm_atomic_helper_setup_commit(state, nonblock);
2259 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2261 ret = drm_atomic_helper_prepare_planes(dev, state);
2266 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2271 ret = drm_atomic_helper_swap_state(state, true);
2275 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2276 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2277 struct nv50_wndw *wndw = nv50_wndw(plane);
2279 if (asyw->set.image)
2280 nv50_wndw_ntfy_enable(wndw, asyw);
2283 drm_atomic_state_get(state);
2286 * Grab another RPM ref for the commit tail, which will release the
2287 * ref when it's finished
2289 pm_runtime_get_noresume(dev->dev);
2292 queue_work(system_unbound_wq, &state->commit_work);
2294 nv50_disp_atomic_commit_tail(state);
2298 drm_atomic_helper_cleanup_planes(dev, state);
2300 pm_runtime_put_autosuspend(dev->dev);
2304 static struct nv50_outp_atom *
2305 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2307 struct nv50_outp_atom *outp;
2309 list_for_each_entry(outp, &atom->outp, head) {
2310 if (outp->encoder == encoder)
2314 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2316 return ERR_PTR(-ENOMEM);
2318 list_add(&outp->head, &atom->outp);
2319 outp->encoder = encoder;
2324 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2325 struct drm_connector_state *old_connector_state)
2327 struct drm_encoder *encoder = old_connector_state->best_encoder;
2328 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2329 struct drm_crtc *crtc;
2330 struct nv50_outp_atom *outp;
2332 if (!(crtc = old_connector_state->crtc))
2335 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2336 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2337 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2338 outp = nv50_disp_outp_atomic_add(atom, encoder);
2340 return PTR_ERR(outp);
2342 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2343 outp->flush_disable = true;
2344 atom->flush_disable = true;
2346 outp->clr.ctrl = true;
2347 atom->lock_core = true;
2354 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2355 struct drm_connector_state *connector_state)
2357 struct drm_encoder *encoder = connector_state->best_encoder;
2358 struct drm_crtc_state *new_crtc_state;
2359 struct drm_crtc *crtc;
2360 struct nv50_outp_atom *outp;
2362 if (!(crtc = connector_state->crtc))
2365 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2366 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2367 outp = nv50_disp_outp_atomic_add(atom, encoder);
2369 return PTR_ERR(outp);
2371 outp->set.ctrl = true;
2372 atom->lock_core = true;
2379 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2381 struct nv50_atom *atom = nv50_atom(state);
2382 struct nv50_core *core = nv50_disp(dev)->core;
2383 struct drm_connector_state *old_connector_state, *new_connector_state;
2384 struct drm_connector *connector;
2385 struct drm_crtc_state *new_crtc_state;
2386 struct drm_crtc *crtc;
2387 struct nv50_head *head;
2388 struct nv50_head_atom *asyh;
2391 if (core->assign_windows && core->func->head->static_wndw_map) {
2392 drm_for_each_crtc(crtc, dev) {
2393 new_crtc_state = drm_atomic_get_crtc_state(state,
2395 if (IS_ERR(new_crtc_state))
2396 return PTR_ERR(new_crtc_state);
2398 head = nv50_head(crtc);
2399 asyh = nv50_head_atom(new_crtc_state);
2400 core->func->head->static_wndw_map(head, asyh);
2404 /* We need to handle colour management on a per-plane basis. */
2405 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2406 if (new_crtc_state->color_mgmt_changed) {
2407 ret = drm_atomic_add_affected_planes(state, crtc);
2413 ret = drm_atomic_helper_check(dev, state);
2417 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2418 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2422 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2427 ret = drm_dp_mst_atomic_check(state);
2431 nv50_crc_atomic_check_outp(atom);
2437 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2439 struct nv50_atom *atom = nv50_atom(state);
2440 struct nv50_outp_atom *outp, *outt;
2442 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2443 list_del(&outp->head);
2447 drm_atomic_state_default_clear(state);
2451 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2453 struct nv50_atom *atom = nv50_atom(state);
2454 drm_atomic_state_default_release(&atom->state);
2458 static struct drm_atomic_state *
2459 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2461 struct nv50_atom *atom;
2462 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2463 drm_atomic_state_init(dev, &atom->state) < 0) {
2467 INIT_LIST_HEAD(&atom->outp);
2468 return &atom->state;
2471 static const struct drm_mode_config_funcs
2473 .fb_create = nouveau_user_framebuffer_create,
2474 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2475 .atomic_check = nv50_disp_atomic_check,
2476 .atomic_commit = nv50_disp_atomic_commit,
2477 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2478 .atomic_state_clear = nv50_disp_atomic_state_clear,
2479 .atomic_state_free = nv50_disp_atomic_state_free,
2482 /******************************************************************************
2484 *****************************************************************************/
2487 nv50_display_fini(struct drm_device *dev, bool suspend)
2489 struct nouveau_encoder *nv_encoder;
2490 struct drm_encoder *encoder;
2491 struct drm_plane *plane;
2493 drm_for_each_plane(plane, dev) {
2494 struct nv50_wndw *wndw = nv50_wndw(plane);
2495 if (plane->funcs != &nv50_wndw)
2497 nv50_wndw_fini(wndw);
2500 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2501 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2502 nv_encoder = nouveau_encoder(encoder);
2503 nv50_mstm_fini(nv_encoder->dp.mstm);
2509 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2511 struct nv50_core *core = nv50_disp(dev)->core;
2512 struct drm_encoder *encoder;
2513 struct drm_plane *plane;
2515 if (resume || runtime)
2516 core->func->init(core);
2518 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2519 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2520 struct nouveau_encoder *nv_encoder =
2521 nouveau_encoder(encoder);
2522 nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2526 drm_for_each_plane(plane, dev) {
2527 struct nv50_wndw *wndw = nv50_wndw(plane);
2528 if (plane->funcs != &nv50_wndw)
2530 nv50_wndw_init(wndw);
2537 nv50_display_destroy(struct drm_device *dev)
2539 struct nv50_disp *disp = nv50_disp(dev);
2541 nv50_audio_component_fini(nouveau_drm(dev));
2543 nvif_object_unmap(&disp->caps);
2544 nvif_object_dtor(&disp->caps);
2545 nv50_core_del(&disp->core);
2547 nouveau_bo_unmap(disp->sync);
2549 nouveau_bo_unpin(disp->sync);
2550 nouveau_bo_ref(NULL, &disp->sync);
2552 nouveau_display(dev)->priv = NULL;
2557 nv50_display_create(struct drm_device *dev)
2559 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2560 struct nouveau_drm *drm = nouveau_drm(dev);
2561 struct dcb_table *dcb = &drm->vbios.dcb;
2562 struct drm_connector *connector, *tmp;
2563 struct nv50_disp *disp;
2564 struct dcb_output *dcbe;
2566 bool has_mst = nv50_has_mst(drm);
2568 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2572 mutex_init(&disp->mutex);
2574 nouveau_display(dev)->priv = disp;
2575 nouveau_display(dev)->dtor = nv50_display_destroy;
2576 nouveau_display(dev)->init = nv50_display_init;
2577 nouveau_display(dev)->fini = nv50_display_fini;
2578 disp->disp = &nouveau_display(dev)->disp;
2579 dev->mode_config.funcs = &nv50_disp_func;
2580 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2581 dev->mode_config.normalize_zpos = true;
2583 /* small shared memory area we use for notifiers and semaphores */
2584 ret = nouveau_bo_new(&drm->client, 4096, 0x1000,
2585 NOUVEAU_GEM_DOMAIN_VRAM,
2586 0, 0x0000, NULL, NULL, &disp->sync);
2588 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true);
2590 ret = nouveau_bo_map(disp->sync);
2592 nouveau_bo_unpin(disp->sync);
2595 nouveau_bo_ref(NULL, &disp->sync);
2601 /* allocate master evo channel */
2602 ret = nv50_core_new(drm, &disp->core);
2606 disp->core->func->init(disp->core);
2607 if (disp->core->func->caps_init) {
2608 ret = disp->core->func->caps_init(drm, disp);
2613 /* Assign the correct format modifiers */
2614 if (disp->disp->object.oclass >= TU102_DISP)
2615 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2617 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2618 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2620 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2622 /* create crtc objects to represent the hw heads */
2623 if (disp->disp->object.oclass >= GV100_DISP)
2624 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2626 if (disp->disp->object.oclass >= GF110_DISP)
2627 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2631 for (i = 0; i < fls(crtcs); i++) {
2632 struct nv50_head *head;
2634 if (!(crtcs & (1 << i)))
2637 head = nv50_head_create(dev, i);
2639 ret = PTR_ERR(head);
2644 head->msto = nv50_msto_new(dev, head, i);
2645 if (IS_ERR(head->msto)) {
2646 ret = PTR_ERR(head->msto);
2652 * FIXME: This is a hack to workaround the following
2655 * https://gitlab.gnome.org/GNOME/mutter/issues/759
2656 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2658 * Once these issues are closed, this should be
2661 head->msto->encoder.possible_crtcs = crtcs;
2665 /* create encoder/connector objects based on VBIOS DCB table */
2666 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2667 connector = nouveau_connector_create(dev, dcbe);
2668 if (IS_ERR(connector))
2671 if (dcbe->location == DCB_LOC_ON_CHIP) {
2672 switch (dcbe->type) {
2673 case DCB_OUTPUT_TMDS:
2674 case DCB_OUTPUT_LVDS:
2676 ret = nv50_sor_create(connector, dcbe);
2678 case DCB_OUTPUT_ANALOG:
2679 ret = nv50_dac_create(connector, dcbe);
2686 ret = nv50_pior_create(connector, dcbe);
2690 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2691 dcbe->location, dcbe->type,
2692 ffs(dcbe->or) - 1, ret);
2697 /* cull any connectors we created that don't have an encoder */
2698 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2699 if (connector->possible_encoders)
2702 NV_WARN(drm, "%s has no encoders, removing\n",
2704 connector->funcs->destroy(connector);
2707 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2708 dev->vblank_disable_immediate = true;
2710 nv50_audio_component_init(drm);
2714 nv50_display_destroy(dev);
2718 /******************************************************************************
2720 *****************************************************************************/
2722 /****************************************************************
2723 * Log2(block height) ----------------------------+ *
2724 * Page Kind ----------------------------------+ | *
2725 * Gob Height/Page Kind Generation ------+ | | *
2726 * Sector layout -------+ | | | *
2727 * Compression ------+ | | | | */
2728 const u64 disp50xx_modifiers[] = { /* | | | | | */
2729 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2730 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2731 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2732 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2733 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2734 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2735 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2736 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2737 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2738 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2739 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2740 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2741 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2742 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2743 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2744 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2745 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2746 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2747 DRM_FORMAT_MOD_LINEAR,
2748 DRM_FORMAT_MOD_INVALID
2751 /****************************************************************
2752 * Log2(block height) ----------------------------+ *
2753 * Page Kind ----------------------------------+ | *
2754 * Gob Height/Page Kind Generation ------+ | | *
2755 * Sector layout -------+ | | | *
2756 * Compression ------+ | | | | */
2757 const u64 disp90xx_modifiers[] = { /* | | | | | */
2758 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2759 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2760 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2761 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2762 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2763 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2764 DRM_FORMAT_MOD_LINEAR,
2765 DRM_FORMAT_MOD_INVALID