2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/dma-mapping.h>
31 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_plane_helper.h>
39 #include <drm/drm_edid.h>
41 #include <nvif/class.h>
42 #include <nvif/cl0002.h>
43 #include <nvif/cl5070.h>
44 #include <nvif/cl507d.h>
45 #include <nvif/event.h>
47 #include "nouveau_drv.h"
48 #include "nouveau_dma.h"
49 #include "nouveau_gem.h"
50 #include "nouveau_connector.h"
51 #include "nouveau_encoder.h"
52 #include "nouveau_fence.h"
53 #include "nouveau_fbcon.h"
55 #include <subdev/bios/dp.h>
57 /******************************************************************************
59 *****************************************************************************/
61 struct nv50_outp_atom {
62 struct list_head head;
64 struct drm_encoder *encoder;
67 union nv50_outp_atom_mask {
75 /******************************************************************************
77 *****************************************************************************/
80 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
81 const s32 *oclass, u8 head, void *data, u32 size,
82 struct nv50_chan *chan)
84 struct nvif_sclass *sclass;
87 chan->device = device;
89 ret = n = nvif_object_sclass_get(disp, &sclass);
94 for (i = 0; i < n; i++) {
95 if (sclass[i].oclass == oclass[0]) {
96 ret = nvif_object_init(disp, 0, oclass[0],
97 data, size, &chan->user);
99 nvif_object_map(&chan->user, NULL, 0);
100 nvif_object_sclass_put(&sclass);
107 nvif_object_sclass_put(&sclass);
112 nv50_chan_destroy(struct nv50_chan *chan)
114 nvif_object_fini(&chan->user);
117 /******************************************************************************
119 *****************************************************************************/
122 nv50_dmac_destroy(struct nv50_dmac *dmac)
124 nvif_object_fini(&dmac->vram);
125 nvif_object_fini(&dmac->sync);
127 nv50_chan_destroy(&dmac->base);
129 nvif_mem_fini(&dmac->push);
133 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
134 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
135 struct nv50_dmac *dmac)
137 struct nouveau_cli *cli = (void *)device->object.client;
138 struct nv50_disp_core_channel_dma_v0 *args = data;
139 u8 type = NVIF_MEM_COHERENT;
142 mutex_init(&dmac->lock);
144 /* Pascal added support for 47-bit physical addresses, but some
145 * parts of EVO still only accept 40-bit PAs.
147 * To avoid issues on systems with large amounts of RAM, and on
148 * systems where an IOMMU maps pages at a high address, we need
149 * to allocate push buffers in VRAM instead.
151 * This appears to match NVIDIA's behaviour on Pascal.
153 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
154 type |= NVIF_MEM_VRAM;
156 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
160 dmac->ptr = dmac->push.object.map.ptr;
162 args->pushbuf = nvif_handle(&dmac->push.object);
164 ret = nv50_chan_create(device, disp, oclass, head, data, size,
172 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
173 &(struct nv_dma_v0) {
174 .target = NV_DMA_V0_TARGET_VRAM,
175 .access = NV_DMA_V0_ACCESS_RDWR,
176 .start = syncbuf + 0x0000,
177 .limit = syncbuf + 0x0fff,
178 }, sizeof(struct nv_dma_v0),
183 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
184 &(struct nv_dma_v0) {
185 .target = NV_DMA_V0_TARGET_VRAM,
186 .access = NV_DMA_V0_ACCESS_RDWR,
188 .limit = device->info.ram_user - 1,
189 }, sizeof(struct nv_dma_v0),
197 /******************************************************************************
198 * EVO channel helpers
199 *****************************************************************************/
201 evo_wait(struct nv50_dmac *evoc, int nr)
203 struct nv50_dmac *dmac = evoc;
204 struct nvif_device *device = dmac->base.device;
205 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
207 mutex_lock(&dmac->lock);
208 if (put + nr >= (PAGE_SIZE / 4) - 8) {
209 dmac->ptr[put] = 0x20000000;
211 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
212 if (nvif_msec(device, 2000,
213 if (!nvif_rd32(&dmac->base.user, 0x0004))
216 mutex_unlock(&dmac->lock);
217 pr_err("nouveau: evo channel stalled\n");
224 return dmac->ptr + put;
228 evo_kick(u32 *push, struct nv50_dmac *evoc)
230 struct nv50_dmac *dmac = evoc;
232 /* Push buffer fetches are not coherent with BAR1, we need to ensure
233 * writes have been flushed right through to VRAM before writing PUT.
235 if (dmac->push.type & NVIF_MEM_VRAM) {
236 struct nvif_device *device = dmac->base.device;
237 nvif_wr32(&device->object, 0x070000, 0x00000001);
238 nvif_msec(device, 2000,
239 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
244 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
245 mutex_unlock(&dmac->lock);
248 /******************************************************************************
249 * Output path helpers
250 *****************************************************************************/
252 nv50_outp_release(struct nouveau_encoder *nv_encoder)
254 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
256 struct nv50_disp_mthd_v1 base;
259 .base.method = NV50_DISP_MTHD_V1_RELEASE,
260 .base.hasht = nv_encoder->dcb->hasht,
261 .base.hashm = nv_encoder->dcb->hashm,
264 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
266 nv_encoder->link = 0;
270 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
272 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
273 struct nv50_disp *disp = nv50_disp(drm->dev);
275 struct nv50_disp_mthd_v1 base;
276 struct nv50_disp_acquire_v0 info;
279 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
280 .base.hasht = nv_encoder->dcb->hasht,
281 .base.hashm = nv_encoder->dcb->hashm,
285 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
287 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
291 nv_encoder->or = args.info.or;
292 nv_encoder->link = args.info.link;
297 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
298 struct drm_crtc_state *crtc_state,
299 struct drm_connector_state *conn_state,
300 struct drm_display_mode *native_mode)
302 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
303 struct drm_display_mode *mode = &crtc_state->mode;
304 struct drm_connector *connector = conn_state->connector;
305 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
306 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
308 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
309 asyc->scaler.full = false;
313 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
314 switch (connector->connector_type) {
315 case DRM_MODE_CONNECTOR_LVDS:
316 case DRM_MODE_CONNECTOR_eDP:
317 /* Force use of scaler for non-EDID modes. */
318 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
321 asyc->scaler.full = true;
330 if (!drm_mode_equal(adjusted_mode, mode)) {
331 drm_mode_copy(adjusted_mode, mode);
332 crtc_state->mode_changed = true;
339 nv50_outp_atomic_check(struct drm_encoder *encoder,
340 struct drm_crtc_state *crtc_state,
341 struct drm_connector_state *conn_state)
343 struct nouveau_connector *nv_connector =
344 nouveau_connector(conn_state->connector);
345 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
346 nv_connector->native_mode);
349 /******************************************************************************
351 *****************************************************************************/
353 nv50_dac_disable(struct drm_encoder *encoder)
355 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
356 struct nv50_core *core = nv50_disp(encoder->dev)->core;
357 if (nv_encoder->crtc)
358 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
359 nv_encoder->crtc = NULL;
360 nv50_outp_release(nv_encoder);
364 nv50_dac_enable(struct drm_encoder *encoder)
366 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
367 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
368 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
369 struct nv50_core *core = nv50_disp(encoder->dev)->core;
371 nv50_outp_acquire(nv_encoder);
373 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
376 nv_encoder->crtc = encoder->crtc;
379 static enum drm_connector_status
380 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
382 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
383 struct nv50_disp *disp = nv50_disp(encoder->dev);
385 struct nv50_disp_mthd_v1 base;
386 struct nv50_disp_dac_load_v0 load;
389 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
390 .base.hasht = nv_encoder->dcb->hasht,
391 .base.hashm = nv_encoder->dcb->hashm,
395 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
396 if (args.load.data == 0)
397 args.load.data = 340;
399 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
400 if (ret || !args.load.load)
401 return connector_status_disconnected;
403 return connector_status_connected;
406 static const struct drm_encoder_helper_funcs
408 .atomic_check = nv50_outp_atomic_check,
409 .enable = nv50_dac_enable,
410 .disable = nv50_dac_disable,
411 .detect = nv50_dac_detect
415 nv50_dac_destroy(struct drm_encoder *encoder)
417 drm_encoder_cleanup(encoder);
421 static const struct drm_encoder_funcs
423 .destroy = nv50_dac_destroy,
427 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
429 struct nouveau_drm *drm = nouveau_drm(connector->dev);
430 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
431 struct nvkm_i2c_bus *bus;
432 struct nouveau_encoder *nv_encoder;
433 struct drm_encoder *encoder;
434 int type = DRM_MODE_ENCODER_DAC;
436 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
439 nv_encoder->dcb = dcbe;
441 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
443 nv_encoder->i2c = &bus->i2c;
445 encoder = to_drm_encoder(nv_encoder);
446 encoder->possible_crtcs = dcbe->heads;
447 encoder->possible_clones = 0;
448 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
449 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
450 drm_encoder_helper_add(encoder, &nv50_dac_help);
452 drm_connector_attach_encoder(connector, encoder);
456 /******************************************************************************
458 *****************************************************************************/
460 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
462 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
463 struct nv50_disp *disp = nv50_disp(encoder->dev);
465 struct nv50_disp_mthd_v1 base;
466 struct nv50_disp_sor_hda_eld_v0 eld;
469 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
470 .base.hasht = nv_encoder->dcb->hasht,
471 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
472 (0x0100 << nv_crtc->index),
475 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
479 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
481 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
482 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
483 struct nouveau_connector *nv_connector;
484 struct nv50_disp *disp = nv50_disp(encoder->dev);
487 struct nv50_disp_mthd_v1 mthd;
488 struct nv50_disp_sor_hda_eld_v0 eld;
490 u8 data[sizeof(nv_connector->base.eld)];
492 .base.mthd.version = 1,
493 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
494 .base.mthd.hasht = nv_encoder->dcb->hasht,
495 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
496 (0x0100 << nv_crtc->index),
499 nv_connector = nouveau_encoder_connector_get(nv_encoder);
500 if (!drm_detect_monitor_audio(nv_connector->edid))
503 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
505 nvif_mthd(&disp->disp->object, 0, &args,
506 sizeof(args.base) + drm_eld_size(args.data));
509 /******************************************************************************
511 *****************************************************************************/
513 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
515 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
516 struct nv50_disp *disp = nv50_disp(encoder->dev);
518 struct nv50_disp_mthd_v1 base;
519 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
522 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
523 .base.hasht = nv_encoder->dcb->hasht,
524 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
525 (0x0100 << nv_crtc->index),
528 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
532 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
534 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
535 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
536 struct nv50_disp *disp = nv50_disp(encoder->dev);
538 struct nv50_disp_mthd_v1 base;
539 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
540 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
543 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
544 .base.hasht = nv_encoder->dcb->hasht,
545 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
546 (0x0100 << nv_crtc->index),
548 .pwr.rekey = 56, /* binary driver, and tegra, constant */
550 struct nouveau_connector *nv_connector;
552 union hdmi_infoframe avi_frame;
553 union hdmi_infoframe vendor_frame;
557 nv_connector = nouveau_encoder_connector_get(nv_encoder);
558 if (!drm_detect_hdmi_monitor(nv_connector->edid))
561 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
564 /* We have an AVI InfoFrame, populate it to the display */
565 args.pwr.avi_infoframe_length
566 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
569 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
570 &nv_connector->base, mode);
572 /* We have a Vendor InfoFrame, populate it to the display */
573 args.pwr.vendor_infoframe_length
574 = hdmi_infoframe_pack(&vendor_frame,
576 + args.pwr.avi_infoframe_length,
580 max_ac_packet = mode->htotal - mode->hdisplay;
581 max_ac_packet -= args.pwr.rekey;
582 max_ac_packet -= 18; /* constant from tegra */
583 args.pwr.max_ac_packet = max_ac_packet / 32;
585 size = sizeof(args.base)
587 + args.pwr.avi_infoframe_length
588 + args.pwr.vendor_infoframe_length;
589 nvif_mthd(&disp->disp->object, 0, &args, size);
590 nv50_audio_enable(encoder, mode);
593 /******************************************************************************
595 *****************************************************************************/
596 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
597 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
598 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
601 struct nouveau_encoder *outp;
603 struct drm_dp_mst_topology_mgr mgr;
604 struct nv50_msto *msto[4];
612 struct nv50_mstm *mstm;
613 struct drm_dp_mst_port *port;
614 struct drm_connector connector;
616 struct drm_display_mode *native;
623 struct drm_encoder encoder;
625 struct nv50_head *head;
626 struct nv50_mstc *mstc;
630 static struct drm_dp_payload *
631 nv50_msto_payload(struct nv50_msto *msto)
633 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
634 struct nv50_mstc *mstc = msto->mstc;
635 struct nv50_mstm *mstm = mstc->mstm;
636 int vcpi = mstc->port->vcpi.vcpi, i;
638 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
639 for (i = 0; i < mstm->mgr.max_payloads; i++) {
640 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
641 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
642 mstm->outp->base.base.name, i, payload->vcpi,
643 payload->start_slot, payload->num_slots);
646 for (i = 0; i < mstm->mgr.max_payloads; i++) {
647 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
648 if (payload->vcpi == vcpi)
656 nv50_msto_cleanup(struct nv50_msto *msto)
658 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
659 struct nv50_mstc *mstc = msto->mstc;
660 struct nv50_mstm *mstm = mstc->mstm;
662 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
663 if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
664 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
665 if (msto->disabled) {
668 msto->disabled = false;
673 nv50_msto_prepare(struct nv50_msto *msto)
675 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
676 struct nv50_mstc *mstc = msto->mstc;
677 struct nv50_mstm *mstm = mstc->mstm;
679 struct nv50_disp_mthd_v1 base;
680 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
683 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
684 .base.hasht = mstm->outp->dcb->hasht,
685 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
686 (0x0100 << msto->head->base.index),
689 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
690 if (mstc->port && mstc->port->vcpi.vcpi > 0) {
691 struct drm_dp_payload *payload = nv50_msto_payload(msto);
693 args.vcpi.start_slot = payload->start_slot;
694 args.vcpi.num_slots = payload->num_slots;
695 args.vcpi.pbn = mstc->port->vcpi.pbn;
696 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
700 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
701 msto->encoder.name, msto->head->base.base.name,
702 args.vcpi.start_slot, args.vcpi.num_slots,
703 args.vcpi.pbn, args.vcpi.aligned_pbn);
704 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
708 nv50_msto_atomic_check(struct drm_encoder *encoder,
709 struct drm_crtc_state *crtc_state,
710 struct drm_connector_state *conn_state)
712 struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
713 struct nv50_mstm *mstm = mstc->mstm;
714 int bpp = conn_state->connector->display_info.bpc * 3;
717 mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
719 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
723 return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
728 nv50_msto_enable(struct drm_encoder *encoder)
730 struct nv50_head *head = nv50_head(encoder->crtc);
731 struct nv50_msto *msto = nv50_msto(encoder);
732 struct nv50_mstc *mstc = NULL;
733 struct nv50_mstm *mstm = NULL;
734 struct drm_connector *connector;
735 struct drm_connector_list_iter conn_iter;
740 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
741 drm_for_each_connector_iter(connector, &conn_iter) {
742 if (connector->state->best_encoder == &msto->encoder) {
743 mstc = nv50_mstc(connector);
748 drm_connector_list_iter_end(&conn_iter);
753 slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
754 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
758 nv50_outp_acquire(mstm->outp);
760 if (mstm->outp->link & 1)
765 switch (mstc->connector.display_info.bpc) {
766 case 6: depth = 0x2; break;
767 case 8: depth = 0x5; break;
769 default: depth = 0x6; break;
772 mstm->outp->update(mstm->outp, head->base.index,
773 nv50_head_atom(head->base.base.state), proto, depth);
777 mstm->modified = true;
781 nv50_msto_disable(struct drm_encoder *encoder)
783 struct nv50_msto *msto = nv50_msto(encoder);
784 struct nv50_mstc *mstc = msto->mstc;
785 struct nv50_mstm *mstm = mstc->mstm;
788 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
790 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
791 mstm->modified = true;
793 mstm->disabled = true;
794 msto->disabled = true;
797 static const struct drm_encoder_helper_funcs
799 .disable = nv50_msto_disable,
800 .enable = nv50_msto_enable,
801 .atomic_check = nv50_msto_atomic_check,
805 nv50_msto_destroy(struct drm_encoder *encoder)
807 struct nv50_msto *msto = nv50_msto(encoder);
808 drm_encoder_cleanup(&msto->encoder);
812 static const struct drm_encoder_funcs
814 .destroy = nv50_msto_destroy,
818 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
819 struct nv50_msto **pmsto)
821 struct nv50_msto *msto;
824 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
827 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
828 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
835 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
836 msto->encoder.possible_crtcs = heads;
840 static struct drm_encoder *
841 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
842 struct drm_connector_state *connector_state)
844 struct nv50_head *head = nv50_head(connector_state->crtc);
845 struct nv50_mstc *mstc = nv50_mstc(connector);
847 struct nv50_mstm *mstm = mstc->mstm;
848 return &mstm->msto[head->base.index]->encoder;
853 static struct drm_encoder *
854 nv50_mstc_best_encoder(struct drm_connector *connector)
856 struct nv50_mstc *mstc = nv50_mstc(connector);
858 struct nv50_mstm *mstm = mstc->mstm;
859 return &mstm->msto[0]->encoder;
864 static enum drm_mode_status
865 nv50_mstc_mode_valid(struct drm_connector *connector,
866 struct drm_display_mode *mode)
872 nv50_mstc_get_modes(struct drm_connector *connector)
874 struct nv50_mstc *mstc = nv50_mstc(connector);
877 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
878 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
880 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
882 if (!mstc->connector.display_info.bpc)
883 mstc->connector.display_info.bpc = 8;
886 drm_mode_destroy(mstc->connector.dev, mstc->native);
887 mstc->native = nouveau_conn_native_mode(&mstc->connector);
891 static const struct drm_connector_helper_funcs
893 .get_modes = nv50_mstc_get_modes,
894 .mode_valid = nv50_mstc_mode_valid,
895 .best_encoder = nv50_mstc_best_encoder,
896 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
899 static enum drm_connector_status
900 nv50_mstc_detect(struct drm_connector *connector, bool force)
902 struct nv50_mstc *mstc = nv50_mstc(connector);
903 enum drm_connector_status conn_status;
907 return connector_status_disconnected;
909 ret = pm_runtime_get_sync(connector->dev->dev);
910 if (ret < 0 && ret != -EACCES)
911 return connector_status_disconnected;
913 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
916 pm_runtime_mark_last_busy(connector->dev->dev);
917 pm_runtime_put_autosuspend(connector->dev->dev);
922 nv50_mstc_destroy(struct drm_connector *connector)
924 struct nv50_mstc *mstc = nv50_mstc(connector);
925 drm_connector_cleanup(&mstc->connector);
929 static const struct drm_connector_funcs
931 .reset = nouveau_conn_reset,
932 .detect = nv50_mstc_detect,
933 .fill_modes = drm_helper_probe_single_connector_modes,
934 .destroy = nv50_mstc_destroy,
935 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
936 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
937 .atomic_set_property = nouveau_conn_atomic_set_property,
938 .atomic_get_property = nouveau_conn_atomic_get_property,
942 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
943 const char *path, struct nv50_mstc **pmstc)
945 struct drm_device *dev = mstm->outp->base.base.dev;
946 struct nv50_mstc *mstc;
949 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
954 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
955 DRM_MODE_CONNECTOR_DisplayPort);
962 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
964 mstc->connector.funcs->reset(&mstc->connector);
965 nouveau_conn_attach_properties(&mstc->connector);
967 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
968 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
970 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
971 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
972 drm_connector_set_path_property(&mstc->connector, path);
977 nv50_mstm_cleanup(struct nv50_mstm *mstm)
979 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
980 struct drm_encoder *encoder;
983 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
984 ret = drm_dp_check_act_status(&mstm->mgr);
986 ret = drm_dp_update_payload_part2(&mstm->mgr);
988 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
989 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
990 struct nv50_msto *msto = nv50_msto(encoder);
991 struct nv50_mstc *mstc = msto->mstc;
992 if (mstc && mstc->mstm == mstm)
993 nv50_msto_cleanup(msto);
997 mstm->modified = false;
1001 nv50_mstm_prepare(struct nv50_mstm *mstm)
1003 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1004 struct drm_encoder *encoder;
1007 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1008 ret = drm_dp_update_payload_part1(&mstm->mgr);
1010 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1011 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1012 struct nv50_msto *msto = nv50_msto(encoder);
1013 struct nv50_mstc *mstc = msto->mstc;
1014 if (mstc && mstc->mstm == mstm)
1015 nv50_msto_prepare(msto);
1019 if (mstm->disabled) {
1021 nv50_outp_release(mstm->outp);
1022 mstm->disabled = false;
1027 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
1029 struct nv50_mstm *mstm = nv50_mstm(mgr);
1030 drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
1034 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1035 struct drm_connector *connector)
1037 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1038 struct nv50_mstc *mstc = nv50_mstc(connector);
1040 drm_connector_unregister(&mstc->connector);
1042 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1044 drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1046 drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1048 drm_connector_put(&mstc->connector);
1052 nv50_mstm_register_connector(struct drm_connector *connector)
1054 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1056 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1058 drm_connector_register(connector);
1061 static struct drm_connector *
1062 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1063 struct drm_dp_mst_port *port, const char *path)
1065 struct nv50_mstm *mstm = nv50_mstm(mgr);
1066 struct nv50_mstc *mstc;
1069 ret = nv50_mstc_new(mstm, port, path, &mstc);
1072 mstc->connector.funcs->destroy(&mstc->connector);
1076 return &mstc->connector;
1079 static const struct drm_dp_mst_topology_cbs
1081 .add_connector = nv50_mstm_add_connector,
1082 .register_connector = nv50_mstm_register_connector,
1083 .destroy_connector = nv50_mstm_destroy_connector,
1084 .hotplug = nv50_mstm_hotplug,
1088 nv50_mstm_service(struct nv50_mstm *mstm)
1090 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1091 bool handled = true;
1099 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1101 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1105 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1109 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1114 nv50_mstm_remove(struct nv50_mstm *mstm)
1117 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1121 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1123 struct nouveau_encoder *outp = mstm->outp;
1125 struct nv50_disp_mthd_v1 base;
1126 struct nv50_disp_sor_dp_mst_link_v0 mst;
1129 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1130 .base.hasht = outp->dcb->hasht,
1131 .base.hashm = outp->dcb->hashm,
1134 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1135 struct nvif_object *disp = &drm->display->disp.object;
1139 /* Even if we're enabling MST, start with disabling the
1140 * branching unit to clear any sink-side MST topology state
1141 * that wasn't set by us
1143 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1148 /* Now, start initializing */
1149 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1156 return nvif_mthd(disp, 0, &args, sizeof(args));
1160 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1162 struct drm_dp_aux *aux;
1164 bool old_state, new_state;
1170 mutex_lock(&mstm->mgr.lock);
1172 old_state = mstm->mgr.mst_state;
1173 new_state = old_state;
1174 aux = mstm->mgr.aux;
1177 /* Just check that the MST hub is still as we expect it */
1178 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1179 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1180 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1183 } else if (dpcd[0] >= 0x12) {
1184 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1188 if (!(dpcd[1] & DP_MST_CAP))
1194 if (new_state == old_state) {
1195 mutex_unlock(&mstm->mgr.lock);
1199 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1203 mutex_unlock(&mstm->mgr.lock);
1205 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1207 return nv50_mstm_enable(mstm, dpcd[0], 0);
1212 mutex_unlock(&mstm->mgr.lock);
1217 nv50_mstm_fini(struct nv50_mstm *mstm)
1219 if (mstm && mstm->mgr.mst_state)
1220 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1224 nv50_mstm_init(struct nv50_mstm *mstm)
1226 if (mstm && mstm->mgr.mst_state)
1227 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1231 nv50_mstm_del(struct nv50_mstm **pmstm)
1233 struct nv50_mstm *mstm = *pmstm;
1241 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1242 int conn_base_id, struct nv50_mstm **pmstm)
1244 const int max_payloads = hweight8(outp->dcb->heads);
1245 struct drm_device *dev = outp->base.base.dev;
1246 struct nv50_mstm *mstm;
1250 /* This is a workaround for some monitors not functioning
1251 * correctly in MST mode on initial module load. I think
1252 * some bad interaction with the VBIOS may be responsible.
1254 * A good ol' off and on again seems to work here ;)
1256 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1257 if (ret >= 0 && dpcd >= 0x12)
1258 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1260 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1263 mstm->mgr.cbs = &nv50_mstm;
1265 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1266 max_payloads, conn_base_id);
1270 for (i = 0; i < max_payloads; i++) {
1271 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1280 /******************************************************************************
1282 *****************************************************************************/
1284 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1285 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1287 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1288 struct nv50_core *core = disp->core;
1291 nv_encoder->ctrl &= ~BIT(head);
1292 if (!(nv_encoder->ctrl & 0x0000000f))
1293 nv_encoder->ctrl = 0;
1295 nv_encoder->ctrl |= proto << 8;
1296 nv_encoder->ctrl |= BIT(head);
1297 asyh->or.depth = depth;
1300 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1304 nv50_sor_disable(struct drm_encoder *encoder)
1306 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1307 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1309 nv_encoder->crtc = NULL;
1312 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1316 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1318 pwr &= ~DP_SET_POWER_MASK;
1319 pwr |= DP_SET_POWER_D3;
1320 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1324 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1325 nv50_audio_disable(encoder, nv_crtc);
1326 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1327 nv50_outp_release(nv_encoder);
1332 nv50_sor_enable(struct drm_encoder *encoder)
1334 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1335 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1336 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1337 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1339 struct nv50_disp_mthd_v1 base;
1340 struct nv50_disp_sor_lvds_script_v0 lvds;
1343 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1344 .base.hasht = nv_encoder->dcb->hasht,
1345 .base.hashm = nv_encoder->dcb->hashm,
1347 struct nv50_disp *disp = nv50_disp(encoder->dev);
1348 struct drm_device *dev = encoder->dev;
1349 struct nouveau_drm *drm = nouveau_drm(dev);
1350 struct nouveau_connector *nv_connector;
1351 struct nvbios *bios = &drm->vbios;
1355 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1356 nv_encoder->crtc = encoder->crtc;
1357 nv50_outp_acquire(nv_encoder);
1359 switch (nv_encoder->dcb->type) {
1360 case DCB_OUTPUT_TMDS:
1361 if (nv_encoder->link & 1) {
1363 /* Only enable dual-link if:
1364 * - Need to (i.e. rate > 165MHz)
1366 * - Not an HDMI monitor, since there's no dual-link
1369 if (mode->clock >= 165000 &&
1370 nv_encoder->dcb->duallink_possible &&
1371 !drm_detect_hdmi_monitor(nv_connector->edid))
1377 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1379 case DCB_OUTPUT_LVDS:
1382 if (bios->fp_no_ddc) {
1383 if (bios->fp.dual_link)
1384 lvds.lvds.script |= 0x0100;
1385 if (bios->fp.if_is_24bit)
1386 lvds.lvds.script |= 0x0200;
1388 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1389 if (((u8 *)nv_connector->edid)[121] == 2)
1390 lvds.lvds.script |= 0x0100;
1392 if (mode->clock >= bios->fp.duallink_transition_clk) {
1393 lvds.lvds.script |= 0x0100;
1396 if (lvds.lvds.script & 0x0100) {
1397 if (bios->fp.strapless_is_24bit & 2)
1398 lvds.lvds.script |= 0x0200;
1400 if (bios->fp.strapless_is_24bit & 1)
1401 lvds.lvds.script |= 0x0200;
1404 if (nv_connector->base.display_info.bpc == 8)
1405 lvds.lvds.script |= 0x0200;
1408 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1411 if (nv_connector->base.display_info.bpc == 6)
1414 if (nv_connector->base.display_info.bpc == 8)
1419 if (nv_encoder->link & 1)
1424 nv50_audio_enable(encoder, mode);
1431 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1434 static const struct drm_encoder_helper_funcs
1436 .atomic_check = nv50_outp_atomic_check,
1437 .enable = nv50_sor_enable,
1438 .disable = nv50_sor_disable,
1442 nv50_sor_destroy(struct drm_encoder *encoder)
1444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1445 nv50_mstm_del(&nv_encoder->dp.mstm);
1446 drm_encoder_cleanup(encoder);
1450 static const struct drm_encoder_funcs
1452 .destroy = nv50_sor_destroy,
1456 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1458 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1459 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1460 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1461 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1462 struct nouveau_encoder *nv_encoder;
1463 struct drm_encoder *encoder;
1464 u8 ver, hdr, cnt, len;
1468 switch (dcbe->type) {
1469 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1470 case DCB_OUTPUT_TMDS:
1473 type = DRM_MODE_ENCODER_TMDS;
1477 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1480 nv_encoder->dcb = dcbe;
1481 nv_encoder->update = nv50_sor_update;
1483 encoder = to_drm_encoder(nv_encoder);
1484 encoder->possible_crtcs = dcbe->heads;
1485 encoder->possible_clones = 0;
1486 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1487 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1488 drm_encoder_helper_add(encoder, &nv50_sor_help);
1490 drm_connector_attach_encoder(connector, encoder);
1492 if (dcbe->type == DCB_OUTPUT_DP) {
1493 struct nv50_disp *disp = nv50_disp(encoder->dev);
1494 struct nvkm_i2c_aux *aux =
1495 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1497 if (disp->disp->object.oclass < GF110_DISP) {
1498 /* HW has no support for address-only
1499 * transactions, so we're required to
1500 * use custom I2C-over-AUX code.
1502 nv_encoder->i2c = &aux->i2c;
1504 nv_encoder->i2c = &nv_connector->aux.ddc;
1506 nv_encoder->aux = aux;
1509 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1510 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1511 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1512 nv_connector->base.base.id,
1513 &nv_encoder->dp.mstm);
1518 struct nvkm_i2c_bus *bus =
1519 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1521 nv_encoder->i2c = &bus->i2c;
1527 /******************************************************************************
1529 *****************************************************************************/
1531 nv50_pior_atomic_check(struct drm_encoder *encoder,
1532 struct drm_crtc_state *crtc_state,
1533 struct drm_connector_state *conn_state)
1535 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1538 crtc_state->adjusted_mode.clock *= 2;
1543 nv50_pior_disable(struct drm_encoder *encoder)
1545 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1546 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1547 if (nv_encoder->crtc)
1548 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1549 nv_encoder->crtc = NULL;
1550 nv50_outp_release(nv_encoder);
1554 nv50_pior_enable(struct drm_encoder *encoder)
1556 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1557 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1558 struct nouveau_connector *nv_connector;
1559 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1560 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1561 u8 owner = 1 << nv_crtc->index;
1564 nv50_outp_acquire(nv_encoder);
1566 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1567 switch (nv_connector->base.display_info.bpc) {
1568 case 10: asyh->or.depth = 0x6; break;
1569 case 8: asyh->or.depth = 0x5; break;
1570 case 6: asyh->or.depth = 0x2; break;
1571 default: asyh->or.depth = 0x0; break;
1574 switch (nv_encoder->dcb->type) {
1575 case DCB_OUTPUT_TMDS:
1584 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1585 nv_encoder->crtc = encoder->crtc;
1588 static const struct drm_encoder_helper_funcs
1590 .atomic_check = nv50_pior_atomic_check,
1591 .enable = nv50_pior_enable,
1592 .disable = nv50_pior_disable,
1596 nv50_pior_destroy(struct drm_encoder *encoder)
1598 drm_encoder_cleanup(encoder);
1602 static const struct drm_encoder_funcs
1604 .destroy = nv50_pior_destroy,
1608 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1610 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1611 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1612 struct nvkm_i2c_bus *bus = NULL;
1613 struct nvkm_i2c_aux *aux = NULL;
1614 struct i2c_adapter *ddc;
1615 struct nouveau_encoder *nv_encoder;
1616 struct drm_encoder *encoder;
1619 switch (dcbe->type) {
1620 case DCB_OUTPUT_TMDS:
1621 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1622 ddc = bus ? &bus->i2c : NULL;
1623 type = DRM_MODE_ENCODER_TMDS;
1626 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1627 ddc = aux ? &aux->i2c : NULL;
1628 type = DRM_MODE_ENCODER_TMDS;
1634 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1637 nv_encoder->dcb = dcbe;
1638 nv_encoder->i2c = ddc;
1639 nv_encoder->aux = aux;
1641 encoder = to_drm_encoder(nv_encoder);
1642 encoder->possible_crtcs = dcbe->heads;
1643 encoder->possible_clones = 0;
1644 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1645 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1646 drm_encoder_helper_add(encoder, &nv50_pior_help);
1648 drm_connector_attach_encoder(connector, encoder);
1652 /******************************************************************************
1654 *****************************************************************************/
1657 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1659 struct nouveau_drm *drm = nouveau_drm(state->dev);
1660 struct nv50_disp *disp = nv50_disp(drm->dev);
1661 struct nv50_core *core = disp->core;
1662 struct nv50_mstm *mstm;
1663 struct drm_encoder *encoder;
1665 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1667 drm_for_each_encoder(encoder, drm->dev) {
1668 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1669 mstm = nouveau_encoder(encoder)->dp.mstm;
1670 if (mstm && mstm->modified)
1671 nv50_mstm_prepare(mstm);
1675 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1676 core->func->update(core, interlock, true);
1677 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1678 disp->core->chan.base.device))
1679 NV_ERROR(drm, "core notifier timeout\n");
1681 drm_for_each_encoder(encoder, drm->dev) {
1682 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1683 mstm = nouveau_encoder(encoder)->dp.mstm;
1684 if (mstm && mstm->modified)
1685 nv50_mstm_cleanup(mstm);
1691 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1693 struct drm_plane_state *new_plane_state;
1694 struct drm_plane *plane;
1697 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1698 struct nv50_wndw *wndw = nv50_wndw(plane);
1699 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1700 if (wndw->func->update)
1701 wndw->func->update(wndw, interlock);
1707 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1709 struct drm_device *dev = state->dev;
1710 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1711 struct drm_crtc *crtc;
1712 struct drm_plane_state *new_plane_state;
1713 struct drm_plane *plane;
1714 struct nouveau_drm *drm = nouveau_drm(dev);
1715 struct nv50_disp *disp = nv50_disp(dev);
1716 struct nv50_atom *atom = nv50_atom(state);
1717 struct nv50_outp_atom *outp, *outt;
1718 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1721 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1722 drm_atomic_helper_wait_for_fences(dev, state, false);
1723 drm_atomic_helper_wait_for_dependencies(state);
1724 drm_atomic_helper_update_legacy_modeset_state(dev, state);
1726 if (atom->lock_core)
1727 mutex_lock(&disp->mutex);
1729 /* Disable head(s). */
1730 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1731 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1732 struct nv50_head *head = nv50_head(crtc);
1734 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1735 asyh->clr.mask, asyh->set.mask);
1736 if (old_crtc_state->active && !new_crtc_state->active)
1737 drm_crtc_vblank_off(crtc);
1739 if (asyh->clr.mask) {
1740 nv50_head_flush_clr(head, asyh, atom->flush_disable);
1741 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1745 /* Disable plane(s). */
1746 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1747 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1748 struct nv50_wndw *wndw = nv50_wndw(plane);
1750 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1751 asyw->clr.mask, asyw->set.mask);
1752 if (!asyw->clr.mask)
1755 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1758 /* Disable output path(s). */
1759 list_for_each_entry(outp, &atom->outp, head) {
1760 const struct drm_encoder_helper_funcs *help;
1761 struct drm_encoder *encoder;
1763 encoder = outp->encoder;
1764 help = encoder->helper_private;
1766 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1767 outp->clr.mask, outp->set.mask);
1769 if (outp->clr.mask) {
1770 help->disable(encoder);
1771 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1772 if (outp->flush_disable) {
1773 nv50_disp_atomic_commit_wndw(state, interlock);
1774 nv50_disp_atomic_commit_core(state, interlock);
1775 memset(interlock, 0x00, sizeof(interlock));
1780 /* Flush disable. */
1781 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1782 if (atom->flush_disable) {
1783 nv50_disp_atomic_commit_wndw(state, interlock);
1784 nv50_disp_atomic_commit_core(state, interlock);
1785 memset(interlock, 0x00, sizeof(interlock));
1789 /* Update output path(s). */
1790 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1791 const struct drm_encoder_helper_funcs *help;
1792 struct drm_encoder *encoder;
1794 encoder = outp->encoder;
1795 help = encoder->helper_private;
1797 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1798 outp->set.mask, outp->clr.mask);
1800 if (outp->set.mask) {
1801 help->enable(encoder);
1802 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1805 list_del(&outp->head);
1809 /* Update head(s). */
1810 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1811 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1812 struct nv50_head *head = nv50_head(crtc);
1814 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1815 asyh->set.mask, asyh->clr.mask);
1817 if (asyh->set.mask) {
1818 nv50_head_flush_set(head, asyh);
1819 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1822 if (new_crtc_state->active) {
1823 if (!old_crtc_state->active)
1824 drm_crtc_vblank_on(crtc);
1825 if (new_crtc_state->event)
1826 drm_crtc_vblank_get(crtc);
1830 /* Update plane(s). */
1831 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1832 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1833 struct nv50_wndw *wndw = nv50_wndw(plane);
1835 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1836 asyw->set.mask, asyw->clr.mask);
1837 if ( !asyw->set.mask &&
1838 (!asyw->clr.mask || atom->flush_disable))
1841 nv50_wndw_flush_set(wndw, interlock, asyw);
1845 nv50_disp_atomic_commit_wndw(state, interlock);
1847 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1848 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1849 interlock[NV50_DISP_INTERLOCK_OVLY] ||
1850 interlock[NV50_DISP_INTERLOCK_WNDW] ||
1851 !atom->state.legacy_cursor_update)
1852 nv50_disp_atomic_commit_core(state, interlock);
1854 disp->core->func->update(disp->core, interlock, false);
1857 if (atom->lock_core)
1858 mutex_unlock(&disp->mutex);
1860 /* Wait for HW to signal completion. */
1861 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1862 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1863 struct nv50_wndw *wndw = nv50_wndw(plane);
1864 int ret = nv50_wndw_wait_armed(wndw, asyw);
1866 NV_ERROR(drm, "%s: timeout\n", plane->name);
1869 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1870 if (new_crtc_state->event) {
1871 unsigned long flags;
1872 /* Get correct count/ts if racing with vblank irq */
1873 if (new_crtc_state->active)
1874 drm_crtc_accurate_vblank_count(crtc);
1875 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1876 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1877 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1879 new_crtc_state->event = NULL;
1880 if (new_crtc_state->active)
1881 drm_crtc_vblank_put(crtc);
1885 drm_atomic_helper_commit_hw_done(state);
1886 drm_atomic_helper_cleanup_planes(dev, state);
1887 drm_atomic_helper_commit_cleanup_done(state);
1888 drm_atomic_state_put(state);
1892 nv50_disp_atomic_commit_work(struct work_struct *work)
1894 struct drm_atomic_state *state =
1895 container_of(work, typeof(*state), commit_work);
1896 nv50_disp_atomic_commit_tail(state);
1900 nv50_disp_atomic_commit(struct drm_device *dev,
1901 struct drm_atomic_state *state, bool nonblock)
1903 struct nouveau_drm *drm = nouveau_drm(dev);
1904 struct drm_plane_state *new_plane_state;
1905 struct drm_plane *plane;
1906 struct drm_crtc *crtc;
1907 bool active = false;
1910 ret = pm_runtime_get_sync(dev->dev);
1911 if (ret < 0 && ret != -EACCES)
1914 ret = drm_atomic_helper_setup_commit(state, nonblock);
1918 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1920 ret = drm_atomic_helper_prepare_planes(dev, state);
1925 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1930 ret = drm_atomic_helper_swap_state(state, true);
1934 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1935 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1936 struct nv50_wndw *wndw = nv50_wndw(plane);
1938 if (asyw->set.image)
1939 nv50_wndw_ntfy_enable(wndw, asyw);
1942 drm_atomic_state_get(state);
1945 queue_work(system_unbound_wq, &state->commit_work);
1947 nv50_disp_atomic_commit_tail(state);
1949 drm_for_each_crtc(crtc, dev) {
1950 if (crtc->state->active) {
1951 if (!drm->have_disp_power_ref) {
1952 drm->have_disp_power_ref = true;
1960 if (!active && drm->have_disp_power_ref) {
1961 pm_runtime_put_autosuspend(dev->dev);
1962 drm->have_disp_power_ref = false;
1967 drm_atomic_helper_cleanup_planes(dev, state);
1969 pm_runtime_put_autosuspend(dev->dev);
1973 static struct nv50_outp_atom *
1974 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
1976 struct nv50_outp_atom *outp;
1978 list_for_each_entry(outp, &atom->outp, head) {
1979 if (outp->encoder == encoder)
1983 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
1985 return ERR_PTR(-ENOMEM);
1987 list_add(&outp->head, &atom->outp);
1988 outp->encoder = encoder;
1993 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
1994 struct drm_connector_state *old_connector_state)
1996 struct drm_encoder *encoder = old_connector_state->best_encoder;
1997 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1998 struct drm_crtc *crtc;
1999 struct nv50_outp_atom *outp;
2001 if (!(crtc = old_connector_state->crtc))
2004 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2005 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2006 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2007 outp = nv50_disp_outp_atomic_add(atom, encoder);
2009 return PTR_ERR(outp);
2011 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2012 outp->flush_disable = true;
2013 atom->flush_disable = true;
2015 outp->clr.ctrl = true;
2016 atom->lock_core = true;
2023 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2024 struct drm_connector_state *connector_state)
2026 struct drm_encoder *encoder = connector_state->best_encoder;
2027 struct drm_crtc_state *new_crtc_state;
2028 struct drm_crtc *crtc;
2029 struct nv50_outp_atom *outp;
2031 if (!(crtc = connector_state->crtc))
2034 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2035 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2036 outp = nv50_disp_outp_atomic_add(atom, encoder);
2038 return PTR_ERR(outp);
2040 outp->set.ctrl = true;
2041 atom->lock_core = true;
2048 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2050 struct nv50_atom *atom = nv50_atom(state);
2051 struct drm_connector_state *old_connector_state, *new_connector_state;
2052 struct drm_connector *connector;
2053 struct drm_crtc_state *new_crtc_state;
2054 struct drm_crtc *crtc;
2057 /* We need to handle colour management on a per-plane basis. */
2058 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2059 if (new_crtc_state->color_mgmt_changed) {
2060 ret = drm_atomic_add_affected_planes(state, crtc);
2066 ret = drm_atomic_helper_check(dev, state);
2070 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2071 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2075 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2084 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2086 struct nv50_atom *atom = nv50_atom(state);
2087 struct nv50_outp_atom *outp, *outt;
2089 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2090 list_del(&outp->head);
2094 drm_atomic_state_default_clear(state);
2098 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2100 struct nv50_atom *atom = nv50_atom(state);
2101 drm_atomic_state_default_release(&atom->state);
2105 static struct drm_atomic_state *
2106 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2108 struct nv50_atom *atom;
2109 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2110 drm_atomic_state_init(dev, &atom->state) < 0) {
2114 INIT_LIST_HEAD(&atom->outp);
2115 return &atom->state;
2118 static const struct drm_mode_config_funcs
2120 .fb_create = nouveau_user_framebuffer_create,
2121 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2122 .atomic_check = nv50_disp_atomic_check,
2123 .atomic_commit = nv50_disp_atomic_commit,
2124 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2125 .atomic_state_clear = nv50_disp_atomic_state_clear,
2126 .atomic_state_free = nv50_disp_atomic_state_free,
2129 /******************************************************************************
2131 *****************************************************************************/
2134 nv50_display_fini(struct drm_device *dev)
2136 struct nouveau_encoder *nv_encoder;
2137 struct drm_encoder *encoder;
2138 struct drm_plane *plane;
2140 drm_for_each_plane(plane, dev) {
2141 struct nv50_wndw *wndw = nv50_wndw(plane);
2142 if (plane->funcs != &nv50_wndw)
2144 nv50_wndw_fini(wndw);
2147 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2148 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2149 nv_encoder = nouveau_encoder(encoder);
2150 nv50_mstm_fini(nv_encoder->dp.mstm);
2156 nv50_display_init(struct drm_device *dev)
2158 struct nv50_core *core = nv50_disp(dev)->core;
2159 struct drm_encoder *encoder;
2160 struct drm_plane *plane;
2162 core->func->init(core);
2164 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2165 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2166 struct nouveau_encoder *nv_encoder =
2167 nouveau_encoder(encoder);
2168 nv50_mstm_init(nv_encoder->dp.mstm);
2172 drm_for_each_plane(plane, dev) {
2173 struct nv50_wndw *wndw = nv50_wndw(plane);
2174 if (plane->funcs != &nv50_wndw)
2176 nv50_wndw_init(wndw);
2183 nv50_display_destroy(struct drm_device *dev)
2185 struct nv50_disp *disp = nv50_disp(dev);
2187 nv50_core_del(&disp->core);
2189 nouveau_bo_unmap(disp->sync);
2191 nouveau_bo_unpin(disp->sync);
2192 nouveau_bo_ref(NULL, &disp->sync);
2194 nouveau_display(dev)->priv = NULL;
2199 nv50_display_create(struct drm_device *dev)
2201 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2202 struct nouveau_drm *drm = nouveau_drm(dev);
2203 struct dcb_table *dcb = &drm->vbios.dcb;
2204 struct drm_connector *connector, *tmp;
2205 struct nv50_disp *disp;
2206 struct dcb_output *dcbe;
2209 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2213 mutex_init(&disp->mutex);
2215 nouveau_display(dev)->priv = disp;
2216 nouveau_display(dev)->dtor = nv50_display_destroy;
2217 nouveau_display(dev)->init = nv50_display_init;
2218 nouveau_display(dev)->fini = nv50_display_fini;
2219 disp->disp = &nouveau_display(dev)->disp;
2220 dev->mode_config.funcs = &nv50_disp_func;
2221 dev->driver->driver_features |= DRIVER_PREFER_XBGR_30BPP;
2223 /* small shared memory area we use for notifiers and semaphores */
2224 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2225 0, 0x0000, NULL, NULL, &disp->sync);
2227 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2229 ret = nouveau_bo_map(disp->sync);
2231 nouveau_bo_unpin(disp->sync);
2234 nouveau_bo_ref(NULL, &disp->sync);
2240 /* allocate master evo channel */
2241 ret = nv50_core_new(drm, &disp->core);
2245 /* create crtc objects to represent the hw heads */
2246 if (disp->disp->object.oclass >= GV100_DISP)
2247 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2249 if (disp->disp->object.oclass >= GF110_DISP)
2250 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2254 for (i = 0; i < fls(crtcs); i++) {
2255 if (!(crtcs & (1 << i)))
2257 ret = nv50_head_create(dev, i);
2262 /* create encoder/connector objects based on VBIOS DCB table */
2263 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2264 connector = nouveau_connector_create(dev, dcbe->connector);
2265 if (IS_ERR(connector))
2268 if (dcbe->location == DCB_LOC_ON_CHIP) {
2269 switch (dcbe->type) {
2270 case DCB_OUTPUT_TMDS:
2271 case DCB_OUTPUT_LVDS:
2273 ret = nv50_sor_create(connector, dcbe);
2275 case DCB_OUTPUT_ANALOG:
2276 ret = nv50_dac_create(connector, dcbe);
2283 ret = nv50_pior_create(connector, dcbe);
2287 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2288 dcbe->location, dcbe->type,
2289 ffs(dcbe->or) - 1, ret);
2294 /* cull any connectors we created that don't have an encoder */
2295 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2296 if (connector->encoder_ids[0])
2299 NV_WARN(drm, "%s has no encoders, removing\n",
2301 connector->funcs->destroy(connector);
2304 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2305 dev->vblank_disable_immediate = true;
2309 nv50_display_destroy(dev);