drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_dp_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_fb_helper.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_vblank.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 static void
 202 evo_flush(struct nv50_dmac *dmac)
 203 {
 204         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 205          * writes have been flushed right through to VRAM before writing PUT.
 206          */
 207         if (dmac->push.type & NVIF_MEM_VRAM) {
 208                 struct nvif_device *device = dmac->base.device;
 209                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 210                 nvif_msec(device, 2000,
 211                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 212                                 break;
 213                 );
 214         }
 215 }
 216
 217 u32 *
 218 evo_wait(struct nv50_dmac *evoc, int nr)
 219 {
 220         struct nv50_dmac *dmac = evoc;
 221         struct nvif_device *device = dmac->base.device;
 222         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 223
 224         mutex_lock(&dmac->lock);
 225         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 226                 dmac->ptr[put] = 0x20000000;
 227                 evo_flush(dmac);
 228
 229                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 230                 if (nvif_msec(device, 2000,
 231                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 232                                 break;
 233                 ) < 0) {
 234                         mutex_unlock(&dmac->lock);
 235                         pr_err("nouveau: evo channel stalled\n");
 236                         return NULL;
 237                 }
 238
 239                 put = 0;
 240         }
 241
 242         return dmac->ptr + put;
 243 }
 244
 245 void
 246 evo_kick(u32 *push, struct nv50_dmac *evoc)
 247 {
 248         struct nv50_dmac *dmac = evoc;
 249
 250         evo_flush(dmac);
 251
 252         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 253         mutex_unlock(&dmac->lock);
 254 }
 255
 256 /******************************************************************************
 257  * Output path helpers
 258  *****************************************************************************/
 259 static void
 260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 261 {
 262         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 263         struct {
 264                 struct nv50_disp_mthd_v1 base;
 265         } args = {
 266                 .base.version = 1,
 267                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 268                 .base.hasht  = nv_encoder->dcb->hasht,
 269                 .base.hashm  = nv_encoder->dcb->hashm,
 270         };
 271
 272         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 273         nv_encoder->or = -1;
 274         nv_encoder->link = 0;
 275 }
 276
 277 static int
 278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 279 {
 280         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 281         struct nv50_disp *disp = nv50_disp(drm->dev);
 282         struct {
 283                 struct nv50_disp_mthd_v1 base;
 284                 struct nv50_disp_acquire_v0 info;
 285         } args = {
 286                 .base.version = 1,
 287                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 288                 .base.hasht  = nv_encoder->dcb->hasht,
 289                 .base.hashm  = nv_encoder->dcb->hashm,
 290         };
 291         int ret;
 292
 293         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 294         if (ret) {
 295                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 296                 return ret;
 297         }
 298
 299         nv_encoder->or = args.info.or;
 300         nv_encoder->link = args.info.link;
 301         return 0;
 302 }
 303
 304 static int
 305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 306                             struct drm_crtc_state *crtc_state,
 307                             struct drm_connector_state *conn_state,
 308                             struct drm_display_mode *native_mode)
 309 {
 310         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 311         struct drm_display_mode *mode = &crtc_state->mode;
 312         struct drm_connector *connector = conn_state->connector;
 313         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 314         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 315
 316         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 317         asyc->scaler.full = false;
 318         if (!native_mode)
 319                 return 0;
 320
 321         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 322                 switch (connector->connector_type) {
 323                 case DRM_MODE_CONNECTOR_LVDS:
 324                 case DRM_MODE_CONNECTOR_eDP:
 325                         /* Don't force scaler for EDID modes with
 326                          * same size as the native one (e.g. different
 327                          * refresh rate)
 328                          */
 329                         if (mode->hdisplay == native_mode->hdisplay &&
 330                             mode->vdisplay == native_mode->vdisplay &&
 331                             mode->type & DRM_MODE_TYPE_DRIVER)
 332                                 break;
 333                         mode = native_mode;
 334                         asyc->scaler.full = true;
 335                         break;
 336                 default:
 337                         break;
 338                 }
 339         } else {
 340                 mode = native_mode;
 341         }
 342
 343         if (!drm_mode_equal(adjusted_mode, mode)) {
 344                 drm_mode_copy(adjusted_mode, mode);
 345                 crtc_state->mode_changed = true;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static int
 352 nv50_outp_atomic_check(struct drm_encoder *encoder,
 353                        struct drm_crtc_state *crtc_state,
 354                        struct drm_connector_state *conn_state)
 355 {
 356         struct drm_connector *connector = conn_state->connector;
 357         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 358         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 359         int ret;
 360
 361         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 362                                           nv_connector->native_mode);
 363         if (ret)
 364                 return ret;
 365
 366         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 367                 asyh->or.bpc = connector->display_info.bpc;
 368
 369         return 0;
 370 }
 371
 372 /******************************************************************************
 373  * DAC
 374  *****************************************************************************/
 375 static void
 376 nv50_dac_disable(struct drm_encoder *encoder)
 377 {
 378         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 379         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 380         if (nv_encoder->crtc)
 381                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 382         nv_encoder->crtc = NULL;
 383         nv50_outp_release(nv_encoder);
 384 }
 385
 386 static void
 387 nv50_dac_enable(struct drm_encoder *encoder)
 388 {
 389         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 390         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 391         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 392         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 393
 394         nv50_outp_acquire(nv_encoder);
 395
 396         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 397         asyh->or.depth = 0;
 398
 399         nv_encoder->crtc = encoder->crtc;
 400 }
 401
 402 static enum drm_connector_status
 403 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 404 {
 405         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 406         struct nv50_disp *disp = nv50_disp(encoder->dev);
 407         struct {
 408                 struct nv50_disp_mthd_v1 base;
 409                 struct nv50_disp_dac_load_v0 load;
 410         } args = {
 411                 .base.version = 1,
 412                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 413                 .base.hasht  = nv_encoder->dcb->hasht,
 414                 .base.hashm  = nv_encoder->dcb->hashm,
 415         };
 416         int ret;
 417
 418         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 419         if (args.load.data == 0)
 420                 args.load.data = 340;
 421
 422         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 423         if (ret || !args.load.load)
 424                 return connector_status_disconnected;
 425
 426         return connector_status_connected;
 427 }
 428
 429 static const struct drm_encoder_helper_funcs
 430 nv50_dac_help = {
 431         .atomic_check = nv50_outp_atomic_check,
 432         .enable = nv50_dac_enable,
 433         .disable = nv50_dac_disable,
 434         .detect = nv50_dac_detect
 435 };
 436
 437 static void
 438 nv50_dac_destroy(struct drm_encoder *encoder)
 439 {
 440         drm_encoder_cleanup(encoder);
 441         kfree(encoder);
 442 }
 443
 444 static const struct drm_encoder_funcs
 445 nv50_dac_func = {
 446         .destroy = nv50_dac_destroy,
 447 };
 448
 449 static int
 450 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 451 {
 452         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 453         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 454         struct nvkm_i2c_bus *bus;
 455         struct nouveau_encoder *nv_encoder;
 456         struct drm_encoder *encoder;
 457         int type = DRM_MODE_ENCODER_DAC;
 458
 459         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 460         if (!nv_encoder)
 461                 return -ENOMEM;
 462         nv_encoder->dcb = dcbe;
 463
 464         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 465         if (bus)
 466                 nv_encoder->i2c = &bus->i2c;
 467
 468         encoder = to_drm_encoder(nv_encoder);
 469         encoder->possible_crtcs = dcbe->heads;
 470         encoder->possible_clones = 0;
 471         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 472                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 473         drm_encoder_helper_add(encoder, &nv50_dac_help);
 474
 475         drm_connector_attach_encoder(connector, encoder);
 476         return 0;
 477 }
 478
 479 /******************************************************************************
 480  * Audio
 481  *****************************************************************************/
 482 static void
 483 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 484 {
 485         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 486         struct nv50_disp *disp = nv50_disp(encoder->dev);
 487         struct {
 488                 struct nv50_disp_mthd_v1 base;
 489                 struct nv50_disp_sor_hda_eld_v0 eld;
 490         } args = {
 491                 .base.version = 1,
 492                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 493                 .base.hasht   = nv_encoder->dcb->hasht,
 494                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 495                                 (0x0100 << nv_crtc->index),
 496         };
 497
 498         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 499 }
 500
 501 static void
 502 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 503 {
 504         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 505         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 506         struct nouveau_connector *nv_connector;
 507         struct nv50_disp *disp = nv50_disp(encoder->dev);
 508         struct __packed {
 509                 struct {
 510                         struct nv50_disp_mthd_v1 mthd;
 511                         struct nv50_disp_sor_hda_eld_v0 eld;
 512                 } base;
 513                 u8 data[sizeof(nv_connector->base.eld)];
 514         } args = {
 515                 .base.mthd.version = 1,
 516                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 517                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 518                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 519                                      (0x0100 << nv_crtc->index),
 520         };
 521
 522         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 523         if (!drm_detect_monitor_audio(nv_connector->edid))
 524                 return;
 525
 526         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 527
 528         nvif_mthd(&disp->disp->object, 0, &args,
 529                   sizeof(args.base) + drm_eld_size(args.data));
 530 }
 531
 532 /******************************************************************************
 533  * HDMI
 534  *****************************************************************************/
 535 static void
 536 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 537 {
 538         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 539         struct nv50_disp *disp = nv50_disp(encoder->dev);
 540         struct {
 541                 struct nv50_disp_mthd_v1 base;
 542                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 543         } args = {
 544                 .base.version = 1,
 545                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 546                 .base.hasht  = nv_encoder->dcb->hasht,
 547                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 548                                (0x0100 << nv_crtc->index),
 549         };
 550
 551         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 552 }
 553
 554 static void
 555 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 556 {
 557         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 558         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 559         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 560         struct nv50_disp *disp = nv50_disp(encoder->dev);
 561         struct {
 562                 struct nv50_disp_mthd_v1 base;
 563                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 564                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 565         } args = {
 566                 .base.version = 1,
 567                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 568                 .base.hasht  = nv_encoder->dcb->hasht,
 569                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 570                                (0x0100 << nv_crtc->index),
 571                 .pwr.state = 1,
 572                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 573         };
 574         struct nouveau_connector *nv_connector;
 575         struct drm_hdmi_info *hdmi;
 576         u32 max_ac_packet;
 577         union hdmi_infoframe avi_frame;
 578         union hdmi_infoframe vendor_frame;
 579         bool high_tmds_clock_ratio = false, scrambling = false;
 580         u8 config;
 581         int ret;
 582         int size;
 583
 584         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 585         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 586                 return;
 587
 588         hdmi = &nv_connector->base.display_info.hdmi;
 589
 590         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 591                                                        &nv_connector->base, mode);
 592         if (!ret) {
 593                 /* We have an AVI InfoFrame, populate it to the display */
 594                 args.pwr.avi_infoframe_length
 595                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 596         }
 597
 598         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 599                                                           &nv_connector->base, mode);
 600         if (!ret) {
 601                 /* We have a Vendor InfoFrame, populate it to the display */
 602                 args.pwr.vendor_infoframe_length
 603                         = hdmi_infoframe_pack(&vendor_frame,
 604                                               args.infoframes
 605                                               + args.pwr.avi_infoframe_length,
 606                                               17);
 607         }
 608
 609         max_ac_packet  = mode->htotal - mode->hdisplay;
 610         max_ac_packet -= args.pwr.rekey;
 611         max_ac_packet -= 18; /* constant from tegra */
 612         args.pwr.max_ac_packet = max_ac_packet / 32;
 613
 614         if (hdmi->scdc.scrambling.supported) {
 615                 high_tmds_clock_ratio = mode->clock > 340000;
 616                 scrambling = high_tmds_clock_ratio ||
 617                         hdmi->scdc.scrambling.low_rates;
 618         }
 619
 620         args.pwr.scdc =
 621                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 622                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 623
 624         size = sizeof(args.base)
 625                 + sizeof(args.pwr)
 626                 + args.pwr.avi_infoframe_length
 627                 + args.pwr.vendor_infoframe_length;
 628         nvif_mthd(&disp->disp->object, 0, &args, size);
 629
 630         nv50_audio_enable(encoder, mode);
 631
 632         /* If SCDC is supported by the downstream monitor, update
 633          * divider / scrambling settings to what we programmed above.
 634          */
 635         if (!hdmi->scdc.scrambling.supported)
 636                 return;
 637
 638         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 639         if (ret < 0) {
 640                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 641                 return;
 642         }
 643         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 644         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 645         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 646         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 647         if (ret < 0)
 648                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 649                          config, ret);
 650 }
 651
 652 /******************************************************************************
 653  * MST
 654  *****************************************************************************/
 655 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 656 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 657 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 658
 659 struct nv50_mstm {
 660         struct nouveau_encoder *outp;
 661
 662         struct drm_dp_mst_topology_mgr mgr;
 663         struct nv50_msto *msto[4];
 664
 665         bool modified;
 666         bool disabled;
 667         int links;
 668 };
 669
 670 struct nv50_mstc {
 671         struct nv50_mstm *mstm;
 672         struct drm_dp_mst_port *port;
 673         struct drm_connector connector;
 674
 675         struct drm_display_mode *native;
 676         struct edid *edid;
 677 };
 678
 679 struct nv50_msto {
 680         struct drm_encoder encoder;
 681
 682         struct nv50_head *head;
 683         struct nv50_mstc *mstc;
 684         bool disabled;
 685 };
 686
 687 static struct drm_dp_payload *
 688 nv50_msto_payload(struct nv50_msto *msto)
 689 {
 690         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 691         struct nv50_mstc *mstc = msto->mstc;
 692         struct nv50_mstm *mstm = mstc->mstm;
 693         int vcpi = mstc->port->vcpi.vcpi, i;
 694
 695         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 696
 697         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 698         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 699                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 700                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 701                           mstm->outp->base.base.name, i, payload->vcpi,
 702                           payload->start_slot, payload->num_slots);
 703         }
 704
 705         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 706                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 707                 if (payload->vcpi == vcpi)
 708                         return payload;
 709         }
 710
 711         return NULL;
 712 }
 713
 714 static void
 715 nv50_msto_cleanup(struct nv50_msto *msto)
 716 {
 717         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 718         struct nv50_mstc *mstc = msto->mstc;
 719         struct nv50_mstm *mstm = mstc->mstm;
 720
 721         if (!msto->disabled)
 722                 return;
 723
 724         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 725
 726         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 727
 728         msto->mstc = NULL;
 729         msto->head = NULL;
 730         msto->disabled = false;
 731 }
 732
 733 static void
 734 nv50_msto_prepare(struct nv50_msto *msto)
 735 {
 736         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 737         struct nv50_mstc *mstc = msto->mstc;
 738         struct nv50_mstm *mstm = mstc->mstm;
 739         struct {
 740                 struct nv50_disp_mthd_v1 base;
 741                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 742         } args = {
 743                 .base.version = 1,
 744                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 745                 .base.hasht  = mstm->outp->dcb->hasht,
 746                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 747                                (0x0100 << msto->head->base.index),
 748         };
 749
 750         mutex_lock(&mstm->mgr.payload_lock);
 751
 752         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 753         if (mstc->port->vcpi.vcpi > 0) {
 754                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 755                 if (payload) {
 756                         args.vcpi.start_slot = payload->start_slot;
 757                         args.vcpi.num_slots = payload->num_slots;
 758                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 759                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 760                 }
 761         }
 762
 763         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 764                   msto->encoder.name, msto->head->base.base.name,
 765                   args.vcpi.start_slot, args.vcpi.num_slots,
 766                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 767
 768         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 769         mutex_unlock(&mstm->mgr.payload_lock);
 770 }
 771
 772 static int
 773 nv50_msto_atomic_check(struct drm_encoder *encoder,
 774                        struct drm_crtc_state *crtc_state,
 775                        struct drm_connector_state *conn_state)
 776 {
 777         struct drm_atomic_state *state = crtc_state->state;
 778         struct drm_connector *connector = conn_state->connector;
 779         struct nv50_mstc *mstc = nv50_mstc(connector);
 780         struct nv50_mstm *mstm = mstc->mstm;
 781         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 782         int slots;
 783         int ret;
 784
 785         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 786                                           mstc->native);
 787         if (ret)
 788                 return ret;
 789
 790         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 791                 return 0;
 792
 793         /*
 794          * When restoring duplicated states, we need to make sure that the bw
 795          * remains the same and avoid recalculating it, as the connector's bpc
 796          * may have changed after the state was duplicated
 797          */
 798         if (!state->duplicated) {
 799                 const int clock = crtc_state->adjusted_mode.clock;
 800
 801                 /*
 802                  * XXX: Since we don't use HDR in userspace quite yet, limit
 803                  * the bpc to 8 to save bandwidth on the topology. In the
 804                  * future, we'll want to properly fix this by dynamically
 805                  * selecting the highest possible bpc that would fit in the
 806                  * topology
 807                  */
 808                 asyh->or.bpc = min(connector->display_info.bpc, 8U);
 809                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, false);
 810         }
 811
 812         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 813                                               asyh->dp.pbn, 0);
 814         if (slots < 0)
 815                 return slots;
 816
 817         asyh->dp.tu = slots;
 818
 819         return 0;
 820 }
 821
 822 static u8
 823 nv50_dp_bpc_to_depth(unsigned int bpc)
 824 {
 825         switch (bpc) {
 826         case  6: return 0x2;
 827         case  8: return 0x5;
 828         case 10: /* fall-through */
 829         default: return 0x6;
 830         }
 831 }
 832
 833 static void
 834 nv50_msto_enable(struct drm_encoder *encoder)
 835 {
 836         struct nv50_head *head = nv50_head(encoder->crtc);
 837         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 838         struct nv50_msto *msto = nv50_msto(encoder);
 839         struct nv50_mstc *mstc = NULL;
 840         struct nv50_mstm *mstm = NULL;
 841         struct drm_connector *connector;
 842         struct drm_connector_list_iter conn_iter;
 843         u8 proto;
 844         bool r;
 845
 846         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 847         drm_for_each_connector_iter(connector, &conn_iter) {
 848                 if (connector->state->best_encoder == &msto->encoder) {
 849                         mstc = nv50_mstc(connector);
 850                         mstm = mstc->mstm;
 851                         break;
 852                 }
 853         }
 854         drm_connector_list_iter_end(&conn_iter);
 855
 856         if (WARN_ON(!mstc))
 857                 return;
 858
 859         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 860                                      armh->dp.tu);
 861         if (!r)
 862                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 863
 864         if (!mstm->links++)
 865                 nv50_outp_acquire(mstm->outp);
 866
 867         if (mstm->outp->link & 1)
 868                 proto = 0x8;
 869         else
 870                 proto = 0x9;
 871
 872         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 873                            nv50_dp_bpc_to_depth(armh->or.bpc));
 874
 875         msto->head = head;
 876         msto->mstc = mstc;
 877         mstm->modified = true;
 878 }
 879
 880 static void
 881 nv50_msto_disable(struct drm_encoder *encoder)
 882 {
 883         struct nv50_msto *msto = nv50_msto(encoder);
 884         struct nv50_mstc *mstc = msto->mstc;
 885         struct nv50_mstm *mstm = mstc->mstm;
 886
 887         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 888
 889         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 890         mstm->modified = true;
 891         if (!--mstm->links)
 892                 mstm->disabled = true;
 893         msto->disabled = true;
 894 }
 895
 896 static const struct drm_encoder_helper_funcs
 897 nv50_msto_help = {
 898         .disable = nv50_msto_disable,
 899         .enable = nv50_msto_enable,
 900         .atomic_check = nv50_msto_atomic_check,
 901 };
 902
 903 static void
 904 nv50_msto_destroy(struct drm_encoder *encoder)
 905 {
 906         struct nv50_msto *msto = nv50_msto(encoder);
 907         drm_encoder_cleanup(&msto->encoder);
 908         kfree(msto);
 909 }
 910
 911 static const struct drm_encoder_funcs
 912 nv50_msto = {
 913         .destroy = nv50_msto_destroy,
 914 };
 915
 916 static int
 917 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 918               struct nv50_msto **pmsto)
 919 {
 920         struct nv50_msto *msto;
 921         int ret;
 922
 923         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 924                 return -ENOMEM;
 925
 926         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 927                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 928         if (ret) {
 929                 kfree(*pmsto);
 930                 *pmsto = NULL;
 931                 return ret;
 932         }
 933
 934         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 935         msto->encoder.possible_crtcs = heads;
 936         return 0;
 937 }
 938
 939 static struct drm_encoder *
 940 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 941                               struct drm_connector_state *connector_state)
 942 {
 943         struct nv50_head *head = nv50_head(connector_state->crtc);
 944         struct nv50_mstc *mstc = nv50_mstc(connector);
 945
 946         return &mstc->mstm->msto[head->base.index]->encoder;
 947 }
 948
 949 static struct drm_encoder *
 950 nv50_mstc_best_encoder(struct drm_connector *connector)
 951 {
 952         struct nv50_mstc *mstc = nv50_mstc(connector);
 953
 954         return &mstc->mstm->msto[0]->encoder;
 955 }
 956
 957 static enum drm_mode_status
 958 nv50_mstc_mode_valid(struct drm_connector *connector,
 959                      struct drm_display_mode *mode)
 960 {
 961         return MODE_OK;
 962 }
 963
 964 static int
 965 nv50_mstc_get_modes(struct drm_connector *connector)
 966 {
 967         struct nv50_mstc *mstc = nv50_mstc(connector);
 968         int ret = 0;
 969
 970         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 971         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 972         if (mstc->edid)
 973                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 974
 975         if (!mstc->connector.display_info.bpc)
 976                 mstc->connector.display_info.bpc = 8;
 977
 978         if (mstc->native)
 979                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 980         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 981         return ret;
 982 }
 983
 984 static int
 985 nv50_mstc_atomic_check(struct drm_connector *connector,
 986                        struct drm_atomic_state *state)
 987 {
 988         struct nv50_mstc *mstc = nv50_mstc(connector);
 989         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
 990         struct drm_connector_state *new_conn_state =
 991                 drm_atomic_get_new_connector_state(state, connector);
 992         struct drm_connector_state *old_conn_state =
 993                 drm_atomic_get_old_connector_state(state, connector);
 994         struct drm_crtc_state *crtc_state;
 995         struct drm_crtc *new_crtc = new_conn_state->crtc;
 996
 997         if (!old_conn_state->crtc)
 998                 return 0;
 999
1000         /* We only want to free VCPI if this state disables the CRTC on this
1001          * connector
1002          */
1003         if (new_crtc) {
1004                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1005
1006                 if (!crtc_state ||
1007                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1008                     crtc_state->enable)
1009                         return 0;
1010         }
1011
1012         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1013 }
1014
1015 static int
1016 nv50_mstc_detect(struct drm_connector *connector,
1017                  struct drm_modeset_acquire_ctx *ctx, bool force)
1018 {
1019         struct nv50_mstc *mstc = nv50_mstc(connector);
1020         int ret;
1021
1022         if (drm_connector_is_unregistered(connector))
1023                 return connector_status_disconnected;
1024
1025         ret = pm_runtime_get_sync(connector->dev->dev);
1026         if (ret < 0 && ret != -EACCES)
1027                 return connector_status_disconnected;
1028
1029         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1030                                      mstc->port);
1031
1032         pm_runtime_mark_last_busy(connector->dev->dev);
1033         pm_runtime_put_autosuspend(connector->dev->dev);
1034         return ret;
1035 }
1036
1037 static const struct drm_connector_helper_funcs
1038 nv50_mstc_help = {
1039         .get_modes = nv50_mstc_get_modes,
1040         .mode_valid = nv50_mstc_mode_valid,
1041         .best_encoder = nv50_mstc_best_encoder,
1042         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1043         .atomic_check = nv50_mstc_atomic_check,
1044         .detect_ctx = nv50_mstc_detect,
1045 };
1046
1047 static void
1048 nv50_mstc_destroy(struct drm_connector *connector)
1049 {
1050         struct nv50_mstc *mstc = nv50_mstc(connector);
1051
1052         drm_connector_cleanup(&mstc->connector);
1053         drm_dp_mst_put_port_malloc(mstc->port);
1054
1055         kfree(mstc);
1056 }
1057
1058 static const struct drm_connector_funcs
1059 nv50_mstc = {
1060         .reset = nouveau_conn_reset,
1061         .fill_modes = drm_helper_probe_single_connector_modes,
1062         .destroy = nv50_mstc_destroy,
1063         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1064         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1065         .atomic_set_property = nouveau_conn_atomic_set_property,
1066         .atomic_get_property = nouveau_conn_atomic_get_property,
1067 };
1068
1069 static int
1070 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1071               const char *path, struct nv50_mstc **pmstc)
1072 {
1073         struct drm_device *dev = mstm->outp->base.base.dev;
1074         struct nv50_mstc *mstc;
1075         int ret, i;
1076
1077         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1078                 return -ENOMEM;
1079         mstc->mstm = mstm;
1080         mstc->port = port;
1081
1082         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1083                                  DRM_MODE_CONNECTOR_DisplayPort);
1084         if (ret) {
1085                 kfree(*pmstc);
1086                 *pmstc = NULL;
1087                 return ret;
1088         }
1089
1090         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1091
1092         mstc->connector.funcs->reset(&mstc->connector);
1093         nouveau_conn_attach_properties(&mstc->connector);
1094
1095         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1096                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1097
1098         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1099         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1100         drm_connector_set_path_property(&mstc->connector, path);
1101         drm_dp_mst_get_port_malloc(port);
1102         return 0;
1103 }
1104
1105 static void
1106 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1107 {
1108         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1109         struct drm_encoder *encoder;
1110         int ret;
1111
1112         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1113         ret = drm_dp_check_act_status(&mstm->mgr);
1114
1115         ret = drm_dp_update_payload_part2(&mstm->mgr);
1116
1117         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1118                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1119                         struct nv50_msto *msto = nv50_msto(encoder);
1120                         struct nv50_mstc *mstc = msto->mstc;
1121                         if (mstc && mstc->mstm == mstm)
1122                                 nv50_msto_cleanup(msto);
1123                 }
1124         }
1125
1126         mstm->modified = false;
1127 }
1128
1129 static void
1130 nv50_mstm_prepare(struct nv50_mstm *mstm)
1131 {
1132         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1133         struct drm_encoder *encoder;
1134         int ret;
1135
1136         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1137         ret = drm_dp_update_payload_part1(&mstm->mgr);
1138
1139         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1140                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1141                         struct nv50_msto *msto = nv50_msto(encoder);
1142                         struct nv50_mstc *mstc = msto->mstc;
1143                         if (mstc && mstc->mstm == mstm)
1144                                 nv50_msto_prepare(msto);
1145                 }
1146         }
1147
1148         if (mstm->disabled) {
1149                 if (!mstm->links)
1150                         nv50_outp_release(mstm->outp);
1151                 mstm->disabled = false;
1152         }
1153 }
1154
1155 static void
1156 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1157                             struct drm_connector *connector)
1158 {
1159         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1160         struct nv50_mstc *mstc = nv50_mstc(connector);
1161
1162         drm_connector_unregister(&mstc->connector);
1163
1164         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1165
1166         drm_connector_put(&mstc->connector);
1167 }
1168
1169 static void
1170 nv50_mstm_register_connector(struct drm_connector *connector)
1171 {
1172         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1173
1174         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1175
1176         drm_connector_register(connector);
1177 }
1178
1179 static struct drm_connector *
1180 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1181                         struct drm_dp_mst_port *port, const char *path)
1182 {
1183         struct nv50_mstm *mstm = nv50_mstm(mgr);
1184         struct nv50_mstc *mstc;
1185         int ret;
1186
1187         ret = nv50_mstc_new(mstm, port, path, &mstc);
1188         if (ret)
1189                 return NULL;
1190
1191         return &mstc->connector;
1192 }
1193
1194 static const struct drm_dp_mst_topology_cbs
1195 nv50_mstm = {
1196         .add_connector = nv50_mstm_add_connector,
1197         .register_connector = nv50_mstm_register_connector,
1198         .destroy_connector = nv50_mstm_destroy_connector,
1199 };
1200
1201 void
1202 nv50_mstm_service(struct nv50_mstm *mstm)
1203 {
1204         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1205         bool handled = true;
1206         int ret;
1207         u8 esi[8] = {};
1208
1209         if (!aux)
1210                 return;
1211
1212         while (handled) {
1213                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1214                 if (ret != 8) {
1215                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1216                         return;
1217                 }
1218
1219                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1220                 if (!handled)
1221                         break;
1222
1223                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1224         }
1225 }
1226
1227 void
1228 nv50_mstm_remove(struct nv50_mstm *mstm)
1229 {
1230         if (mstm)
1231                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1232 }
1233
1234 static int
1235 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1236 {
1237         struct nouveau_encoder *outp = mstm->outp;
1238         struct {
1239                 struct nv50_disp_mthd_v1 base;
1240                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1241         } args = {
1242                 .base.version = 1,
1243                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1244                 .base.hasht = outp->dcb->hasht,
1245                 .base.hashm = outp->dcb->hashm,
1246                 .mst.state = state,
1247         };
1248         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1249         struct nvif_object *disp = &drm->display->disp.object;
1250         int ret;
1251
1252         if (dpcd >= 0x12) {
1253                 /* Even if we're enabling MST, start with disabling the
1254                  * branching unit to clear any sink-side MST topology state
1255                  * that wasn't set by us
1256                  */
1257                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1258                 if (ret < 0)
1259                         return ret;
1260
1261                 if (state) {
1262                         /* Now, start initializing */
1263                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1264                                                  DP_MST_EN);
1265                         if (ret < 0)
1266                                 return ret;
1267                 }
1268         }
1269
1270         return nvif_mthd(disp, 0, &args, sizeof(args));
1271 }
1272
1273 int
1274 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1275 {
1276         struct drm_dp_aux *aux;
1277         int ret;
1278         bool old_state, new_state;
1279         u8 mstm_ctrl;
1280
1281         if (!mstm)
1282                 return 0;
1283
1284         mutex_lock(&mstm->mgr.lock);
1285
1286         old_state = mstm->mgr.mst_state;
1287         new_state = old_state;
1288         aux = mstm->mgr.aux;
1289
1290         if (old_state) {
1291                 /* Just check that the MST hub is still as we expect it */
1292                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1293                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1294                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1295                         new_state = false;
1296                 }
1297         } else if (dpcd[0] >= 0x12) {
1298                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1299                 if (ret < 0)
1300                         goto probe_error;
1301
1302                 if (!(dpcd[1] & DP_MST_CAP))
1303                         dpcd[0] = 0x11;
1304                 else
1305                         new_state = allow;
1306         }
1307
1308         if (new_state == old_state) {
1309                 mutex_unlock(&mstm->mgr.lock);
1310                 return new_state;
1311         }
1312
1313         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1314         if (ret)
1315                 goto probe_error;
1316
1317         mutex_unlock(&mstm->mgr.lock);
1318
1319         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1320         if (ret)
1321                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1322
1323         return new_state;
1324
1325 probe_error:
1326         mutex_unlock(&mstm->mgr.lock);
1327         return ret;
1328 }
1329
1330 static void
1331 nv50_mstm_fini(struct nv50_mstm *mstm)
1332 {
1333         if (mstm && mstm->mgr.mst_state)
1334                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1335 }
1336
1337 static void
1338 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1339 {
1340         int ret;
1341
1342         if (!mstm || !mstm->mgr.mst_state)
1343                 return;
1344
1345         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1346         if (ret == -1) {
1347                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1348                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1349         }
1350 }
1351
1352 static void
1353 nv50_mstm_del(struct nv50_mstm **pmstm)
1354 {
1355         struct nv50_mstm *mstm = *pmstm;
1356         if (mstm) {
1357                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1358                 kfree(*pmstm);
1359                 *pmstm = NULL;
1360         }
1361 }
1362
1363 static int
1364 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1365               int conn_base_id, struct nv50_mstm **pmstm)
1366 {
1367         const int max_payloads = hweight8(outp->dcb->heads);
1368         struct drm_device *dev = outp->base.base.dev;
1369         struct nv50_mstm *mstm;
1370         int ret, i;
1371         u8 dpcd;
1372
1373         /* This is a workaround for some monitors not functioning
1374          * correctly in MST mode on initial module load.  I think
1375          * some bad interaction with the VBIOS may be responsible.
1376          *
1377          * A good ol' off and on again seems to work here ;)
1378          */
1379         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1380         if (ret >= 0 && dpcd >= 0x12)
1381                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1382
1383         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1384                 return -ENOMEM;
1385         mstm->outp = outp;
1386         mstm->mgr.cbs = &nv50_mstm;
1387
1388         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1389                                            max_payloads, conn_base_id);
1390         if (ret)
1391                 return ret;
1392
1393         for (i = 0; i < max_payloads; i++) {
1394                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1395                                     i, &mstm->msto[i]);
1396                 if (ret)
1397                         return ret;
1398         }
1399
1400         return 0;
1401 }
1402
1403 /******************************************************************************
1404  * SOR
1405  *****************************************************************************/
1406 static void
1407 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1408                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1409 {
1410         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1411         struct nv50_core *core = disp->core;
1412
1413         if (!asyh) {
1414                 nv_encoder->ctrl &= ~BIT(head);
1415                 if (!(nv_encoder->ctrl & 0x0000000f))
1416                         nv_encoder->ctrl = 0;
1417         } else {
1418                 nv_encoder->ctrl |= proto << 8;
1419                 nv_encoder->ctrl |= BIT(head);
1420                 asyh->or.depth = depth;
1421         }
1422
1423         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1424 }
1425
1426 static void
1427 nv50_sor_disable(struct drm_encoder *encoder)
1428 {
1429         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1430         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1431
1432         nv_encoder->crtc = NULL;
1433
1434         if (nv_crtc) {
1435                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1436                 u8 pwr;
1437
1438                 if (aux) {
1439                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1440                         if (ret == 0) {
1441                                 pwr &= ~DP_SET_POWER_MASK;
1442                                 pwr |=  DP_SET_POWER_D3;
1443                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1444                         }
1445                 }
1446
1447                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1448                 nv50_audio_disable(encoder, nv_crtc);
1449                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1450                 nv50_outp_release(nv_encoder);
1451         }
1452 }
1453
1454 static void
1455 nv50_sor_enable(struct drm_encoder *encoder)
1456 {
1457         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1458         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1459         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1460         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1461         struct {
1462                 struct nv50_disp_mthd_v1 base;
1463                 struct nv50_disp_sor_lvds_script_v0 lvds;
1464         } lvds = {
1465                 .base.version = 1,
1466                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1467                 .base.hasht   = nv_encoder->dcb->hasht,
1468                 .base.hashm   = nv_encoder->dcb->hashm,
1469         };
1470         struct nv50_disp *disp = nv50_disp(encoder->dev);
1471         struct drm_device *dev = encoder->dev;
1472         struct nouveau_drm *drm = nouveau_drm(dev);
1473         struct nouveau_connector *nv_connector;
1474         struct nvbios *bios = &drm->vbios;
1475         u8 proto = 0xf;
1476         u8 depth = 0x0;
1477
1478         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1479         nv_encoder->crtc = encoder->crtc;
1480         nv50_outp_acquire(nv_encoder);
1481
1482         switch (nv_encoder->dcb->type) {
1483         case DCB_OUTPUT_TMDS:
1484                 if (nv_encoder->link & 1) {
1485                         proto = 0x1;
1486                         /* Only enable dual-link if:
1487                          *  - Need to (i.e. rate > 165MHz)
1488                          *  - DCB says we can
1489                          *  - Not an HDMI monitor, since there's no dual-link
1490                          *    on HDMI.
1491                          */
1492                         if (mode->clock >= 165000 &&
1493                             nv_encoder->dcb->duallink_possible &&
1494                             !drm_detect_hdmi_monitor(nv_connector->edid))
1495                                 proto |= 0x4;
1496                 } else {
1497                         proto = 0x2;
1498                 }
1499
1500                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1501                 break;
1502         case DCB_OUTPUT_LVDS:
1503                 proto = 0x0;
1504
1505                 if (bios->fp_no_ddc) {
1506                         if (bios->fp.dual_link)
1507                                 lvds.lvds.script |= 0x0100;
1508                         if (bios->fp.if_is_24bit)
1509                                 lvds.lvds.script |= 0x0200;
1510                 } else {
1511                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1512                                 if (((u8 *)nv_connector->edid)[121] == 2)
1513                                         lvds.lvds.script |= 0x0100;
1514                         } else
1515                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1516                                 lvds.lvds.script |= 0x0100;
1517                         }
1518
1519                         if (lvds.lvds.script & 0x0100) {
1520                                 if (bios->fp.strapless_is_24bit & 2)
1521                                         lvds.lvds.script |= 0x0200;
1522                         } else {
1523                                 if (bios->fp.strapless_is_24bit & 1)
1524                                         lvds.lvds.script |= 0x0200;
1525                         }
1526
1527                         if (asyh->or.bpc == 8)
1528                                 lvds.lvds.script |= 0x0200;
1529                 }
1530
1531                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1532                 break;
1533         case DCB_OUTPUT_DP:
1534                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1535
1536                 if (nv_encoder->link & 1)
1537                         proto = 0x8;
1538                 else
1539                         proto = 0x9;
1540
1541                 nv50_audio_enable(encoder, mode);
1542                 break;
1543         default:
1544                 BUG();
1545                 break;
1546         }
1547
1548         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1549 }
1550
1551 static const struct drm_encoder_helper_funcs
1552 nv50_sor_help = {
1553         .atomic_check = nv50_outp_atomic_check,
1554         .enable = nv50_sor_enable,
1555         .disable = nv50_sor_disable,
1556 };
1557
1558 static void
1559 nv50_sor_destroy(struct drm_encoder *encoder)
1560 {
1561         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1562         nv50_mstm_del(&nv_encoder->dp.mstm);
1563         drm_encoder_cleanup(encoder);
1564         kfree(encoder);
1565 }
1566
1567 static const struct drm_encoder_funcs
1568 nv50_sor_func = {
1569         .destroy = nv50_sor_destroy,
1570 };
1571
1572 static int
1573 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1574 {
1575         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1576         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1577         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1578         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1579         struct nouveau_encoder *nv_encoder;
1580         struct drm_encoder *encoder;
1581         u8 ver, hdr, cnt, len;
1582         u32 data;
1583         int type, ret;
1584
1585         switch (dcbe->type) {
1586         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1587         case DCB_OUTPUT_TMDS:
1588         case DCB_OUTPUT_DP:
1589         default:
1590                 type = DRM_MODE_ENCODER_TMDS;
1591                 break;
1592         }
1593
1594         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1595         if (!nv_encoder)
1596                 return -ENOMEM;
1597         nv_encoder->dcb = dcbe;
1598         nv_encoder->update = nv50_sor_update;
1599
1600         encoder = to_drm_encoder(nv_encoder);
1601         encoder->possible_crtcs = dcbe->heads;
1602         encoder->possible_clones = 0;
1603         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1604                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1605         drm_encoder_helper_add(encoder, &nv50_sor_help);
1606
1607         drm_connector_attach_encoder(connector, encoder);
1608
1609         if (dcbe->type == DCB_OUTPUT_DP) {
1610                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1611                 struct nvkm_i2c_aux *aux =
1612                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1613                 if (aux) {
1614                         if (disp->disp->object.oclass < GF110_DISP) {
1615                                 /* HW has no support for address-only
1616                                  * transactions, so we're required to
1617                                  * use custom I2C-over-AUX code.
1618                                  */
1619                                 nv_encoder->i2c = &aux->i2c;
1620                         } else {
1621                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1622                         }
1623                         nv_encoder->aux = aux;
1624                 }
1625
1626                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1627                     (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1628                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1629                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1630                                             nv_connector->base.base.id,
1631                                             &nv_encoder->dp.mstm);
1632                         if (ret)
1633                                 return ret;
1634                 }
1635         } else {
1636                 struct nvkm_i2c_bus *bus =
1637                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1638                 if (bus)
1639                         nv_encoder->i2c = &bus->i2c;
1640         }
1641
1642         return 0;
1643 }
1644
1645 /******************************************************************************
1646  * PIOR
1647  *****************************************************************************/
1648 static int
1649 nv50_pior_atomic_check(struct drm_encoder *encoder,
1650                        struct drm_crtc_state *crtc_state,
1651                        struct drm_connector_state *conn_state)
1652 {
1653         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1654         if (ret)
1655                 return ret;
1656         crtc_state->adjusted_mode.clock *= 2;
1657         return 0;
1658 }
1659
1660 static void
1661 nv50_pior_disable(struct drm_encoder *encoder)
1662 {
1663         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1664         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1665         if (nv_encoder->crtc)
1666                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1667         nv_encoder->crtc = NULL;
1668         nv50_outp_release(nv_encoder);
1669 }
1670
1671 static void
1672 nv50_pior_enable(struct drm_encoder *encoder)
1673 {
1674         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1675         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1676         struct nouveau_connector *nv_connector;
1677         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1678         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1679         u8 owner = 1 << nv_crtc->index;
1680         u8 proto;
1681
1682         nv50_outp_acquire(nv_encoder);
1683
1684         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1685         switch (asyh->or.bpc) {
1686         case 10: asyh->or.depth = 0x6; break;
1687         case  8: asyh->or.depth = 0x5; break;
1688         case  6: asyh->or.depth = 0x2; break;
1689         default: asyh->or.depth = 0x0; break;
1690         }
1691
1692         switch (nv_encoder->dcb->type) {
1693         case DCB_OUTPUT_TMDS:
1694         case DCB_OUTPUT_DP:
1695                 proto = 0x0;
1696                 break;
1697         default:
1698                 BUG();
1699                 break;
1700         }
1701
1702         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1703         nv_encoder->crtc = encoder->crtc;
1704 }
1705
1706 static const struct drm_encoder_helper_funcs
1707 nv50_pior_help = {
1708         .atomic_check = nv50_pior_atomic_check,
1709         .enable = nv50_pior_enable,
1710         .disable = nv50_pior_disable,
1711 };
1712
1713 static void
1714 nv50_pior_destroy(struct drm_encoder *encoder)
1715 {
1716         drm_encoder_cleanup(encoder);
1717         kfree(encoder);
1718 }
1719
1720 static const struct drm_encoder_funcs
1721 nv50_pior_func = {
1722         .destroy = nv50_pior_destroy,
1723 };
1724
1725 static int
1726 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1727 {
1728         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1729         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1730         struct nvkm_i2c_bus *bus = NULL;
1731         struct nvkm_i2c_aux *aux = NULL;
1732         struct i2c_adapter *ddc;
1733         struct nouveau_encoder *nv_encoder;
1734         struct drm_encoder *encoder;
1735         int type;
1736
1737         switch (dcbe->type) {
1738         case DCB_OUTPUT_TMDS:
1739                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1740                 ddc  = bus ? &bus->i2c : NULL;
1741                 type = DRM_MODE_ENCODER_TMDS;
1742                 break;
1743         case DCB_OUTPUT_DP:
1744                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1745                 ddc  = aux ? &aux->i2c : NULL;
1746                 type = DRM_MODE_ENCODER_TMDS;
1747                 break;
1748         default:
1749                 return -ENODEV;
1750         }
1751
1752         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1753         if (!nv_encoder)
1754                 return -ENOMEM;
1755         nv_encoder->dcb = dcbe;
1756         nv_encoder->i2c = ddc;
1757         nv_encoder->aux = aux;
1758
1759         encoder = to_drm_encoder(nv_encoder);
1760         encoder->possible_crtcs = dcbe->heads;
1761         encoder->possible_clones = 0;
1762         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1763                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1764         drm_encoder_helper_add(encoder, &nv50_pior_help);
1765
1766         drm_connector_attach_encoder(connector, encoder);
1767         return 0;
1768 }
1769
1770 /******************************************************************************
1771  * Atomic
1772  *****************************************************************************/
1773
1774 static void
1775 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1776 {
1777         struct nouveau_drm *drm = nouveau_drm(state->dev);
1778         struct nv50_disp *disp = nv50_disp(drm->dev);
1779         struct nv50_core *core = disp->core;
1780         struct nv50_mstm *mstm;
1781         struct drm_encoder *encoder;
1782
1783         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1784
1785         drm_for_each_encoder(encoder, drm->dev) {
1786                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1787                         mstm = nouveau_encoder(encoder)->dp.mstm;
1788                         if (mstm && mstm->modified)
1789                                 nv50_mstm_prepare(mstm);
1790                 }
1791         }
1792
1793         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1794         core->func->update(core, interlock, true);
1795         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1796                                        disp->core->chan.base.device))
1797                 NV_ERROR(drm, "core notifier timeout\n");
1798
1799         drm_for_each_encoder(encoder, drm->dev) {
1800                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1801                         mstm = nouveau_encoder(encoder)->dp.mstm;
1802                         if (mstm && mstm->modified)
1803                                 nv50_mstm_cleanup(mstm);
1804                 }
1805         }
1806 }
1807
1808 static void
1809 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1810 {
1811         struct drm_plane_state *new_plane_state;
1812         struct drm_plane *plane;
1813         int i;
1814
1815         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1816                 struct nv50_wndw *wndw = nv50_wndw(plane);
1817                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1818                         if (wndw->func->update)
1819                                 wndw->func->update(wndw, interlock);
1820                 }
1821         }
1822 }
1823
1824 static void
1825 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1826 {
1827         struct drm_device *dev = state->dev;
1828         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1829         struct drm_crtc *crtc;
1830         struct drm_plane_state *new_plane_state;
1831         struct drm_plane *plane;
1832         struct nouveau_drm *drm = nouveau_drm(dev);
1833         struct nv50_disp *disp = nv50_disp(dev);
1834         struct nv50_atom *atom = nv50_atom(state);
1835         struct nv50_outp_atom *outp, *outt;
1836         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1837         int i;
1838
1839         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1840         drm_atomic_helper_wait_for_fences(dev, state, false);
1841         drm_atomic_helper_wait_for_dependencies(state);
1842         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1843
1844         if (atom->lock_core)
1845                 mutex_lock(&disp->mutex);
1846
1847         /* Disable head(s). */
1848         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1849                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1850                 struct nv50_head *head = nv50_head(crtc);
1851
1852                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1853                           asyh->clr.mask, asyh->set.mask);
1854
1855                 if (old_crtc_state->active && !new_crtc_state->active) {
1856                         pm_runtime_put_noidle(dev->dev);
1857                         drm_crtc_vblank_off(crtc);
1858                 }
1859
1860                 if (asyh->clr.mask) {
1861                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1862                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1863                 }
1864         }
1865
1866         /* Disable plane(s). */
1867         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1868                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1869                 struct nv50_wndw *wndw = nv50_wndw(plane);
1870
1871                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1872                           asyw->clr.mask, asyw->set.mask);
1873                 if (!asyw->clr.mask)
1874                         continue;
1875
1876                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1877         }
1878
1879         /* Disable output path(s). */
1880         list_for_each_entry(outp, &atom->outp, head) {
1881                 const struct drm_encoder_helper_funcs *help;
1882                 struct drm_encoder *encoder;
1883
1884                 encoder = outp->encoder;
1885                 help = encoder->helper_private;
1886
1887                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1888                           outp->clr.mask, outp->set.mask);
1889
1890                 if (outp->clr.mask) {
1891                         help->disable(encoder);
1892                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1893                         if (outp->flush_disable) {
1894                                 nv50_disp_atomic_commit_wndw(state, interlock);
1895                                 nv50_disp_atomic_commit_core(state, interlock);
1896                                 memset(interlock, 0x00, sizeof(interlock));
1897                         }
1898                 }
1899         }
1900
1901         /* Flush disable. */
1902         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1903                 if (atom->flush_disable) {
1904                         nv50_disp_atomic_commit_wndw(state, interlock);
1905                         nv50_disp_atomic_commit_core(state, interlock);
1906                         memset(interlock, 0x00, sizeof(interlock));
1907                 }
1908         }
1909
1910         /* Update output path(s). */
1911         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1912                 const struct drm_encoder_helper_funcs *help;
1913                 struct drm_encoder *encoder;
1914
1915                 encoder = outp->encoder;
1916                 help = encoder->helper_private;
1917
1918                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1919                           outp->set.mask, outp->clr.mask);
1920
1921                 if (outp->set.mask) {
1922                         help->enable(encoder);
1923                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1924                 }
1925
1926                 list_del(&outp->head);
1927                 kfree(outp);
1928         }
1929
1930         /* Update head(s). */
1931         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1932                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1933                 struct nv50_head *head = nv50_head(crtc);
1934
1935                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1936                           asyh->set.mask, asyh->clr.mask);
1937
1938                 if (asyh->set.mask) {
1939                         nv50_head_flush_set(head, asyh);
1940                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1941                 }
1942
1943                 if (new_crtc_state->active) {
1944                         if (!old_crtc_state->active) {
1945                                 drm_crtc_vblank_on(crtc);
1946                                 pm_runtime_get_noresume(dev->dev);
1947                         }
1948                         if (new_crtc_state->event)
1949                                 drm_crtc_vblank_get(crtc);
1950                 }
1951         }
1952
1953         /* Update plane(s). */
1954         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1955                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1956                 struct nv50_wndw *wndw = nv50_wndw(plane);
1957
1958                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1959                           asyw->set.mask, asyw->clr.mask);
1960                 if ( !asyw->set.mask &&
1961                     (!asyw->clr.mask || atom->flush_disable))
1962                         continue;
1963
1964                 nv50_wndw_flush_set(wndw, interlock, asyw);
1965         }
1966
1967         /* Flush update. */
1968         nv50_disp_atomic_commit_wndw(state, interlock);
1969
1970         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1971                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1972                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1973                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1974                     !atom->state.legacy_cursor_update)
1975                         nv50_disp_atomic_commit_core(state, interlock);
1976                 else
1977                         disp->core->func->update(disp->core, interlock, false);
1978         }
1979
1980         if (atom->lock_core)
1981                 mutex_unlock(&disp->mutex);
1982
1983         /* Wait for HW to signal completion. */
1984         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1985                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1986                 struct nv50_wndw *wndw = nv50_wndw(plane);
1987                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1988                 if (ret)
1989                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1990         }
1991
1992         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1993                 if (new_crtc_state->event) {
1994                         unsigned long flags;
1995                         /* Get correct count/ts if racing with vblank irq */
1996                         if (new_crtc_state->active)
1997                                 drm_crtc_accurate_vblank_count(crtc);
1998                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1999                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2000                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2001
2002                         new_crtc_state->event = NULL;
2003                         if (new_crtc_state->active)
2004                                 drm_crtc_vblank_put(crtc);
2005                 }
2006         }
2007
2008         drm_atomic_helper_commit_hw_done(state);
2009         drm_atomic_helper_cleanup_planes(dev, state);
2010         drm_atomic_helper_commit_cleanup_done(state);
2011         drm_atomic_state_put(state);
2012
2013         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2014         pm_runtime_mark_last_busy(dev->dev);
2015         pm_runtime_put_autosuspend(dev->dev);
2016 }
2017
2018 static void
2019 nv50_disp_atomic_commit_work(struct work_struct *work)
2020 {
2021         struct drm_atomic_state *state =
2022                 container_of(work, typeof(*state), commit_work);
2023         nv50_disp_atomic_commit_tail(state);
2024 }
2025
2026 static int
2027 nv50_disp_atomic_commit(struct drm_device *dev,
2028                         struct drm_atomic_state *state, bool nonblock)
2029 {
2030         struct drm_plane_state *new_plane_state;
2031         struct drm_plane *plane;
2032         int ret, i;
2033
2034         ret = pm_runtime_get_sync(dev->dev);
2035         if (ret < 0 && ret != -EACCES)
2036                 return ret;
2037
2038         ret = drm_atomic_helper_setup_commit(state, nonblock);
2039         if (ret)
2040                 goto done;
2041
2042         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2043
2044         ret = drm_atomic_helper_prepare_planes(dev, state);
2045         if (ret)
2046                 goto done;
2047
2048         if (!nonblock) {
2049                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2050                 if (ret)
2051                         goto err_cleanup;
2052         }
2053
2054         ret = drm_atomic_helper_swap_state(state, true);
2055         if (ret)
2056                 goto err_cleanup;
2057
2058         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2059                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2060                 struct nv50_wndw *wndw = nv50_wndw(plane);
2061
2062                 if (asyw->set.image)
2063                         nv50_wndw_ntfy_enable(wndw, asyw);
2064         }
2065
2066         drm_atomic_state_get(state);
2067
2068         /*
2069          * Grab another RPM ref for the commit tail, which will release the
2070          * ref when it's finished
2071          */
2072         pm_runtime_get_noresume(dev->dev);
2073
2074         if (nonblock)
2075                 queue_work(system_unbound_wq, &state->commit_work);
2076         else
2077                 nv50_disp_atomic_commit_tail(state);
2078
2079 err_cleanup:
2080         if (ret)
2081                 drm_atomic_helper_cleanup_planes(dev, state);
2082 done:
2083         pm_runtime_put_autosuspend(dev->dev);
2084         return ret;
2085 }
2086
2087 static struct nv50_outp_atom *
2088 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2089 {
2090         struct nv50_outp_atom *outp;
2091
2092         list_for_each_entry(outp, &atom->outp, head) {
2093                 if (outp->encoder == encoder)
2094                         return outp;
2095         }
2096
2097         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2098         if (!outp)
2099                 return ERR_PTR(-ENOMEM);
2100
2101         list_add(&outp->head, &atom->outp);
2102         outp->encoder = encoder;
2103         return outp;
2104 }
2105
2106 static int
2107 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2108                                 struct drm_connector_state *old_connector_state)
2109 {
2110         struct drm_encoder *encoder = old_connector_state->best_encoder;
2111         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2112         struct drm_crtc *crtc;
2113         struct nv50_outp_atom *outp;
2114
2115         if (!(crtc = old_connector_state->crtc))
2116                 return 0;
2117
2118         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2119         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2120         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2121                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2122                 if (IS_ERR(outp))
2123                         return PTR_ERR(outp);
2124
2125                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2126                         outp->flush_disable = true;
2127                         atom->flush_disable = true;
2128                 }
2129                 outp->clr.ctrl = true;
2130                 atom->lock_core = true;
2131         }
2132
2133         return 0;
2134 }
2135
2136 static int
2137 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2138                                 struct drm_connector_state *connector_state)
2139 {
2140         struct drm_encoder *encoder = connector_state->best_encoder;
2141         struct drm_crtc_state *new_crtc_state;
2142         struct drm_crtc *crtc;
2143         struct nv50_outp_atom *outp;
2144
2145         if (!(crtc = connector_state->crtc))
2146                 return 0;
2147
2148         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2149         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2150                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2151                 if (IS_ERR(outp))
2152                         return PTR_ERR(outp);
2153
2154                 outp->set.ctrl = true;
2155                 atom->lock_core = true;
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int
2162 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2163 {
2164         struct nv50_atom *atom = nv50_atom(state);
2165         struct drm_connector_state *old_connector_state, *new_connector_state;
2166         struct drm_connector *connector;
2167         struct drm_crtc_state *new_crtc_state;
2168         struct drm_crtc *crtc;
2169         int ret, i;
2170
2171         /* We need to handle colour management on a per-plane basis. */
2172         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2173                 if (new_crtc_state->color_mgmt_changed) {
2174                         ret = drm_atomic_add_affected_planes(state, crtc);
2175                         if (ret)
2176                                 return ret;
2177                 }
2178         }
2179
2180         ret = drm_atomic_helper_check(dev, state);
2181         if (ret)
2182                 return ret;
2183
2184         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2185                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2186                 if (ret)
2187                         return ret;
2188
2189                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2190                 if (ret)
2191                         return ret;
2192         }
2193
2194         ret = drm_dp_mst_atomic_check(state);
2195         if (ret)
2196                 return ret;
2197
2198         return 0;
2199 }
2200
2201 static void
2202 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2203 {
2204         struct nv50_atom *atom = nv50_atom(state);
2205         struct nv50_outp_atom *outp, *outt;
2206
2207         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2208                 list_del(&outp->head);
2209                 kfree(outp);
2210         }
2211
2212         drm_atomic_state_default_clear(state);
2213 }
2214
2215 static void
2216 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2217 {
2218         struct nv50_atom *atom = nv50_atom(state);
2219         drm_atomic_state_default_release(&atom->state);
2220         kfree(atom);
2221 }
2222
2223 static struct drm_atomic_state *
2224 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2225 {
2226         struct nv50_atom *atom;
2227         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2228             drm_atomic_state_init(dev, &atom->state) < 0) {
2229                 kfree(atom);
2230                 return NULL;
2231         }
2232         INIT_LIST_HEAD(&atom->outp);
2233         return &atom->state;
2234 }
2235
2236 static const struct drm_mode_config_funcs
2237 nv50_disp_func = {
2238         .fb_create = nouveau_user_framebuffer_create,
2239         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2240         .atomic_check = nv50_disp_atomic_check,
2241         .atomic_commit = nv50_disp_atomic_commit,
2242         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2243         .atomic_state_clear = nv50_disp_atomic_state_clear,
2244         .atomic_state_free = nv50_disp_atomic_state_free,
2245 };
2246
2247 /******************************************************************************
2248  * Init
2249  *****************************************************************************/
2250
2251 static void
2252 nv50_display_fini(struct drm_device *dev, bool suspend)
2253 {
2254         struct nouveau_encoder *nv_encoder;
2255         struct drm_encoder *encoder;
2256         struct drm_plane *plane;
2257
2258         drm_for_each_plane(plane, dev) {
2259                 struct nv50_wndw *wndw = nv50_wndw(plane);
2260                 if (plane->funcs != &nv50_wndw)
2261                         continue;
2262                 nv50_wndw_fini(wndw);
2263         }
2264
2265         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2266                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2267                         nv_encoder = nouveau_encoder(encoder);
2268                         nv50_mstm_fini(nv_encoder->dp.mstm);
2269                 }
2270         }
2271 }
2272
2273 static int
2274 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2275 {
2276         struct nv50_core *core = nv50_disp(dev)->core;
2277         struct drm_encoder *encoder;
2278         struct drm_plane *plane;
2279
2280         core->func->init(core);
2281
2282         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2283                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2284                         struct nouveau_encoder *nv_encoder =
2285                                 nouveau_encoder(encoder);
2286                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2287                 }
2288         }
2289
2290         drm_for_each_plane(plane, dev) {
2291                 struct nv50_wndw *wndw = nv50_wndw(plane);
2292                 if (plane->funcs != &nv50_wndw)
2293                         continue;
2294                 nv50_wndw_init(wndw);
2295         }
2296
2297         return 0;
2298 }
2299
2300 static void
2301 nv50_display_destroy(struct drm_device *dev)
2302 {
2303         struct nv50_disp *disp = nv50_disp(dev);
2304
2305         nv50_core_del(&disp->core);
2306
2307         nouveau_bo_unmap(disp->sync);
2308         if (disp->sync)
2309                 nouveau_bo_unpin(disp->sync);
2310         nouveau_bo_ref(NULL, &disp->sync);
2311
2312         nouveau_display(dev)->priv = NULL;
2313         kfree(disp);
2314 }
2315
2316 int
2317 nv50_display_create(struct drm_device *dev)
2318 {
2319         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2320         struct nouveau_drm *drm = nouveau_drm(dev);
2321         struct dcb_table *dcb = &drm->vbios.dcb;
2322         struct drm_connector *connector, *tmp;
2323         struct nv50_disp *disp;
2324         struct dcb_output *dcbe;
2325         int crtcs, ret, i;
2326
2327         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2328         if (!disp)
2329                 return -ENOMEM;
2330
2331         mutex_init(&disp->mutex);
2332
2333         nouveau_display(dev)->priv = disp;
2334         nouveau_display(dev)->dtor = nv50_display_destroy;
2335         nouveau_display(dev)->init = nv50_display_init;
2336         nouveau_display(dev)->fini = nv50_display_fini;
2337         disp->disp = &nouveau_display(dev)->disp;
2338         dev->mode_config.funcs = &nv50_disp_func;
2339         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2340         dev->mode_config.normalize_zpos = true;
2341
2342         /* small shared memory area we use for notifiers and semaphores */
2343         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2344                              0, 0x0000, NULL, NULL, &disp->sync);
2345         if (!ret) {
2346                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2347                 if (!ret) {
2348                         ret = nouveau_bo_map(disp->sync);
2349                         if (ret)
2350                                 nouveau_bo_unpin(disp->sync);
2351                 }
2352                 if (ret)
2353                         nouveau_bo_ref(NULL, &disp->sync);
2354         }
2355
2356         if (ret)
2357                 goto out;
2358
2359         /* allocate master evo channel */
2360         ret = nv50_core_new(drm, &disp->core);
2361         if (ret)
2362                 goto out;
2363
2364         /* create crtc objects to represent the hw heads */
2365         if (disp->disp->object.oclass >= GV100_DISP)
2366                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2367         else
2368         if (disp->disp->object.oclass >= GF110_DISP)
2369                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2370         else
2371                 crtcs = 0x3;
2372
2373         for (i = 0; i < fls(crtcs); i++) {
2374                 if (!(crtcs & (1 << i)))
2375                         continue;
2376                 ret = nv50_head_create(dev, i);
2377                 if (ret)
2378                         goto out;
2379         }
2380
2381         /* create encoder/connector objects based on VBIOS DCB table */
2382         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2383                 connector = nouveau_connector_create(dev, dcbe);
2384                 if (IS_ERR(connector))
2385                         continue;
2386
2387                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2388                         switch (dcbe->type) {
2389                         case DCB_OUTPUT_TMDS:
2390                         case DCB_OUTPUT_LVDS:
2391                         case DCB_OUTPUT_DP:
2392                                 ret = nv50_sor_create(connector, dcbe);
2393                                 break;
2394                         case DCB_OUTPUT_ANALOG:
2395                                 ret = nv50_dac_create(connector, dcbe);
2396                                 break;
2397                         default:
2398                                 ret = -ENODEV;
2399                                 break;
2400                         }
2401                 } else {
2402                         ret = nv50_pior_create(connector, dcbe);
2403                 }
2404
2405                 if (ret) {
2406                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2407                                      dcbe->location, dcbe->type,
2408                                      ffs(dcbe->or) - 1, ret);
2409                         ret = 0;
2410                 }
2411         }
2412
2413         /* cull any connectors we created that don't have an encoder */
2414         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2415                 if (connector->possible_encoders)
2416                         continue;
2417
2418                 NV_WARN(drm, "%s has no encoders, removing\n",
2419                         connector->name);
2420                 connector->funcs->destroy(connector);
2421         }
2422
2423         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2424         dev->vblank_disable_immediate = true;
2425
2426 out:
2427         if (ret)
2428                 nv50_display_destroy(dev);
2429         return ret;
2430 }