drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32 #include <linux/component.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_scdc_helper.h>
  41 #include <drm/drm_vblank.h>
  42
  43 #include <nvif/class.h>
  44 #include <nvif/cl0002.h>
  45 #include <nvif/cl5070.h>
  46 #include <nvif/cl507d.h>
  47 #include <nvif/event.h>
  48 #include <nvif/timer.h>
  49
  50 #include "nouveau_drv.h"
  51 #include "nouveau_dma.h"
  52 #include "nouveau_gem.h"
  53 #include "nouveau_connector.h"
  54 #include "nouveau_encoder.h"
  55 #include "nouveau_fence.h"
  56 #include "nouveau_fbcon.h"
  57
  58 #include <subdev/bios/dp.h>
  59
  60 /******************************************************************************
  61  * Atomic state
  62  *****************************************************************************/
  63
  64 struct nv50_outp_atom {
  65         struct list_head head;
  66
  67         struct drm_encoder *encoder;
  68         bool flush_disable;
  69
  70         union nv50_outp_atom_mask {
  71                 struct {
  72                         bool ctrl:1;
  73                 };
  74                 u8 mask;
  75         } set, clr;
  76 };
  77
  78 /******************************************************************************
  79  * EVO channel
  80  *****************************************************************************/
  81
  82 static int
  83 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  84                  const s32 *oclass, u8 head, void *data, u32 size,
  85                  struct nv50_chan *chan)
  86 {
  87         struct nvif_sclass *sclass;
  88         int ret, i, n;
  89
  90         chan->device = device;
  91
  92         ret = n = nvif_object_sclass_get(disp, &sclass);
  93         if (ret < 0)
  94                 return ret;
  95
  96         while (oclass[0]) {
  97                 for (i = 0; i < n; i++) {
  98                         if (sclass[i].oclass == oclass[0]) {
  99                                 ret = nvif_object_init(disp, 0, oclass[0],
 100                                                        data, size, &chan->user);
 101                                 if (ret == 0)
 102                                         nvif_object_map(&chan->user, NULL, 0);
 103                                 nvif_object_sclass_put(&sclass);
 104                                 return ret;
 105                         }
 106                 }
 107                 oclass++;
 108         }
 109
 110         nvif_object_sclass_put(&sclass);
 111         return -ENOSYS;
 112 }
 113
 114 static void
 115 nv50_chan_destroy(struct nv50_chan *chan)
 116 {
 117         nvif_object_fini(&chan->user);
 118 }
 119
 120 /******************************************************************************
 121  * DMA EVO channel
 122  *****************************************************************************/
 123
 124 void
 125 nv50_dmac_destroy(struct nv50_dmac *dmac)
 126 {
 127         nvif_object_fini(&dmac->vram);
 128         nvif_object_fini(&dmac->sync);
 129
 130         nv50_chan_destroy(&dmac->base);
 131
 132         nvif_mem_fini(&dmac->push);
 133 }
 134
 135 int
 136 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 137                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 138                  struct nv50_dmac *dmac)
 139 {
 140         struct nouveau_cli *cli = (void *)device->object.client;
 141         struct nv50_disp_core_channel_dma_v0 *args = data;
 142         u8 type = NVIF_MEM_COHERENT;
 143         int ret;
 144
 145         mutex_init(&dmac->lock);
 146
 147         /* Pascal added support for 47-bit physical addresses, but some
 148          * parts of EVO still only accept 40-bit PAs.
 149          *
 150          * To avoid issues on systems with large amounts of RAM, and on
 151          * systems where an IOMMU maps pages at a high address, we need
 152          * to allocate push buffers in VRAM instead.
 153          *
 154          * This appears to match NVIDIA's behaviour on Pascal.
 155          */
 156         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 157                 type |= NVIF_MEM_VRAM;
 158
 159         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 160         if (ret)
 161                 return ret;
 162
 163         dmac->ptr = dmac->push.object.map.ptr;
 164
 165         args->pushbuf = nvif_handle(&dmac->push.object);
 166
 167         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 168                                &dmac->base);
 169         if (ret)
 170                 return ret;
 171
 172         if (!syncbuf)
 173                 return 0;
 174
 175         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 176                                &(struct nv_dma_v0) {
 177                                         .target = NV_DMA_V0_TARGET_VRAM,
 178                                         .access = NV_DMA_V0_ACCESS_RDWR,
 179                                         .start = syncbuf + 0x0000,
 180                                         .limit = syncbuf + 0x0fff,
 181                                }, sizeof(struct nv_dma_v0),
 182                                &dmac->sync);
 183         if (ret)
 184                 return ret;
 185
 186         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 187                                &(struct nv_dma_v0) {
 188                                         .target = NV_DMA_V0_TARGET_VRAM,
 189                                         .access = NV_DMA_V0_ACCESS_RDWR,
 190                                         .start = 0,
 191                                         .limit = device->info.ram_user - 1,
 192                                }, sizeof(struct nv_dma_v0),
 193                                &dmac->vram);
 194         if (ret)
 195                 return ret;
 196
 197         return ret;
 198 }
 199
 200 /******************************************************************************
 201  * EVO channel helpers
 202  *****************************************************************************/
 203 static void
 204 evo_flush(struct nv50_dmac *dmac)
 205 {
 206         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 207          * writes have been flushed right through to VRAM before writing PUT.
 208          */
 209         if (dmac->push.type & NVIF_MEM_VRAM) {
 210                 struct nvif_device *device = dmac->base.device;
 211                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 212                 nvif_msec(device, 2000,
 213                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 214                                 break;
 215                 );
 216         }
 217 }
 218
 219 u32 *
 220 evo_wait(struct nv50_dmac *evoc, int nr)
 221 {
 222         struct nv50_dmac *dmac = evoc;
 223         struct nvif_device *device = dmac->base.device;
 224         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 225
 226         mutex_lock(&dmac->lock);
 227         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 228                 dmac->ptr[put] = 0x20000000;
 229                 evo_flush(dmac);
 230
 231                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 232                 if (nvif_msec(device, 2000,
 233                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 234                                 break;
 235                 ) < 0) {
 236                         mutex_unlock(&dmac->lock);
 237                         pr_err("nouveau: evo channel stalled\n");
 238                         return NULL;
 239                 }
 240
 241                 put = 0;
 242         }
 243
 244         return dmac->ptr + put;
 245 }
 246
 247 void
 248 evo_kick(u32 *push, struct nv50_dmac *evoc)
 249 {
 250         struct nv50_dmac *dmac = evoc;
 251
 252         evo_flush(dmac);
 253
 254         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 255         mutex_unlock(&dmac->lock);
 256 }
 257
 258 /******************************************************************************
 259  * Output path helpers
 260  *****************************************************************************/
 261 static void
 262 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 263 {
 264         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 265         struct {
 266                 struct nv50_disp_mthd_v1 base;
 267         } args = {
 268                 .base.version = 1,
 269                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 270                 .base.hasht  = nv_encoder->dcb->hasht,
 271                 .base.hashm  = nv_encoder->dcb->hashm,
 272         };
 273
 274         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 275         nv_encoder->or = -1;
 276         nv_encoder->link = 0;
 277 }
 278
 279 static int
 280 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 281 {
 282         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 283         struct nv50_disp *disp = nv50_disp(drm->dev);
 284         struct {
 285                 struct nv50_disp_mthd_v1 base;
 286                 struct nv50_disp_acquire_v0 info;
 287         } args = {
 288                 .base.version = 1,
 289                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 290                 .base.hasht  = nv_encoder->dcb->hasht,
 291                 .base.hashm  = nv_encoder->dcb->hashm,
 292         };
 293         int ret;
 294
 295         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 296         if (ret) {
 297                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 298                 return ret;
 299         }
 300
 301         nv_encoder->or = args.info.or;
 302         nv_encoder->link = args.info.link;
 303         return 0;
 304 }
 305
 306 static int
 307 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 308                             struct drm_crtc_state *crtc_state,
 309                             struct drm_connector_state *conn_state,
 310                             struct drm_display_mode *native_mode)
 311 {
 312         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 313         struct drm_display_mode *mode = &crtc_state->mode;
 314         struct drm_connector *connector = conn_state->connector;
 315         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 316         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 317
 318         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 319         asyc->scaler.full = false;
 320         if (!native_mode)
 321                 return 0;
 322
 323         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 324                 switch (connector->connector_type) {
 325                 case DRM_MODE_CONNECTOR_LVDS:
 326                 case DRM_MODE_CONNECTOR_eDP:
 327                         /* Don't force scaler for EDID modes with
 328                          * same size as the native one (e.g. different
 329                          * refresh rate)
 330                          */
 331                         if (mode->hdisplay == native_mode->hdisplay &&
 332                             mode->vdisplay == native_mode->vdisplay &&
 333                             mode->type & DRM_MODE_TYPE_DRIVER)
 334                                 break;
 335                         mode = native_mode;
 336                         asyc->scaler.full = true;
 337                         break;
 338                 default:
 339                         break;
 340                 }
 341         } else {
 342                 mode = native_mode;
 343         }
 344
 345         if (!drm_mode_equal(adjusted_mode, mode)) {
 346                 drm_mode_copy(adjusted_mode, mode);
 347                 crtc_state->mode_changed = true;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int
 354 nv50_outp_atomic_check(struct drm_encoder *encoder,
 355                        struct drm_crtc_state *crtc_state,
 356                        struct drm_connector_state *conn_state)
 357 {
 358         struct drm_connector *connector = conn_state->connector;
 359         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 360         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 361         int ret;
 362
 363         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 364                                           nv_connector->native_mode);
 365         if (ret)
 366                 return ret;
 367
 368         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 369                 asyh->or.bpc = connector->display_info.bpc;
 370
 371         return 0;
 372 }
 373
 374 /******************************************************************************
 375  * DAC
 376  *****************************************************************************/
 377 static void
 378 nv50_dac_disable(struct drm_encoder *encoder)
 379 {
 380         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 381         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 382         if (nv_encoder->crtc)
 383                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 384         nv_encoder->crtc = NULL;
 385         nv50_outp_release(nv_encoder);
 386 }
 387
 388 static void
 389 nv50_dac_enable(struct drm_encoder *encoder)
 390 {
 391         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 392         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 393         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 394         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 395
 396         nv50_outp_acquire(nv_encoder);
 397
 398         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 399         asyh->or.depth = 0;
 400
 401         nv_encoder->crtc = encoder->crtc;
 402 }
 403
 404 static enum drm_connector_status
 405 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 406 {
 407         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 408         struct nv50_disp *disp = nv50_disp(encoder->dev);
 409         struct {
 410                 struct nv50_disp_mthd_v1 base;
 411                 struct nv50_disp_dac_load_v0 load;
 412         } args = {
 413                 .base.version = 1,
 414                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 415                 .base.hasht  = nv_encoder->dcb->hasht,
 416                 .base.hashm  = nv_encoder->dcb->hashm,
 417         };
 418         int ret;
 419
 420         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 421         if (args.load.data == 0)
 422                 args.load.data = 340;
 423
 424         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 425         if (ret || !args.load.load)
 426                 return connector_status_disconnected;
 427
 428         return connector_status_connected;
 429 }
 430
 431 static const struct drm_encoder_helper_funcs
 432 nv50_dac_help = {
 433         .atomic_check = nv50_outp_atomic_check,
 434         .enable = nv50_dac_enable,
 435         .disable = nv50_dac_disable,
 436         .detect = nv50_dac_detect
 437 };
 438
 439 static void
 440 nv50_dac_destroy(struct drm_encoder *encoder)
 441 {
 442         drm_encoder_cleanup(encoder);
 443         kfree(encoder);
 444 }
 445
 446 static const struct drm_encoder_funcs
 447 nv50_dac_func = {
 448         .destroy = nv50_dac_destroy,
 449 };
 450
 451 static int
 452 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 453 {
 454         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 455         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 456         struct nvkm_i2c_bus *bus;
 457         struct nouveau_encoder *nv_encoder;
 458         struct drm_encoder *encoder;
 459         int type = DRM_MODE_ENCODER_DAC;
 460
 461         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 462         if (!nv_encoder)
 463                 return -ENOMEM;
 464         nv_encoder->dcb = dcbe;
 465
 466         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 467         if (bus)
 468                 nv_encoder->i2c = &bus->i2c;
 469
 470         encoder = to_drm_encoder(nv_encoder);
 471         encoder->possible_crtcs = dcbe->heads;
 472         encoder->possible_clones = 0;
 473         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 474                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 475         drm_encoder_helper_add(encoder, &nv50_dac_help);
 476
 477         drm_connector_attach_encoder(connector, encoder);
 478         return 0;
 479 }
 480
 481 /*
 482  * audio component binding for ELD notification
 483  */
 484 static void
 485 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 486                                 int dev_id)
 487 {
 488         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 489                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 490                                                  port, dev_id);
 491 }
 492
 493 static int
 494 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 495                              bool *enabled, unsigned char *buf, int max_bytes)
 496 {
 497         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 498         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 499         struct drm_encoder *encoder;
 500         struct nouveau_encoder *nv_encoder;
 501         struct nouveau_connector *nv_connector;
 502         struct nouveau_crtc *nv_crtc;
 503         int ret = 0;
 504
 505         *enabled = false;
 506         drm_for_each_encoder(encoder, drm->dev) {
 507                 nv_encoder = nouveau_encoder(encoder);
 508                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 509                 nv_crtc = nouveau_crtc(encoder->crtc);
 510                 if (!nv_connector || !nv_crtc || nv_encoder->or != port ||
 511                     nv_crtc->index != dev_id)
 512                         continue;
 513                 *enabled = drm_detect_monitor_audio(nv_connector->edid);
 514                 if (*enabled) {
 515                         ret = drm_eld_size(nv_connector->base.eld);
 516                         memcpy(buf, nv_connector->base.eld,
 517                                min(max_bytes, ret));
 518                 }
 519                 break;
 520         }
 521         return ret;
 522 }
 523
 524 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 525         .get_eld = nv50_audio_component_get_eld,
 526 };
 527
 528 static int
 529 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 530                           void *data)
 531 {
 532         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 533         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 534         struct drm_audio_component *acomp = data;
 535
 536         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 537                 return -ENOMEM;
 538
 539         drm_modeset_lock_all(drm_dev);
 540         acomp->ops = &nv50_audio_component_ops;
 541         acomp->dev = kdev;
 542         drm->audio.component = acomp;
 543         drm_modeset_unlock_all(drm_dev);
 544         return 0;
 545 }
 546
 547 static void
 548 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 549                             void *data)
 550 {
 551         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 552         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 553         struct drm_audio_component *acomp = data;
 554
 555         drm_modeset_lock_all(drm_dev);
 556         drm->audio.component = NULL;
 557         acomp->ops = NULL;
 558         acomp->dev = NULL;
 559         drm_modeset_unlock_all(drm_dev);
 560 }
 561
 562 static const struct component_ops nv50_audio_component_bind_ops = {
 563         .bind   = nv50_audio_component_bind,
 564         .unbind = nv50_audio_component_unbind,
 565 };
 566
 567 static void
 568 nv50_audio_component_init(struct nouveau_drm *drm)
 569 {
 570         if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 571                 drm->audio.component_registered = true;
 572 }
 573
 574 static void
 575 nv50_audio_component_fini(struct nouveau_drm *drm)
 576 {
 577         if (drm->audio.component_registered) {
 578                 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 579                 drm->audio.component_registered = false;
 580         }
 581 }
 582
 583 /******************************************************************************
 584  * Audio
 585  *****************************************************************************/
 586 static void
 587 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 588 {
 589         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 590         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 591         struct nv50_disp *disp = nv50_disp(encoder->dev);
 592         struct {
 593                 struct nv50_disp_mthd_v1 base;
 594                 struct nv50_disp_sor_hda_eld_v0 eld;
 595         } args = {
 596                 .base.version = 1,
 597                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 598                 .base.hasht   = nv_encoder->dcb->hasht,
 599                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 600                                 (0x0100 << nv_crtc->index),
 601         };
 602
 603         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 604
 605         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 606                                         nv_crtc->index);
 607 }
 608
 609 static void
 610 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 611 {
 612         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 613         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 614         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 615         struct nouveau_connector *nv_connector;
 616         struct nv50_disp *disp = nv50_disp(encoder->dev);
 617         struct __packed {
 618                 struct {
 619                         struct nv50_disp_mthd_v1 mthd;
 620                         struct nv50_disp_sor_hda_eld_v0 eld;
 621                 } base;
 622                 u8 data[sizeof(nv_connector->base.eld)];
 623         } args = {
 624                 .base.mthd.version = 1,
 625                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 626                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 627                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 628                                      (0x0100 << nv_crtc->index),
 629         };
 630
 631         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 632         if (!drm_detect_monitor_audio(nv_connector->edid))
 633                 return;
 634
 635         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 636
 637         nvif_mthd(&disp->disp->object, 0, &args,
 638                   sizeof(args.base) + drm_eld_size(args.data));
 639
 640         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 641                                         nv_crtc->index);
 642 }
 643
 644 /******************************************************************************
 645  * HDMI
 646  *****************************************************************************/
 647 static void
 648 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 649 {
 650         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 651         struct nv50_disp *disp = nv50_disp(encoder->dev);
 652         struct {
 653                 struct nv50_disp_mthd_v1 base;
 654                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 655         } args = {
 656                 .base.version = 1,
 657                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 658                 .base.hasht  = nv_encoder->dcb->hasht,
 659                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 660                                (0x0100 << nv_crtc->index),
 661         };
 662
 663         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 664 }
 665
 666 static void
 667 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 668 {
 669         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 670         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 671         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 672         struct nv50_disp *disp = nv50_disp(encoder->dev);
 673         struct {
 674                 struct nv50_disp_mthd_v1 base;
 675                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 676                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 677         } args = {
 678                 .base.version = 1,
 679                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 680                 .base.hasht  = nv_encoder->dcb->hasht,
 681                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 682                                (0x0100 << nv_crtc->index),
 683                 .pwr.state = 1,
 684                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 685         };
 686         struct nouveau_connector *nv_connector;
 687         struct drm_hdmi_info *hdmi;
 688         u32 max_ac_packet;
 689         union hdmi_infoframe avi_frame;
 690         union hdmi_infoframe vendor_frame;
 691         bool high_tmds_clock_ratio = false, scrambling = false;
 692         u8 config;
 693         int ret;
 694         int size;
 695
 696         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 697         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 698                 return;
 699
 700         hdmi = &nv_connector->base.display_info.hdmi;
 701
 702         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 703                                                        &nv_connector->base, mode);
 704         if (!ret) {
 705                 /* We have an AVI InfoFrame, populate it to the display */
 706                 args.pwr.avi_infoframe_length
 707                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 708         }
 709
 710         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 711                                                           &nv_connector->base, mode);
 712         if (!ret) {
 713                 /* We have a Vendor InfoFrame, populate it to the display */
 714                 args.pwr.vendor_infoframe_length
 715                         = hdmi_infoframe_pack(&vendor_frame,
 716                                               args.infoframes
 717                                               + args.pwr.avi_infoframe_length,
 718                                               17);
 719         }
 720
 721         max_ac_packet  = mode->htotal - mode->hdisplay;
 722         max_ac_packet -= args.pwr.rekey;
 723         max_ac_packet -= 18; /* constant from tegra */
 724         args.pwr.max_ac_packet = max_ac_packet / 32;
 725
 726         if (hdmi->scdc.scrambling.supported) {
 727                 high_tmds_clock_ratio = mode->clock > 340000;
 728                 scrambling = high_tmds_clock_ratio ||
 729                         hdmi->scdc.scrambling.low_rates;
 730         }
 731
 732         args.pwr.scdc =
 733                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 734                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 735
 736         size = sizeof(args.base)
 737                 + sizeof(args.pwr)
 738                 + args.pwr.avi_infoframe_length
 739                 + args.pwr.vendor_infoframe_length;
 740         nvif_mthd(&disp->disp->object, 0, &args, size);
 741
 742         nv50_audio_enable(encoder, mode);
 743
 744         /* If SCDC is supported by the downstream monitor, update
 745          * divider / scrambling settings to what we programmed above.
 746          */
 747         if (!hdmi->scdc.scrambling.supported)
 748                 return;
 749
 750         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 751         if (ret < 0) {
 752                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 753                 return;
 754         }
 755         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 756         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 757         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 758         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 759         if (ret < 0)
 760                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 761                          config, ret);
 762 }
 763
 764 /******************************************************************************
 765  * MST
 766  *****************************************************************************/
 767 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 768 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 769 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 770
 771 struct nv50_mstm {
 772         struct nouveau_encoder *outp;
 773
 774         struct drm_dp_mst_topology_mgr mgr;
 775
 776         bool modified;
 777         bool disabled;
 778         int links;
 779 };
 780
 781 struct nv50_mstc {
 782         struct nv50_mstm *mstm;
 783         struct drm_dp_mst_port *port;
 784         struct drm_connector connector;
 785
 786         struct drm_display_mode *native;
 787         struct edid *edid;
 788 };
 789
 790 struct nv50_msto {
 791         struct drm_encoder encoder;
 792
 793         struct nv50_head *head;
 794         struct nv50_mstc *mstc;
 795         bool disabled;
 796 };
 797
 798 static struct drm_dp_payload *
 799 nv50_msto_payload(struct nv50_msto *msto)
 800 {
 801         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 802         struct nv50_mstc *mstc = msto->mstc;
 803         struct nv50_mstm *mstm = mstc->mstm;
 804         int vcpi = mstc->port->vcpi.vcpi, i;
 805
 806         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 807
 808         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 809         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 810                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 811                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 812                           mstm->outp->base.base.name, i, payload->vcpi,
 813                           payload->start_slot, payload->num_slots);
 814         }
 815
 816         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 817                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 818                 if (payload->vcpi == vcpi)
 819                         return payload;
 820         }
 821
 822         return NULL;
 823 }
 824
 825 static void
 826 nv50_msto_cleanup(struct nv50_msto *msto)
 827 {
 828         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 829         struct nv50_mstc *mstc = msto->mstc;
 830         struct nv50_mstm *mstm = mstc->mstm;
 831
 832         if (!msto->disabled)
 833                 return;
 834
 835         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 836
 837         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 838
 839         msto->mstc = NULL;
 840         msto->disabled = false;
 841 }
 842
 843 static void
 844 nv50_msto_prepare(struct nv50_msto *msto)
 845 {
 846         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 847         struct nv50_mstc *mstc = msto->mstc;
 848         struct nv50_mstm *mstm = mstc->mstm;
 849         struct {
 850                 struct nv50_disp_mthd_v1 base;
 851                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 852         } args = {
 853                 .base.version = 1,
 854                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 855                 .base.hasht  = mstm->outp->dcb->hasht,
 856                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 857                                (0x0100 << msto->head->base.index),
 858         };
 859
 860         mutex_lock(&mstm->mgr.payload_lock);
 861
 862         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 863         if (mstc->port->vcpi.vcpi > 0) {
 864                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 865                 if (payload) {
 866                         args.vcpi.start_slot = payload->start_slot;
 867                         args.vcpi.num_slots = payload->num_slots;
 868                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 869                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 870                 }
 871         }
 872
 873         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 874                   msto->encoder.name, msto->head->base.base.name,
 875                   args.vcpi.start_slot, args.vcpi.num_slots,
 876                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 877
 878         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 879         mutex_unlock(&mstm->mgr.payload_lock);
 880 }
 881
 882 static int
 883 nv50_msto_atomic_check(struct drm_encoder *encoder,
 884                        struct drm_crtc_state *crtc_state,
 885                        struct drm_connector_state *conn_state)
 886 {
 887         struct drm_atomic_state *state = crtc_state->state;
 888         struct drm_connector *connector = conn_state->connector;
 889         struct nv50_mstc *mstc = nv50_mstc(connector);
 890         struct nv50_mstm *mstm = mstc->mstm;
 891         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 892         int slots;
 893         int ret;
 894
 895         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 896                                           mstc->native);
 897         if (ret)
 898                 return ret;
 899
 900         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 901                 return 0;
 902
 903         /*
 904          * When restoring duplicated states, we need to make sure that the bw
 905          * remains the same and avoid recalculating it, as the connector's bpc
 906          * may have changed after the state was duplicated
 907          */
 908         if (!state->duplicated) {
 909                 const int clock = crtc_state->adjusted_mode.clock;
 910
 911                 /*
 912                  * XXX: Since we don't use HDR in userspace quite yet, limit
 913                  * the bpc to 8 to save bandwidth on the topology. In the
 914                  * future, we'll want to properly fix this by dynamically
 915                  * selecting the highest possible bpc that would fit in the
 916                  * topology
 917                  */
 918                 asyh->or.bpc = min(connector->display_info.bpc, 8U);
 919                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, false);
 920         }
 921
 922         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 923                                               asyh->dp.pbn, 0);
 924         if (slots < 0)
 925                 return slots;
 926
 927         asyh->dp.tu = slots;
 928
 929         return 0;
 930 }
 931
 932 static u8
 933 nv50_dp_bpc_to_depth(unsigned int bpc)
 934 {
 935         switch (bpc) {
 936         case  6: return 0x2;
 937         case  8: return 0x5;
 938         case 10: /* fall-through */
 939         default: return 0x6;
 940         }
 941 }
 942
 943 static void
 944 nv50_msto_enable(struct drm_encoder *encoder)
 945 {
 946         struct nv50_head *head = nv50_head(encoder->crtc);
 947         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 948         struct nv50_msto *msto = nv50_msto(encoder);
 949         struct nv50_mstc *mstc = NULL;
 950         struct nv50_mstm *mstm = NULL;
 951         struct drm_connector *connector;
 952         struct drm_connector_list_iter conn_iter;
 953         u8 proto;
 954         bool r;
 955
 956         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 957         drm_for_each_connector_iter(connector, &conn_iter) {
 958                 if (connector->state->best_encoder == &msto->encoder) {
 959                         mstc = nv50_mstc(connector);
 960                         mstm = mstc->mstm;
 961                         break;
 962                 }
 963         }
 964         drm_connector_list_iter_end(&conn_iter);
 965
 966         if (WARN_ON(!mstc))
 967                 return;
 968
 969         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 970                                      armh->dp.tu);
 971         if (!r)
 972                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 973
 974         if (!mstm->links++)
 975                 nv50_outp_acquire(mstm->outp);
 976
 977         if (mstm->outp->link & 1)
 978                 proto = 0x8;
 979         else
 980                 proto = 0x9;
 981
 982         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 983                            nv50_dp_bpc_to_depth(armh->or.bpc));
 984
 985         msto->mstc = mstc;
 986         mstm->modified = true;
 987 }
 988
 989 static void
 990 nv50_msto_disable(struct drm_encoder *encoder)
 991 {
 992         struct nv50_msto *msto = nv50_msto(encoder);
 993         struct nv50_mstc *mstc = msto->mstc;
 994         struct nv50_mstm *mstm = mstc->mstm;
 995
 996         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 997
 998         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 999         mstm->modified = true;
1000         if (!--mstm->links)
1001                 mstm->disabled = true;
1002         msto->disabled = true;
1003 }
1004
1005 static const struct drm_encoder_helper_funcs
1006 nv50_msto_help = {
1007         .disable = nv50_msto_disable,
1008         .enable = nv50_msto_enable,
1009         .atomic_check = nv50_msto_atomic_check,
1010 };
1011
1012 static void
1013 nv50_msto_destroy(struct drm_encoder *encoder)
1014 {
1015         struct nv50_msto *msto = nv50_msto(encoder);
1016         drm_encoder_cleanup(&msto->encoder);
1017         kfree(msto);
1018 }
1019
1020 static const struct drm_encoder_funcs
1021 nv50_msto = {
1022         .destroy = nv50_msto_destroy,
1023 };
1024
1025 static struct nv50_msto *
1026 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1027 {
1028         struct nv50_msto *msto;
1029         int ret;
1030
1031         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1032         if (!msto)
1033                 return ERR_PTR(-ENOMEM);
1034
1035         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1036                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1037         if (ret) {
1038                 kfree(msto);
1039                 return ERR_PTR(ret);
1040         }
1041
1042         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1043         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1044         msto->head = head;
1045         return msto;
1046 }
1047
1048 static struct drm_encoder *
1049 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1050                               struct drm_connector_state *connector_state)
1051 {
1052         struct nv50_mstc *mstc = nv50_mstc(connector);
1053         struct drm_crtc *crtc = connector_state->crtc;
1054
1055         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1056                 return NULL;
1057
1058         return &nv50_head(crtc)->msto->encoder;
1059 }
1060
1061 static enum drm_mode_status
1062 nv50_mstc_mode_valid(struct drm_connector *connector,
1063                      struct drm_display_mode *mode)
1064 {
1065         return MODE_OK;
1066 }
1067
1068 static int
1069 nv50_mstc_get_modes(struct drm_connector *connector)
1070 {
1071         struct nv50_mstc *mstc = nv50_mstc(connector);
1072         int ret = 0;
1073
1074         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1075         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1076         if (mstc->edid)
1077                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1078
1079         if (!mstc->connector.display_info.bpc)
1080                 mstc->connector.display_info.bpc = 8;
1081
1082         if (mstc->native)
1083                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1084         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1085         return ret;
1086 }
1087
1088 static int
1089 nv50_mstc_atomic_check(struct drm_connector *connector,
1090                        struct drm_atomic_state *state)
1091 {
1092         struct nv50_mstc *mstc = nv50_mstc(connector);
1093         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1094         struct drm_connector_state *new_conn_state =
1095                 drm_atomic_get_new_connector_state(state, connector);
1096         struct drm_connector_state *old_conn_state =
1097                 drm_atomic_get_old_connector_state(state, connector);
1098         struct drm_crtc_state *crtc_state;
1099         struct drm_crtc *new_crtc = new_conn_state->crtc;
1100
1101         if (!old_conn_state->crtc)
1102                 return 0;
1103
1104         /* We only want to free VCPI if this state disables the CRTC on this
1105          * connector
1106          */
1107         if (new_crtc) {
1108                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1109
1110                 if (!crtc_state ||
1111                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1112                     crtc_state->enable)
1113                         return 0;
1114         }
1115
1116         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1117 }
1118
1119 static int
1120 nv50_mstc_detect(struct drm_connector *connector,
1121                  struct drm_modeset_acquire_ctx *ctx, bool force)
1122 {
1123         struct nv50_mstc *mstc = nv50_mstc(connector);
1124         int ret;
1125
1126         if (drm_connector_is_unregistered(connector))
1127                 return connector_status_disconnected;
1128
1129         ret = pm_runtime_get_sync(connector->dev->dev);
1130         if (ret < 0 && ret != -EACCES)
1131                 return connector_status_disconnected;
1132
1133         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1134                                      mstc->port);
1135
1136         pm_runtime_mark_last_busy(connector->dev->dev);
1137         pm_runtime_put_autosuspend(connector->dev->dev);
1138         return ret;
1139 }
1140
1141 static const struct drm_connector_helper_funcs
1142 nv50_mstc_help = {
1143         .get_modes = nv50_mstc_get_modes,
1144         .mode_valid = nv50_mstc_mode_valid,
1145         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1146         .atomic_check = nv50_mstc_atomic_check,
1147         .detect_ctx = nv50_mstc_detect,
1148 };
1149
1150 static void
1151 nv50_mstc_destroy(struct drm_connector *connector)
1152 {
1153         struct nv50_mstc *mstc = nv50_mstc(connector);
1154
1155         drm_connector_cleanup(&mstc->connector);
1156         drm_dp_mst_put_port_malloc(mstc->port);
1157
1158         kfree(mstc);
1159 }
1160
1161 static const struct drm_connector_funcs
1162 nv50_mstc = {
1163         .reset = nouveau_conn_reset,
1164         .fill_modes = drm_helper_probe_single_connector_modes,
1165         .destroy = nv50_mstc_destroy,
1166         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1167         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1168         .atomic_set_property = nouveau_conn_atomic_set_property,
1169         .atomic_get_property = nouveau_conn_atomic_get_property,
1170 };
1171
1172 static int
1173 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1174               const char *path, struct nv50_mstc **pmstc)
1175 {
1176         struct drm_device *dev = mstm->outp->base.base.dev;
1177         struct drm_crtc *crtc;
1178         struct nv50_mstc *mstc;
1179         int ret;
1180
1181         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1182                 return -ENOMEM;
1183         mstc->mstm = mstm;
1184         mstc->port = port;
1185
1186         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1187                                  DRM_MODE_CONNECTOR_DisplayPort);
1188         if (ret) {
1189                 kfree(*pmstc);
1190                 *pmstc = NULL;
1191                 return ret;
1192         }
1193
1194         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1195
1196         mstc->connector.funcs->reset(&mstc->connector);
1197         nouveau_conn_attach_properties(&mstc->connector);
1198
1199         drm_for_each_crtc(crtc, dev) {
1200                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1201                         continue;
1202
1203                 drm_connector_attach_encoder(&mstc->connector,
1204                                              &nv50_head(crtc)->msto->encoder);
1205         }
1206
1207         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1208         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1209         drm_connector_set_path_property(&mstc->connector, path);
1210         drm_dp_mst_get_port_malloc(port);
1211         return 0;
1212 }
1213
1214 static void
1215 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1216 {
1217         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1218         struct drm_encoder *encoder;
1219         int ret;
1220
1221         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1222         ret = drm_dp_check_act_status(&mstm->mgr);
1223
1224         ret = drm_dp_update_payload_part2(&mstm->mgr);
1225
1226         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1227                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1228                         struct nv50_msto *msto = nv50_msto(encoder);
1229                         struct nv50_mstc *mstc = msto->mstc;
1230                         if (mstc && mstc->mstm == mstm)
1231                                 nv50_msto_cleanup(msto);
1232                 }
1233         }
1234
1235         mstm->modified = false;
1236 }
1237
1238 static void
1239 nv50_mstm_prepare(struct nv50_mstm *mstm)
1240 {
1241         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1242         struct drm_encoder *encoder;
1243         int ret;
1244
1245         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1246         ret = drm_dp_update_payload_part1(&mstm->mgr);
1247
1248         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1249                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1250                         struct nv50_msto *msto = nv50_msto(encoder);
1251                         struct nv50_mstc *mstc = msto->mstc;
1252                         if (mstc && mstc->mstm == mstm)
1253                                 nv50_msto_prepare(msto);
1254                 }
1255         }
1256
1257         if (mstm->disabled) {
1258                 if (!mstm->links)
1259                         nv50_outp_release(mstm->outp);
1260                 mstm->disabled = false;
1261         }
1262 }
1263
1264 static struct drm_connector *
1265 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1266                         struct drm_dp_mst_port *port, const char *path)
1267 {
1268         struct nv50_mstm *mstm = nv50_mstm(mgr);
1269         struct nv50_mstc *mstc;
1270         int ret;
1271
1272         ret = nv50_mstc_new(mstm, port, path, &mstc);
1273         if (ret)
1274                 return NULL;
1275
1276         return &mstc->connector;
1277 }
1278
1279 static const struct drm_dp_mst_topology_cbs
1280 nv50_mstm = {
1281         .add_connector = nv50_mstm_add_connector,
1282 };
1283
1284 void
1285 nv50_mstm_service(struct nv50_mstm *mstm)
1286 {
1287         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1288         bool handled = true;
1289         int ret;
1290         u8 esi[8] = {};
1291
1292         if (!aux)
1293                 return;
1294
1295         while (handled) {
1296                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1297                 if (ret != 8) {
1298                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1299                         return;
1300                 }
1301
1302                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1303                 if (!handled)
1304                         break;
1305
1306                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1307         }
1308 }
1309
1310 void
1311 nv50_mstm_remove(struct nv50_mstm *mstm)
1312 {
1313         if (mstm)
1314                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1315 }
1316
1317 static int
1318 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1319 {
1320         struct nouveau_encoder *outp = mstm->outp;
1321         struct {
1322                 struct nv50_disp_mthd_v1 base;
1323                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1324         } args = {
1325                 .base.version = 1,
1326                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1327                 .base.hasht = outp->dcb->hasht,
1328                 .base.hashm = outp->dcb->hashm,
1329                 .mst.state = state,
1330         };
1331         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1332         struct nvif_object *disp = &drm->display->disp.object;
1333         int ret;
1334
1335         if (dpcd >= 0x12) {
1336                 /* Even if we're enabling MST, start with disabling the
1337                  * branching unit to clear any sink-side MST topology state
1338                  * that wasn't set by us
1339                  */
1340                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1341                 if (ret < 0)
1342                         return ret;
1343
1344                 if (state) {
1345                         /* Now, start initializing */
1346                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1347                                                  DP_MST_EN);
1348                         if (ret < 0)
1349                                 return ret;
1350                 }
1351         }
1352
1353         return nvif_mthd(disp, 0, &args, sizeof(args));
1354 }
1355
1356 int
1357 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1358 {
1359         struct drm_dp_aux *aux;
1360         int ret;
1361         bool old_state, new_state;
1362         u8 mstm_ctrl;
1363
1364         if (!mstm)
1365                 return 0;
1366
1367         mutex_lock(&mstm->mgr.lock);
1368
1369         old_state = mstm->mgr.mst_state;
1370         new_state = old_state;
1371         aux = mstm->mgr.aux;
1372
1373         if (old_state) {
1374                 /* Just check that the MST hub is still as we expect it */
1375                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1376                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1377                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1378                         new_state = false;
1379                 }
1380         } else if (dpcd[0] >= 0x12) {
1381                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1382                 if (ret < 0)
1383                         goto probe_error;
1384
1385                 if (!(dpcd[1] & DP_MST_CAP))
1386                         dpcd[0] = 0x11;
1387                 else
1388                         new_state = allow;
1389         }
1390
1391         if (new_state == old_state) {
1392                 mutex_unlock(&mstm->mgr.lock);
1393                 return new_state;
1394         }
1395
1396         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1397         if (ret)
1398                 goto probe_error;
1399
1400         mutex_unlock(&mstm->mgr.lock);
1401
1402         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1403         if (ret)
1404                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1405
1406         return new_state;
1407
1408 probe_error:
1409         mutex_unlock(&mstm->mgr.lock);
1410         return ret;
1411 }
1412
1413 static void
1414 nv50_mstm_fini(struct nv50_mstm *mstm)
1415 {
1416         if (mstm && mstm->mgr.mst_state)
1417                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1418 }
1419
1420 static void
1421 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1422 {
1423         int ret;
1424
1425         if (!mstm || !mstm->mgr.mst_state)
1426                 return;
1427
1428         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1429         if (ret == -1) {
1430                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1431                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1432         }
1433 }
1434
1435 static void
1436 nv50_mstm_del(struct nv50_mstm **pmstm)
1437 {
1438         struct nv50_mstm *mstm = *pmstm;
1439         if (mstm) {
1440                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1441                 kfree(*pmstm);
1442                 *pmstm = NULL;
1443         }
1444 }
1445
1446 static int
1447 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1448               int conn_base_id, struct nv50_mstm **pmstm)
1449 {
1450         const int max_payloads = hweight8(outp->dcb->heads);
1451         struct drm_device *dev = outp->base.base.dev;
1452         struct nv50_mstm *mstm;
1453         int ret;
1454         u8 dpcd;
1455
1456         /* This is a workaround for some monitors not functioning
1457          * correctly in MST mode on initial module load.  I think
1458          * some bad interaction with the VBIOS may be responsible.
1459          *
1460          * A good ol' off and on again seems to work here ;)
1461          */
1462         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1463         if (ret >= 0 && dpcd >= 0x12)
1464                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1465
1466         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1467                 return -ENOMEM;
1468         mstm->outp = outp;
1469         mstm->mgr.cbs = &nv50_mstm;
1470
1471         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1472                                            max_payloads, conn_base_id);
1473         if (ret)
1474                 return ret;
1475
1476         return 0;
1477 }
1478
1479 /******************************************************************************
1480  * SOR
1481  *****************************************************************************/
1482 static void
1483 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1484                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1485 {
1486         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1487         struct nv50_core *core = disp->core;
1488
1489         if (!asyh) {
1490                 nv_encoder->ctrl &= ~BIT(head);
1491                 if (!(nv_encoder->ctrl & 0x0000000f))
1492                         nv_encoder->ctrl = 0;
1493         } else {
1494                 nv_encoder->ctrl |= proto << 8;
1495                 nv_encoder->ctrl |= BIT(head);
1496                 asyh->or.depth = depth;
1497         }
1498
1499         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1500 }
1501
1502 static void
1503 nv50_sor_disable(struct drm_encoder *encoder)
1504 {
1505         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1506         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1507
1508         nv_encoder->crtc = NULL;
1509
1510         if (nv_crtc) {
1511                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1512                 u8 pwr;
1513
1514                 if (aux) {
1515                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1516                         if (ret == 0) {
1517                                 pwr &= ~DP_SET_POWER_MASK;
1518                                 pwr |=  DP_SET_POWER_D3;
1519                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1520                         }
1521                 }
1522
1523                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1524                 nv50_audio_disable(encoder, nv_crtc);
1525                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1526                 nv50_outp_release(nv_encoder);
1527         }
1528 }
1529
1530 static void
1531 nv50_sor_enable(struct drm_encoder *encoder)
1532 {
1533         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1534         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1535         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1536         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1537         struct {
1538                 struct nv50_disp_mthd_v1 base;
1539                 struct nv50_disp_sor_lvds_script_v0 lvds;
1540         } lvds = {
1541                 .base.version = 1,
1542                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1543                 .base.hasht   = nv_encoder->dcb->hasht,
1544                 .base.hashm   = nv_encoder->dcb->hashm,
1545         };
1546         struct nv50_disp *disp = nv50_disp(encoder->dev);
1547         struct drm_device *dev = encoder->dev;
1548         struct nouveau_drm *drm = nouveau_drm(dev);
1549         struct nouveau_connector *nv_connector;
1550         struct nvbios *bios = &drm->vbios;
1551         u8 proto = 0xf;
1552         u8 depth = 0x0;
1553
1554         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1555         nv_encoder->crtc = encoder->crtc;
1556         nv50_outp_acquire(nv_encoder);
1557
1558         switch (nv_encoder->dcb->type) {
1559         case DCB_OUTPUT_TMDS:
1560                 if (nv_encoder->link & 1) {
1561                         proto = 0x1;
1562                         /* Only enable dual-link if:
1563                          *  - Need to (i.e. rate > 165MHz)
1564                          *  - DCB says we can
1565                          *  - Not an HDMI monitor, since there's no dual-link
1566                          *    on HDMI.
1567                          */
1568                         if (mode->clock >= 165000 &&
1569                             nv_encoder->dcb->duallink_possible &&
1570                             !drm_detect_hdmi_monitor(nv_connector->edid))
1571                                 proto |= 0x4;
1572                 } else {
1573                         proto = 0x2;
1574                 }
1575
1576                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1577                 break;
1578         case DCB_OUTPUT_LVDS:
1579                 proto = 0x0;
1580
1581                 if (bios->fp_no_ddc) {
1582                         if (bios->fp.dual_link)
1583                                 lvds.lvds.script |= 0x0100;
1584                         if (bios->fp.if_is_24bit)
1585                                 lvds.lvds.script |= 0x0200;
1586                 } else {
1587                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1588                                 if (((u8 *)nv_connector->edid)[121] == 2)
1589                                         lvds.lvds.script |= 0x0100;
1590                         } else
1591                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1592                                 lvds.lvds.script |= 0x0100;
1593                         }
1594
1595                         if (lvds.lvds.script & 0x0100) {
1596                                 if (bios->fp.strapless_is_24bit & 2)
1597                                         lvds.lvds.script |= 0x0200;
1598                         } else {
1599                                 if (bios->fp.strapless_is_24bit & 1)
1600                                         lvds.lvds.script |= 0x0200;
1601                         }
1602
1603                         if (asyh->or.bpc == 8)
1604                                 lvds.lvds.script |= 0x0200;
1605                 }
1606
1607                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1608                 break;
1609         case DCB_OUTPUT_DP:
1610                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1611
1612                 if (nv_encoder->link & 1)
1613                         proto = 0x8;
1614                 else
1615                         proto = 0x9;
1616
1617                 nv50_audio_enable(encoder, mode);
1618                 break;
1619         default:
1620                 BUG();
1621                 break;
1622         }
1623
1624         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1625 }
1626
1627 static const struct drm_encoder_helper_funcs
1628 nv50_sor_help = {
1629         .atomic_check = nv50_outp_atomic_check,
1630         .enable = nv50_sor_enable,
1631         .disable = nv50_sor_disable,
1632 };
1633
1634 static void
1635 nv50_sor_destroy(struct drm_encoder *encoder)
1636 {
1637         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1638         nv50_mstm_del(&nv_encoder->dp.mstm);
1639         drm_encoder_cleanup(encoder);
1640         kfree(encoder);
1641 }
1642
1643 static const struct drm_encoder_funcs
1644 nv50_sor_func = {
1645         .destroy = nv50_sor_destroy,
1646 };
1647
1648 static bool nv50_has_mst(struct nouveau_drm *drm)
1649 {
1650         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1651         u32 data;
1652         u8 ver, hdr, cnt, len;
1653
1654         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1655         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1656 }
1657
1658 static int
1659 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1660 {
1661         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1662         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1663         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1664         struct nouveau_encoder *nv_encoder;
1665         struct drm_encoder *encoder;
1666         struct nv50_disp *disp = nv50_disp(connector->dev);
1667         int type, ret;
1668
1669         switch (dcbe->type) {
1670         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1671         case DCB_OUTPUT_TMDS:
1672         case DCB_OUTPUT_DP:
1673         default:
1674                 type = DRM_MODE_ENCODER_TMDS;
1675                 break;
1676         }
1677
1678         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1679         if (!nv_encoder)
1680                 return -ENOMEM;
1681         nv_encoder->dcb = dcbe;
1682         nv_encoder->update = nv50_sor_update;
1683
1684         encoder = to_drm_encoder(nv_encoder);
1685         encoder->possible_crtcs = dcbe->heads;
1686         encoder->possible_clones = 0;
1687         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1688                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1689         drm_encoder_helper_add(encoder, &nv50_sor_help);
1690
1691         drm_connector_attach_encoder(connector, encoder);
1692
1693         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1694
1695         if (dcbe->type == DCB_OUTPUT_DP) {
1696                 struct nvkm_i2c_aux *aux =
1697                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1698
1699                 if (aux) {
1700                         if (disp->disp->object.oclass < GF110_DISP) {
1701                                 /* HW has no support for address-only
1702                                  * transactions, so we're required to
1703                                  * use custom I2C-over-AUX code.
1704                                  */
1705                                 nv_encoder->i2c = &aux->i2c;
1706                         } else {
1707                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1708                         }
1709                         nv_encoder->aux = aux;
1710                 }
1711
1712                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1713                     nv50_has_mst(drm)) {
1714                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1715                                             16, nv_connector->base.base.id,
1716                                             &nv_encoder->dp.mstm);
1717                         if (ret)
1718                                 return ret;
1719                 }
1720         } else {
1721                 struct nvkm_i2c_bus *bus =
1722                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1723                 if (bus)
1724                         nv_encoder->i2c = &bus->i2c;
1725         }
1726
1727         return 0;
1728 }
1729
1730 /******************************************************************************
1731  * PIOR
1732  *****************************************************************************/
1733 static int
1734 nv50_pior_atomic_check(struct drm_encoder *encoder,
1735                        struct drm_crtc_state *crtc_state,
1736                        struct drm_connector_state *conn_state)
1737 {
1738         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1739         if (ret)
1740                 return ret;
1741         crtc_state->adjusted_mode.clock *= 2;
1742         return 0;
1743 }
1744
1745 static void
1746 nv50_pior_disable(struct drm_encoder *encoder)
1747 {
1748         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1749         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1750         if (nv_encoder->crtc)
1751                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1752         nv_encoder->crtc = NULL;
1753         nv50_outp_release(nv_encoder);
1754 }
1755
1756 static void
1757 nv50_pior_enable(struct drm_encoder *encoder)
1758 {
1759         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1760         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1761         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1762         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1763         u8 owner = 1 << nv_crtc->index;
1764         u8 proto;
1765
1766         nv50_outp_acquire(nv_encoder);
1767
1768         switch (asyh->or.bpc) {
1769         case 10: asyh->or.depth = 0x6; break;
1770         case  8: asyh->or.depth = 0x5; break;
1771         case  6: asyh->or.depth = 0x2; break;
1772         default: asyh->or.depth = 0x0; break;
1773         }
1774
1775         switch (nv_encoder->dcb->type) {
1776         case DCB_OUTPUT_TMDS:
1777         case DCB_OUTPUT_DP:
1778                 proto = 0x0;
1779                 break;
1780         default:
1781                 BUG();
1782                 break;
1783         }
1784
1785         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1786         nv_encoder->crtc = encoder->crtc;
1787 }
1788
1789 static const struct drm_encoder_helper_funcs
1790 nv50_pior_help = {
1791         .atomic_check = nv50_pior_atomic_check,
1792         .enable = nv50_pior_enable,
1793         .disable = nv50_pior_disable,
1794 };
1795
1796 static void
1797 nv50_pior_destroy(struct drm_encoder *encoder)
1798 {
1799         drm_encoder_cleanup(encoder);
1800         kfree(encoder);
1801 }
1802
1803 static const struct drm_encoder_funcs
1804 nv50_pior_func = {
1805         .destroy = nv50_pior_destroy,
1806 };
1807
1808 static int
1809 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1810 {
1811         struct drm_device *dev = connector->dev;
1812         struct nouveau_drm *drm = nouveau_drm(dev);
1813         struct nv50_disp *disp = nv50_disp(dev);
1814         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1815         struct nvkm_i2c_bus *bus = NULL;
1816         struct nvkm_i2c_aux *aux = NULL;
1817         struct i2c_adapter *ddc;
1818         struct nouveau_encoder *nv_encoder;
1819         struct drm_encoder *encoder;
1820         int type;
1821
1822         switch (dcbe->type) {
1823         case DCB_OUTPUT_TMDS:
1824                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1825                 ddc  = bus ? &bus->i2c : NULL;
1826                 type = DRM_MODE_ENCODER_TMDS;
1827                 break;
1828         case DCB_OUTPUT_DP:
1829                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1830                 ddc  = aux ? &aux->i2c : NULL;
1831                 type = DRM_MODE_ENCODER_TMDS;
1832                 break;
1833         default:
1834                 return -ENODEV;
1835         }
1836
1837         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1838         if (!nv_encoder)
1839                 return -ENOMEM;
1840         nv_encoder->dcb = dcbe;
1841         nv_encoder->i2c = ddc;
1842         nv_encoder->aux = aux;
1843
1844         encoder = to_drm_encoder(nv_encoder);
1845         encoder->possible_crtcs = dcbe->heads;
1846         encoder->possible_clones = 0;
1847         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1848                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1849         drm_encoder_helper_add(encoder, &nv50_pior_help);
1850
1851         drm_connector_attach_encoder(connector, encoder);
1852
1853         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1854
1855         return 0;
1856 }
1857
1858 /******************************************************************************
1859  * Atomic
1860  *****************************************************************************/
1861
1862 static void
1863 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1864 {
1865         struct nouveau_drm *drm = nouveau_drm(state->dev);
1866         struct nv50_disp *disp = nv50_disp(drm->dev);
1867         struct nv50_core *core = disp->core;
1868         struct nv50_mstm *mstm;
1869         struct drm_encoder *encoder;
1870
1871         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1872
1873         drm_for_each_encoder(encoder, drm->dev) {
1874                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1875                         mstm = nouveau_encoder(encoder)->dp.mstm;
1876                         if (mstm && mstm->modified)
1877                                 nv50_mstm_prepare(mstm);
1878                 }
1879         }
1880
1881         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1882         core->func->update(core, interlock, true);
1883         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1884                                        disp->core->chan.base.device))
1885                 NV_ERROR(drm, "core notifier timeout\n");
1886
1887         drm_for_each_encoder(encoder, drm->dev) {
1888                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1889                         mstm = nouveau_encoder(encoder)->dp.mstm;
1890                         if (mstm && mstm->modified)
1891                                 nv50_mstm_cleanup(mstm);
1892                 }
1893         }
1894 }
1895
1896 static void
1897 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1898 {
1899         struct drm_plane_state *new_plane_state;
1900         struct drm_plane *plane;
1901         int i;
1902
1903         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1904                 struct nv50_wndw *wndw = nv50_wndw(plane);
1905                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1906                         if (wndw->func->update)
1907                                 wndw->func->update(wndw, interlock);
1908                 }
1909         }
1910 }
1911
1912 static void
1913 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1914 {
1915         struct drm_device *dev = state->dev;
1916         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1917         struct drm_crtc *crtc;
1918         struct drm_plane_state *new_plane_state;
1919         struct drm_plane *plane;
1920         struct nouveau_drm *drm = nouveau_drm(dev);
1921         struct nv50_disp *disp = nv50_disp(dev);
1922         struct nv50_atom *atom = nv50_atom(state);
1923         struct nv50_core *core = disp->core;
1924         struct nv50_outp_atom *outp, *outt;
1925         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1926         int i;
1927
1928         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1929         drm_atomic_helper_wait_for_fences(dev, state, false);
1930         drm_atomic_helper_wait_for_dependencies(state);
1931         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1932
1933         if (atom->lock_core)
1934                 mutex_lock(&disp->mutex);
1935
1936         /* Disable head(s). */
1937         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1938                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1939                 struct nv50_head *head = nv50_head(crtc);
1940
1941                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1942                           asyh->clr.mask, asyh->set.mask);
1943
1944                 if (old_crtc_state->active && !new_crtc_state->active) {
1945                         pm_runtime_put_noidle(dev->dev);
1946                         drm_crtc_vblank_off(crtc);
1947                 }
1948
1949                 if (asyh->clr.mask) {
1950                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1951                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1952                 }
1953         }
1954
1955         /* Disable plane(s). */
1956         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1957                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1958                 struct nv50_wndw *wndw = nv50_wndw(plane);
1959
1960                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1961                           asyw->clr.mask, asyw->set.mask);
1962                 if (!asyw->clr.mask)
1963                         continue;
1964
1965                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1966         }
1967
1968         /* Disable output path(s). */
1969         list_for_each_entry(outp, &atom->outp, head) {
1970                 const struct drm_encoder_helper_funcs *help;
1971                 struct drm_encoder *encoder;
1972
1973                 encoder = outp->encoder;
1974                 help = encoder->helper_private;
1975
1976                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1977                           outp->clr.mask, outp->set.mask);
1978
1979                 if (outp->clr.mask) {
1980                         help->disable(encoder);
1981                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1982                         if (outp->flush_disable) {
1983                                 nv50_disp_atomic_commit_wndw(state, interlock);
1984                                 nv50_disp_atomic_commit_core(state, interlock);
1985                                 memset(interlock, 0x00, sizeof(interlock));
1986                         }
1987                 }
1988         }
1989
1990         /* Flush disable. */
1991         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1992                 if (atom->flush_disable) {
1993                         nv50_disp_atomic_commit_wndw(state, interlock);
1994                         nv50_disp_atomic_commit_core(state, interlock);
1995                         memset(interlock, 0x00, sizeof(interlock));
1996                 }
1997         }
1998
1999         /* Update output path(s). */
2000         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2001                 const struct drm_encoder_helper_funcs *help;
2002                 struct drm_encoder *encoder;
2003
2004                 encoder = outp->encoder;
2005                 help = encoder->helper_private;
2006
2007                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2008                           outp->set.mask, outp->clr.mask);
2009
2010                 if (outp->set.mask) {
2011                         help->enable(encoder);
2012                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2013                 }
2014
2015                 list_del(&outp->head);
2016                 kfree(outp);
2017         }
2018
2019         /* Update head(s). */
2020         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2021                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2022                 struct nv50_head *head = nv50_head(crtc);
2023
2024                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2025                           asyh->set.mask, asyh->clr.mask);
2026
2027                 if (asyh->set.mask) {
2028                         nv50_head_flush_set(head, asyh);
2029                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2030                 }
2031
2032                 if (new_crtc_state->active) {
2033                         if (!old_crtc_state->active) {
2034                                 drm_crtc_vblank_on(crtc);
2035                                 pm_runtime_get_noresume(dev->dev);
2036                         }
2037                         if (new_crtc_state->event)
2038                                 drm_crtc_vblank_get(crtc);
2039                 }
2040         }
2041
2042         /* Update window->head assignment.
2043          *
2044          * This has to happen in an update that's not interlocked with
2045          * any window channels to avoid hitting HW error checks.
2046          *
2047          *TODO: Proper handling of window ownership (Turing apparently
2048          *      supports non-fixed mappings).
2049          */
2050         if (core->assign_windows) {
2051                 core->func->wndw.owner(core);
2052                 core->func->update(core, interlock, false);
2053                 core->assign_windows = false;
2054                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2055         }
2056
2057         /* Update plane(s). */
2058         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2059                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2060                 struct nv50_wndw *wndw = nv50_wndw(plane);
2061
2062                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2063                           asyw->set.mask, asyw->clr.mask);
2064                 if ( !asyw->set.mask &&
2065                     (!asyw->clr.mask || atom->flush_disable))
2066                         continue;
2067
2068                 nv50_wndw_flush_set(wndw, interlock, asyw);
2069         }
2070
2071         /* Flush update. */
2072         nv50_disp_atomic_commit_wndw(state, interlock);
2073
2074         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2075                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2076                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2077                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2078                     !atom->state.legacy_cursor_update)
2079                         nv50_disp_atomic_commit_core(state, interlock);
2080                 else
2081                         disp->core->func->update(disp->core, interlock, false);
2082         }
2083
2084         if (atom->lock_core)
2085                 mutex_unlock(&disp->mutex);
2086
2087         /* Wait for HW to signal completion. */
2088         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2089                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2090                 struct nv50_wndw *wndw = nv50_wndw(plane);
2091                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2092                 if (ret)
2093                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2094         }
2095
2096         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2097                 if (new_crtc_state->event) {
2098                         unsigned long flags;
2099                         /* Get correct count/ts if racing with vblank irq */
2100                         if (new_crtc_state->active)
2101                                 drm_crtc_accurate_vblank_count(crtc);
2102                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2103                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2104                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2105
2106                         new_crtc_state->event = NULL;
2107                         if (new_crtc_state->active)
2108                                 drm_crtc_vblank_put(crtc);
2109                 }
2110         }
2111
2112         drm_atomic_helper_commit_hw_done(state);
2113         drm_atomic_helper_cleanup_planes(dev, state);
2114         drm_atomic_helper_commit_cleanup_done(state);
2115         drm_atomic_state_put(state);
2116
2117         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2118         pm_runtime_mark_last_busy(dev->dev);
2119         pm_runtime_put_autosuspend(dev->dev);
2120 }
2121
2122 static void
2123 nv50_disp_atomic_commit_work(struct work_struct *work)
2124 {
2125         struct drm_atomic_state *state =
2126                 container_of(work, typeof(*state), commit_work);
2127         nv50_disp_atomic_commit_tail(state);
2128 }
2129
2130 static int
2131 nv50_disp_atomic_commit(struct drm_device *dev,
2132                         struct drm_atomic_state *state, bool nonblock)
2133 {
2134         struct drm_plane_state *new_plane_state;
2135         struct drm_plane *plane;
2136         int ret, i;
2137
2138         ret = pm_runtime_get_sync(dev->dev);
2139         if (ret < 0 && ret != -EACCES)
2140                 return ret;
2141
2142         ret = drm_atomic_helper_setup_commit(state, nonblock);
2143         if (ret)
2144                 goto done;
2145
2146         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2147
2148         ret = drm_atomic_helper_prepare_planes(dev, state);
2149         if (ret)
2150                 goto done;
2151
2152         if (!nonblock) {
2153                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2154                 if (ret)
2155                         goto err_cleanup;
2156         }
2157
2158         ret = drm_atomic_helper_swap_state(state, true);
2159         if (ret)
2160                 goto err_cleanup;
2161
2162         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2163                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2164                 struct nv50_wndw *wndw = nv50_wndw(plane);
2165
2166                 if (asyw->set.image)
2167                         nv50_wndw_ntfy_enable(wndw, asyw);
2168         }
2169
2170         drm_atomic_state_get(state);
2171
2172         /*
2173          * Grab another RPM ref for the commit tail, which will release the
2174          * ref when it's finished
2175          */
2176         pm_runtime_get_noresume(dev->dev);
2177
2178         if (nonblock)
2179                 queue_work(system_unbound_wq, &state->commit_work);
2180         else
2181                 nv50_disp_atomic_commit_tail(state);
2182
2183 err_cleanup:
2184         if (ret)
2185                 drm_atomic_helper_cleanup_planes(dev, state);
2186 done:
2187         pm_runtime_put_autosuspend(dev->dev);
2188         return ret;
2189 }
2190
2191 static struct nv50_outp_atom *
2192 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2193 {
2194         struct nv50_outp_atom *outp;
2195
2196         list_for_each_entry(outp, &atom->outp, head) {
2197                 if (outp->encoder == encoder)
2198                         return outp;
2199         }
2200
2201         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2202         if (!outp)
2203                 return ERR_PTR(-ENOMEM);
2204
2205         list_add(&outp->head, &atom->outp);
2206         outp->encoder = encoder;
2207         return outp;
2208 }
2209
2210 static int
2211 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2212                                 struct drm_connector_state *old_connector_state)
2213 {
2214         struct drm_encoder *encoder = old_connector_state->best_encoder;
2215         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2216         struct drm_crtc *crtc;
2217         struct nv50_outp_atom *outp;
2218
2219         if (!(crtc = old_connector_state->crtc))
2220                 return 0;
2221
2222         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2223         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2224         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2225                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2226                 if (IS_ERR(outp))
2227                         return PTR_ERR(outp);
2228
2229                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2230                         outp->flush_disable = true;
2231                         atom->flush_disable = true;
2232                 }
2233                 outp->clr.ctrl = true;
2234                 atom->lock_core = true;
2235         }
2236
2237         return 0;
2238 }
2239
2240 static int
2241 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2242                                 struct drm_connector_state *connector_state)
2243 {
2244         struct drm_encoder *encoder = connector_state->best_encoder;
2245         struct drm_crtc_state *new_crtc_state;
2246         struct drm_crtc *crtc;
2247         struct nv50_outp_atom *outp;
2248
2249         if (!(crtc = connector_state->crtc))
2250                 return 0;
2251
2252         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2253         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2254                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2255                 if (IS_ERR(outp))
2256                         return PTR_ERR(outp);
2257
2258                 outp->set.ctrl = true;
2259                 atom->lock_core = true;
2260         }
2261
2262         return 0;
2263 }
2264
2265 static int
2266 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2267 {
2268         struct nv50_atom *atom = nv50_atom(state);
2269         struct drm_connector_state *old_connector_state, *new_connector_state;
2270         struct drm_connector *connector;
2271         struct drm_crtc_state *new_crtc_state;
2272         struct drm_crtc *crtc;
2273         int ret, i;
2274
2275         /* We need to handle colour management on a per-plane basis. */
2276         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2277                 if (new_crtc_state->color_mgmt_changed) {
2278                         ret = drm_atomic_add_affected_planes(state, crtc);
2279                         if (ret)
2280                                 return ret;
2281                 }
2282         }
2283
2284         ret = drm_atomic_helper_check(dev, state);
2285         if (ret)
2286                 return ret;
2287
2288         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2289                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2290                 if (ret)
2291                         return ret;
2292
2293                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2294                 if (ret)
2295                         return ret;
2296         }
2297
2298         ret = drm_dp_mst_atomic_check(state);
2299         if (ret)
2300                 return ret;
2301
2302         return 0;
2303 }
2304
2305 static void
2306 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2307 {
2308         struct nv50_atom *atom = nv50_atom(state);
2309         struct nv50_outp_atom *outp, *outt;
2310
2311         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2312                 list_del(&outp->head);
2313                 kfree(outp);
2314         }
2315
2316         drm_atomic_state_default_clear(state);
2317 }
2318
2319 static void
2320 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2321 {
2322         struct nv50_atom *atom = nv50_atom(state);
2323         drm_atomic_state_default_release(&atom->state);
2324         kfree(atom);
2325 }
2326
2327 static struct drm_atomic_state *
2328 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2329 {
2330         struct nv50_atom *atom;
2331         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2332             drm_atomic_state_init(dev, &atom->state) < 0) {
2333                 kfree(atom);
2334                 return NULL;
2335         }
2336         INIT_LIST_HEAD(&atom->outp);
2337         return &atom->state;
2338 }
2339
2340 static const struct drm_mode_config_funcs
2341 nv50_disp_func = {
2342         .fb_create = nouveau_user_framebuffer_create,
2343         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2344         .atomic_check = nv50_disp_atomic_check,
2345         .atomic_commit = nv50_disp_atomic_commit,
2346         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2347         .atomic_state_clear = nv50_disp_atomic_state_clear,
2348         .atomic_state_free = nv50_disp_atomic_state_free,
2349 };
2350
2351 /******************************************************************************
2352  * Init
2353  *****************************************************************************/
2354
2355 static void
2356 nv50_display_fini(struct drm_device *dev, bool suspend)
2357 {
2358         struct nouveau_encoder *nv_encoder;
2359         struct drm_encoder *encoder;
2360         struct drm_plane *plane;
2361
2362         drm_for_each_plane(plane, dev) {
2363                 struct nv50_wndw *wndw = nv50_wndw(plane);
2364                 if (plane->funcs != &nv50_wndw)
2365                         continue;
2366                 nv50_wndw_fini(wndw);
2367         }
2368
2369         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2370                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2371                         nv_encoder = nouveau_encoder(encoder);
2372                         nv50_mstm_fini(nv_encoder->dp.mstm);
2373                 }
2374         }
2375 }
2376
2377 static int
2378 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2379 {
2380         struct nv50_core *core = nv50_disp(dev)->core;
2381         struct drm_encoder *encoder;
2382         struct drm_plane *plane;
2383
2384         if (resume || runtime)
2385                 core->func->init(core);
2386
2387         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2388                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2389                         struct nouveau_encoder *nv_encoder =
2390                                 nouveau_encoder(encoder);
2391                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2392                 }
2393         }
2394
2395         drm_for_each_plane(plane, dev) {
2396                 struct nv50_wndw *wndw = nv50_wndw(plane);
2397                 if (plane->funcs != &nv50_wndw)
2398                         continue;
2399                 nv50_wndw_init(wndw);
2400         }
2401
2402         return 0;
2403 }
2404
2405 static void
2406 nv50_display_destroy(struct drm_device *dev)
2407 {
2408         struct nv50_disp *disp = nv50_disp(dev);
2409
2410         nv50_audio_component_fini(nouveau_drm(dev));
2411
2412         nvif_object_unmap(&disp->caps);
2413         nvif_object_fini(&disp->caps);
2414         nv50_core_del(&disp->core);
2415
2416         nouveau_bo_unmap(disp->sync);
2417         if (disp->sync)
2418                 nouveau_bo_unpin(disp->sync);
2419         nouveau_bo_ref(NULL, &disp->sync);
2420
2421         nouveau_display(dev)->priv = NULL;
2422         kfree(disp);
2423 }
2424
2425 int
2426 nv50_display_create(struct drm_device *dev)
2427 {
2428         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2429         struct nouveau_drm *drm = nouveau_drm(dev);
2430         struct dcb_table *dcb = &drm->vbios.dcb;
2431         struct drm_connector *connector, *tmp;
2432         struct nv50_disp *disp;
2433         struct dcb_output *dcbe;
2434         int crtcs, ret, i;
2435         bool has_mst = nv50_has_mst(drm);
2436
2437         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2438         if (!disp)
2439                 return -ENOMEM;
2440
2441         mutex_init(&disp->mutex);
2442
2443         nouveau_display(dev)->priv = disp;
2444         nouveau_display(dev)->dtor = nv50_display_destroy;
2445         nouveau_display(dev)->init = nv50_display_init;
2446         nouveau_display(dev)->fini = nv50_display_fini;
2447         disp->disp = &nouveau_display(dev)->disp;
2448         dev->mode_config.funcs = &nv50_disp_func;
2449         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2450         dev->mode_config.normalize_zpos = true;
2451
2452         /* small shared memory area we use for notifiers and semaphores */
2453         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2454                              0, 0x0000, NULL, NULL, &disp->sync);
2455         if (!ret) {
2456                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2457                 if (!ret) {
2458                         ret = nouveau_bo_map(disp->sync);
2459                         if (ret)
2460                                 nouveau_bo_unpin(disp->sync);
2461                 }
2462                 if (ret)
2463                         nouveau_bo_ref(NULL, &disp->sync);
2464         }
2465
2466         if (ret)
2467                 goto out;
2468
2469         /* allocate master evo channel */
2470         ret = nv50_core_new(drm, &disp->core);
2471         if (ret)
2472                 goto out;
2473
2474         disp->core->func->init(disp->core);
2475         if (disp->core->func->caps_init) {
2476                 ret = disp->core->func->caps_init(drm, disp);
2477                 if (ret)
2478                         goto out;
2479         }
2480
2481         /* Assign the correct format modifiers */
2482         if (disp->disp->object.oclass >= TU102_DISP)
2483                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2484         else
2485         if (disp->disp->object.oclass >= GF110_DISP)
2486                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2487         else
2488                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2489
2490         /* create crtc objects to represent the hw heads */
2491         if (disp->disp->object.oclass >= GV100_DISP)
2492                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2493         else
2494         if (disp->disp->object.oclass >= GF110_DISP)
2495                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2496         else
2497                 crtcs = 0x3;
2498
2499         for (i = 0; i < fls(crtcs); i++) {
2500                 struct nv50_head *head;
2501
2502                 if (!(crtcs & (1 << i)))
2503                         continue;
2504
2505                 head = nv50_head_create(dev, i);
2506                 if (IS_ERR(head)) {
2507                         ret = PTR_ERR(head);
2508                         goto out;
2509                 }
2510
2511                 if (has_mst) {
2512                         head->msto = nv50_msto_new(dev, head, i);
2513                         if (IS_ERR(head->msto)) {
2514                                 ret = PTR_ERR(head->msto);
2515                                 head->msto = NULL;
2516                                 goto out;
2517                         }
2518
2519                         /*
2520                          * FIXME: This is a hack to workaround the following
2521                          * issues:
2522                          *
2523                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2524                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2525                          *
2526                          * Once these issues are closed, this should be
2527                          * removed
2528                          */
2529                         head->msto->encoder.possible_crtcs = crtcs;
2530                 }
2531         }
2532
2533         /* create encoder/connector objects based on VBIOS DCB table */
2534         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2535                 connector = nouveau_connector_create(dev, dcbe);
2536                 if (IS_ERR(connector))
2537                         continue;
2538
2539                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2540                         switch (dcbe->type) {
2541                         case DCB_OUTPUT_TMDS:
2542                         case DCB_OUTPUT_LVDS:
2543                         case DCB_OUTPUT_DP:
2544                                 ret = nv50_sor_create(connector, dcbe);
2545                                 break;
2546                         case DCB_OUTPUT_ANALOG:
2547                                 ret = nv50_dac_create(connector, dcbe);
2548                                 break;
2549                         default:
2550                                 ret = -ENODEV;
2551                                 break;
2552                         }
2553                 } else {
2554                         ret = nv50_pior_create(connector, dcbe);
2555                 }
2556
2557                 if (ret) {
2558                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2559                                      dcbe->location, dcbe->type,
2560                                      ffs(dcbe->or) - 1, ret);
2561                         ret = 0;
2562                 }
2563         }
2564
2565         /* cull any connectors we created that don't have an encoder */
2566         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2567                 if (connector->possible_encoders)
2568                         continue;
2569
2570                 NV_WARN(drm, "%s has no encoders, removing\n",
2571                         connector->name);
2572                 connector->funcs->destroy(connector);
2573         }
2574
2575         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2576         dev->vblank_disable_immediate = true;
2577
2578         nv50_audio_component_init(drm);
2579
2580 out:
2581         if (ret)
2582                 nv50_display_destroy(dev);
2583         return ret;
2584 }
2585
2586 /******************************************************************************
2587  * Format modifiers
2588  *****************************************************************************/
2589
2590 /****************************************************************
2591  *            Log2(block height) ----------------------------+  *
2592  *            Page Kind ----------------------------------+  |  *
2593  *            Gob Height/Page Kind Generation ------+     |  |  *
2594  *                          Sector layout -------+  |     |  |  *
2595  *                          Compression ------+  |  |     |  |  */
2596 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2597         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2598         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2599         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2600         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2601         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2602         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2603         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2604         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2605         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2606         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2607         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2608         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2609         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2610         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2611         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2612         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2613         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2614         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2615         DRM_FORMAT_MOD_LINEAR,
2616         DRM_FORMAT_MOD_INVALID
2617 };
2618
2619 /****************************************************************
2620  *            Log2(block height) ----------------------------+  *
2621  *            Page Kind ----------------------------------+  |  *
2622  *            Gob Height/Page Kind Generation ------+     |  |  *
2623  *                          Sector layout -------+  |     |  |  *
2624  *                          Compression ------+  |  |     |  |  */
2625 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2626         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2627         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2628         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2629         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2630         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2631         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2632         DRM_FORMAT_MOD_LINEAR,
2633         DRM_FORMAT_MOD_INVALID
2634 };