drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40 #include <drm/drm_edid.h>
  41
  42 #include <nvif/class.h>
  43 #include <nvif/cl0002.h>
  44 #include <nvif/cl5070.h>
  45 #include <nvif/cl507d.h>
  46 #include <nvif/event.h>
  47
  48 #include "nouveau_drv.h"
  49 #include "nouveau_dma.h"
  50 #include "nouveau_gem.h"
  51 #include "nouveau_connector.h"
  52 #include "nouveau_encoder.h"
  53 #include "nouveau_fence.h"
  54 #include "nouveau_fbcon.h"
  55
  56 #include <subdev/bios/dp.h>
  57
  58 /******************************************************************************
  59  * Atomic state
  60  *****************************************************************************/
  61
  62 struct nv50_outp_atom {
  63         struct list_head head;
  64
  65         struct drm_encoder *encoder;
  66         bool flush_disable;
  67
  68         union nv50_outp_atom_mask {
  69                 struct {
  70                         bool ctrl:1;
  71                 };
  72                 u8 mask;
  73         } set, clr;
  74 };
  75
  76 /******************************************************************************
  77  * EVO channel
  78  *****************************************************************************/
  79
  80 static int
  81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  82                  const s32 *oclass, u8 head, void *data, u32 size,
  83                  struct nv50_chan *chan)
  84 {
  85         struct nvif_sclass *sclass;
  86         int ret, i, n;
  87
  88         chan->device = device;
  89
  90         ret = n = nvif_object_sclass_get(disp, &sclass);
  91         if (ret < 0)
  92                 return ret;
  93
  94         while (oclass[0]) {
  95                 for (i = 0; i < n; i++) {
  96                         if (sclass[i].oclass == oclass[0]) {
  97                                 ret = nvif_object_init(disp, 0, oclass[0],
  98                                                        data, size, &chan->user);
  99                                 if (ret == 0)
 100                                         nvif_object_map(&chan->user, NULL, 0);
 101                                 nvif_object_sclass_put(&sclass);
 102                                 return ret;
 103                         }
 104                 }
 105                 oclass++;
 106         }
 107
 108         nvif_object_sclass_put(&sclass);
 109         return -ENOSYS;
 110 }
 111
 112 static void
 113 nv50_chan_destroy(struct nv50_chan *chan)
 114 {
 115         nvif_object_fini(&chan->user);
 116 }
 117
 118 /******************************************************************************
 119  * DMA EVO channel
 120  *****************************************************************************/
 121
 122 void
 123 nv50_dmac_destroy(struct nv50_dmac *dmac)
 124 {
 125         nvif_object_fini(&dmac->vram);
 126         nvif_object_fini(&dmac->sync);
 127
 128         nv50_chan_destroy(&dmac->base);
 129
 130         nvif_mem_fini(&dmac->push);
 131 }
 132
 133 int
 134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 135                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 136                  struct nv50_dmac *dmac)
 137 {
 138         struct nouveau_cli *cli = (void *)device->object.client;
 139         struct nv50_disp_core_channel_dma_v0 *args = data;
 140         u8 type = NVIF_MEM_COHERENT;
 141         int ret;
 142
 143         mutex_init(&dmac->lock);
 144
 145         /* Pascal added support for 47-bit physical addresses, but some
 146          * parts of EVO still only accept 40-bit PAs.
 147          *
 148          * To avoid issues on systems with large amounts of RAM, and on
 149          * systems where an IOMMU maps pages at a high address, we need
 150          * to allocate push buffers in VRAM instead.
 151          *
 152          * This appears to match NVIDIA's behaviour on Pascal.
 153          */
 154         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 155                 type |= NVIF_MEM_VRAM;
 156
 157         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 158         if (ret)
 159                 return ret;
 160
 161         dmac->ptr = dmac->push.object.map.ptr;
 162
 163         args->pushbuf = nvif_handle(&dmac->push.object);
 164
 165         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 166                                &dmac->base);
 167         if (ret)
 168                 return ret;
 169
 170         if (!syncbuf)
 171                 return 0;
 172
 173         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 174                                &(struct nv_dma_v0) {
 175                                         .target = NV_DMA_V0_TARGET_VRAM,
 176                                         .access = NV_DMA_V0_ACCESS_RDWR,
 177                                         .start = syncbuf + 0x0000,
 178                                         .limit = syncbuf + 0x0fff,
 179                                }, sizeof(struct nv_dma_v0),
 180                                &dmac->sync);
 181         if (ret)
 182                 return ret;
 183
 184         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 185                                &(struct nv_dma_v0) {
 186                                         .target = NV_DMA_V0_TARGET_VRAM,
 187                                         .access = NV_DMA_V0_ACCESS_RDWR,
 188                                         .start = 0,
 189                                         .limit = device->info.ram_user - 1,
 190                                }, sizeof(struct nv_dma_v0),
 191                                &dmac->vram);
 192         if (ret)
 193                 return ret;
 194
 195         return ret;
 196 }
 197
 198 /******************************************************************************
 199  * EVO channel helpers
 200  *****************************************************************************/
 201 u32 *
 202 evo_wait(struct nv50_dmac *evoc, int nr)
 203 {
 204         struct nv50_dmac *dmac = evoc;
 205         struct nvif_device *device = dmac->base.device;
 206         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 207
 208         mutex_lock(&dmac->lock);
 209         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 210                 dmac->ptr[put] = 0x20000000;
 211
 212                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 213                 if (nvif_msec(device, 2000,
 214                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 215                                 break;
 216                 ) < 0) {
 217                         mutex_unlock(&dmac->lock);
 218                         pr_err("nouveau: evo channel stalled\n");
 219                         return NULL;
 220                 }
 221
 222                 put = 0;
 223         }
 224
 225         return dmac->ptr + put;
 226 }
 227
 228 void
 229 evo_kick(u32 *push, struct nv50_dmac *evoc)
 230 {
 231         struct nv50_dmac *dmac = evoc;
 232
 233         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 234          * writes have been flushed right through to VRAM before writing PUT.
 235          */
 236         if (dmac->push.type & NVIF_MEM_VRAM) {
 237                 struct nvif_device *device = dmac->base.device;
 238                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 239                 nvif_msec(device, 2000,
 240                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 241                                 break;
 242                 );
 243         }
 244
 245         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 246         mutex_unlock(&dmac->lock);
 247 }
 248
 249 /******************************************************************************
 250  * Output path helpers
 251  *****************************************************************************/
 252 static void
 253 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 254 {
 255         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 256         struct {
 257                 struct nv50_disp_mthd_v1 base;
 258         } args = {
 259                 .base.version = 1,
 260                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 261                 .base.hasht  = nv_encoder->dcb->hasht,
 262                 .base.hashm  = nv_encoder->dcb->hashm,
 263         };
 264
 265         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 266         nv_encoder->or = -1;
 267         nv_encoder->link = 0;
 268 }
 269
 270 static int
 271 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
 272 {
 273         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 274         struct nv50_disp *disp = nv50_disp(drm->dev);
 275         struct {
 276                 struct nv50_disp_mthd_v1 base;
 277                 struct nv50_disp_acquire_v0 info;
 278         } args = {
 279                 .base.version = 1,
 280                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 281                 .base.hasht  = nv_encoder->dcb->hasht,
 282                 .base.hashm  = nv_encoder->dcb->hashm,
 283         };
 284         int ret;
 285
 286         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 287         if (ret) {
 288                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 289                 return ret;
 290         }
 291
 292         nv_encoder->or = args.info.or;
 293         nv_encoder->link = args.info.link;
 294         return 0;
 295 }
 296
 297 static int
 298 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 299                             struct drm_crtc_state *crtc_state,
 300                             struct drm_connector_state *conn_state,
 301                             struct drm_display_mode *native_mode)
 302 {
 303         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 304         struct drm_display_mode *mode = &crtc_state->mode;
 305         struct drm_connector *connector = conn_state->connector;
 306         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 307         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 308
 309         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 310         asyc->scaler.full = false;
 311         if (!native_mode)
 312                 return 0;
 313
 314         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 315                 switch (connector->connector_type) {
 316                 case DRM_MODE_CONNECTOR_LVDS:
 317                 case DRM_MODE_CONNECTOR_eDP:
 318                         /* Force use of scaler for non-EDID modes. */
 319                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
 320                                 break;
 321                         mode = native_mode;
 322                         asyc->scaler.full = true;
 323                         break;
 324                 default:
 325                         break;
 326                 }
 327         } else {
 328                 mode = native_mode;
 329         }
 330
 331         if (!drm_mode_equal(adjusted_mode, mode)) {
 332                 drm_mode_copy(adjusted_mode, mode);
 333                 crtc_state->mode_changed = true;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int
 340 nv50_outp_atomic_check(struct drm_encoder *encoder,
 341                        struct drm_crtc_state *crtc_state,
 342                        struct drm_connector_state *conn_state)
 343 {
 344         struct nouveau_connector *nv_connector =
 345                 nouveau_connector(conn_state->connector);
 346         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 347                                            nv_connector->native_mode);
 348 }
 349
 350 /******************************************************************************
 351  * DAC
 352  *****************************************************************************/
 353 static void
 354 nv50_dac_disable(struct drm_encoder *encoder)
 355 {
 356         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 357         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 358         if (nv_encoder->crtc)
 359                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 360         nv_encoder->crtc = NULL;
 361         nv50_outp_release(nv_encoder);
 362 }
 363
 364 static void
 365 nv50_dac_enable(struct drm_encoder *encoder)
 366 {
 367         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 368         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 369         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 370         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 371
 372         nv50_outp_acquire(nv_encoder);
 373
 374         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 375         asyh->or.depth = 0;
 376
 377         nv_encoder->crtc = encoder->crtc;
 378 }
 379
 380 static enum drm_connector_status
 381 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 382 {
 383         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 384         struct nv50_disp *disp = nv50_disp(encoder->dev);
 385         struct {
 386                 struct nv50_disp_mthd_v1 base;
 387                 struct nv50_disp_dac_load_v0 load;
 388         } args = {
 389                 .base.version = 1,
 390                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 391                 .base.hasht  = nv_encoder->dcb->hasht,
 392                 .base.hashm  = nv_encoder->dcb->hashm,
 393         };
 394         int ret;
 395
 396         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 397         if (args.load.data == 0)
 398                 args.load.data = 340;
 399
 400         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 401         if (ret || !args.load.load)
 402                 return connector_status_disconnected;
 403
 404         return connector_status_connected;
 405 }
 406
 407 static const struct drm_encoder_helper_funcs
 408 nv50_dac_help = {
 409         .atomic_check = nv50_outp_atomic_check,
 410         .enable = nv50_dac_enable,
 411         .disable = nv50_dac_disable,
 412         .detect = nv50_dac_detect
 413 };
 414
 415 static void
 416 nv50_dac_destroy(struct drm_encoder *encoder)
 417 {
 418         drm_encoder_cleanup(encoder);
 419         kfree(encoder);
 420 }
 421
 422 static const struct drm_encoder_funcs
 423 nv50_dac_func = {
 424         .destroy = nv50_dac_destroy,
 425 };
 426
 427 static int
 428 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 429 {
 430         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 431         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 432         struct nvkm_i2c_bus *bus;
 433         struct nouveau_encoder *nv_encoder;
 434         struct drm_encoder *encoder;
 435         int type = DRM_MODE_ENCODER_DAC;
 436
 437         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 438         if (!nv_encoder)
 439                 return -ENOMEM;
 440         nv_encoder->dcb = dcbe;
 441
 442         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 443         if (bus)
 444                 nv_encoder->i2c = &bus->i2c;
 445
 446         encoder = to_drm_encoder(nv_encoder);
 447         encoder->possible_crtcs = dcbe->heads;
 448         encoder->possible_clones = 0;
 449         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 450                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 451         drm_encoder_helper_add(encoder, &nv50_dac_help);
 452
 453         drm_connector_attach_encoder(connector, encoder);
 454         return 0;
 455 }
 456
 457 /******************************************************************************
 458  * Audio
 459  *****************************************************************************/
 460 static void
 461 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 462 {
 463         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 464         struct nv50_disp *disp = nv50_disp(encoder->dev);
 465         struct {
 466                 struct nv50_disp_mthd_v1 base;
 467                 struct nv50_disp_sor_hda_eld_v0 eld;
 468         } args = {
 469                 .base.version = 1,
 470                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 471                 .base.hasht   = nv_encoder->dcb->hasht,
 472                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 473                                 (0x0100 << nv_crtc->index),
 474         };
 475
 476         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 477 }
 478
 479 static void
 480 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 481 {
 482         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 483         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 484         struct nouveau_connector *nv_connector;
 485         struct nv50_disp *disp = nv50_disp(encoder->dev);
 486         struct __packed {
 487                 struct {
 488                         struct nv50_disp_mthd_v1 mthd;
 489                         struct nv50_disp_sor_hda_eld_v0 eld;
 490                 } base;
 491                 u8 data[sizeof(nv_connector->base.eld)];
 492         } args = {
 493                 .base.mthd.version = 1,
 494                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 495                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 496                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 497                                      (0x0100 << nv_crtc->index),
 498         };
 499
 500         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 501         if (!drm_detect_monitor_audio(nv_connector->edid))
 502                 return;
 503
 504         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 505
 506         nvif_mthd(&disp->disp->object, 0, &args,
 507                   sizeof(args.base) + drm_eld_size(args.data));
 508 }
 509
 510 /******************************************************************************
 511  * HDMI
 512  *****************************************************************************/
 513 static void
 514 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 515 {
 516         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 517         struct nv50_disp *disp = nv50_disp(encoder->dev);
 518         struct {
 519                 struct nv50_disp_mthd_v1 base;
 520                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 521         } args = {
 522                 .base.version = 1,
 523                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 524                 .base.hasht  = nv_encoder->dcb->hasht,
 525                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 526                                (0x0100 << nv_crtc->index),
 527         };
 528
 529         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 530 }
 531
 532 static void
 533 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 534 {
 535         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 536         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 537         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 538         struct nv50_disp *disp = nv50_disp(encoder->dev);
 539         struct {
 540                 struct nv50_disp_mthd_v1 base;
 541                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 542                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 543         } args = {
 544                 .base.version = 1,
 545                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 546                 .base.hasht  = nv_encoder->dcb->hasht,
 547                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 548                                (0x0100 << nv_crtc->index),
 549                 .pwr.state = 1,
 550                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 551         };
 552         struct nouveau_connector *nv_connector;
 553         struct drm_hdmi_info *hdmi;
 554         u32 max_ac_packet;
 555         union hdmi_infoframe avi_frame;
 556         union hdmi_infoframe vendor_frame;
 557         bool high_tmds_clock_ratio = false, scrambling = false;
 558         u8 config;
 559         int ret;
 560         int size;
 561
 562         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 563         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 564                 return;
 565
 566         hdmi = &nv_connector->base.display_info.hdmi;
 567
 568         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 569                                                        &nv_connector->base, mode);
 570         if (!ret) {
 571                 /* We have an AVI InfoFrame, populate it to the display */
 572                 args.pwr.avi_infoframe_length
 573                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 574         }
 575
 576         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 577                                                           &nv_connector->base, mode);
 578         if (!ret) {
 579                 /* We have a Vendor InfoFrame, populate it to the display */
 580                 args.pwr.vendor_infoframe_length
 581                         = hdmi_infoframe_pack(&vendor_frame,
 582                                               args.infoframes
 583                                               + args.pwr.avi_infoframe_length,
 584                                               17);
 585         }
 586
 587         max_ac_packet  = mode->htotal - mode->hdisplay;
 588         max_ac_packet -= args.pwr.rekey;
 589         max_ac_packet -= 18; /* constant from tegra */
 590         args.pwr.max_ac_packet = max_ac_packet / 32;
 591
 592         if (hdmi->scdc.scrambling.supported) {
 593                 high_tmds_clock_ratio = mode->clock > 340000;
 594                 scrambling = high_tmds_clock_ratio ||
 595                         hdmi->scdc.scrambling.low_rates;
 596         }
 597
 598         args.pwr.scdc =
 599                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 600                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 601
 602         size = sizeof(args.base)
 603                 + sizeof(args.pwr)
 604                 + args.pwr.avi_infoframe_length
 605                 + args.pwr.vendor_infoframe_length;
 606         nvif_mthd(&disp->disp->object, 0, &args, size);
 607
 608         nv50_audio_enable(encoder, mode);
 609
 610         /* If SCDC is supported by the downstream monitor, update
 611          * divider / scrambling settings to what we programmed above.
 612          */
 613         if (!hdmi->scdc.scrambling.supported)
 614                 return;
 615
 616         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 617         if (ret < 0) {
 618                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 619                 return;
 620         }
 621         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 622         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 623         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 624         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 625         if (ret < 0)
 626                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 627                          config, ret);
 628 }
 629
 630 /******************************************************************************
 631  * MST
 632  *****************************************************************************/
 633 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 634 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 635 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 636
 637 struct nv50_mstm {
 638         struct nouveau_encoder *outp;
 639
 640         struct drm_dp_mst_topology_mgr mgr;
 641         struct nv50_msto *msto[4];
 642
 643         bool modified;
 644         bool disabled;
 645         int links;
 646 };
 647
 648 struct nv50_mstc {
 649         struct nv50_mstm *mstm;
 650         struct drm_dp_mst_port *port;
 651         struct drm_connector connector;
 652
 653         struct drm_display_mode *native;
 654         struct edid *edid;
 655
 656         int pbn;
 657 };
 658
 659 struct nv50_msto {
 660         struct drm_encoder encoder;
 661
 662         struct nv50_head *head;
 663         struct nv50_mstc *mstc;
 664         bool disabled;
 665 };
 666
 667 static struct drm_dp_payload *
 668 nv50_msto_payload(struct nv50_msto *msto)
 669 {
 670         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 671         struct nv50_mstc *mstc = msto->mstc;
 672         struct nv50_mstm *mstm = mstc->mstm;
 673         int vcpi = mstc->port->vcpi.vcpi, i;
 674
 675         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 676         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 677                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 678                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 679                           mstm->outp->base.base.name, i, payload->vcpi,
 680                           payload->start_slot, payload->num_slots);
 681         }
 682
 683         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 684                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 685                 if (payload->vcpi == vcpi)
 686                         return payload;
 687         }
 688
 689         return NULL;
 690 }
 691
 692 static void
 693 nv50_msto_cleanup(struct nv50_msto *msto)
 694 {
 695         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 696         struct nv50_mstc *mstc = msto->mstc;
 697         struct nv50_mstm *mstm = mstc->mstm;
 698
 699         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 700         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
 701                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 702         if (msto->disabled) {
 703                 msto->mstc = NULL;
 704                 msto->head = NULL;
 705                 msto->disabled = false;
 706         }
 707 }
 708
 709 static void
 710 nv50_msto_prepare(struct nv50_msto *msto)
 711 {
 712         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 713         struct nv50_mstc *mstc = msto->mstc;
 714         struct nv50_mstm *mstm = mstc->mstm;
 715         struct {
 716                 struct nv50_disp_mthd_v1 base;
 717                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 718         } args = {
 719                 .base.version = 1,
 720                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 721                 .base.hasht  = mstm->outp->dcb->hasht,
 722                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 723                                (0x0100 << msto->head->base.index),
 724         };
 725
 726         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 727         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
 728                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 729                 if (payload) {
 730                         args.vcpi.start_slot = payload->start_slot;
 731                         args.vcpi.num_slots = payload->num_slots;
 732                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 733                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 734                 }
 735         }
 736
 737         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 738                   msto->encoder.name, msto->head->base.base.name,
 739                   args.vcpi.start_slot, args.vcpi.num_slots,
 740                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 741         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 742 }
 743
 744 static int
 745 nv50_msto_atomic_check(struct drm_encoder *encoder,
 746                        struct drm_crtc_state *crtc_state,
 747                        struct drm_connector_state *conn_state)
 748 {
 749         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
 750         struct nv50_mstm *mstm = mstc->mstm;
 751         int bpp = conn_state->connector->display_info.bpc * 3;
 752         int slots;
 753
 754         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
 755
 756         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 757         if (slots < 0)
 758                 return slots;
 759
 760         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 761                                            mstc->native);
 762 }
 763
 764 static void
 765 nv50_msto_enable(struct drm_encoder *encoder)
 766 {
 767         struct nv50_head *head = nv50_head(encoder->crtc);
 768         struct nv50_msto *msto = nv50_msto(encoder);
 769         struct nv50_mstc *mstc = NULL;
 770         struct nv50_mstm *mstm = NULL;
 771         struct drm_connector *connector;
 772         struct drm_connector_list_iter conn_iter;
 773         u8 proto, depth;
 774         int slots;
 775         bool r;
 776
 777         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 778         drm_for_each_connector_iter(connector, &conn_iter) {
 779                 if (connector->state->best_encoder == &msto->encoder) {
 780                         mstc = nv50_mstc(connector);
 781                         mstm = mstc->mstm;
 782                         break;
 783                 }
 784         }
 785         drm_connector_list_iter_end(&conn_iter);
 786
 787         if (WARN_ON(!mstc))
 788                 return;
 789
 790         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
 791         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
 792         WARN_ON(!r);
 793
 794         if (!mstm->links++)
 795                 nv50_outp_acquire(mstm->outp);
 796
 797         if (mstm->outp->link & 1)
 798                 proto = 0x8;
 799         else
 800                 proto = 0x9;
 801
 802         switch (mstc->connector.display_info.bpc) {
 803         case  6: depth = 0x2; break;
 804         case  8: depth = 0x5; break;
 805         case 10:
 806         default: depth = 0x6; break;
 807         }
 808
 809         mstm->outp->update(mstm->outp, head->base.index,
 810                            nv50_head_atom(head->base.base.state), proto, depth);
 811
 812         msto->head = head;
 813         msto->mstc = mstc;
 814         mstm->modified = true;
 815 }
 816
 817 static void
 818 nv50_msto_disable(struct drm_encoder *encoder)
 819 {
 820         struct nv50_msto *msto = nv50_msto(encoder);
 821         struct nv50_mstc *mstc = msto->mstc;
 822         struct nv50_mstm *mstm = mstc->mstm;
 823
 824         if (mstc->port)
 825                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 826
 827         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 828         mstm->modified = true;
 829         if (!--mstm->links)
 830                 mstm->disabled = true;
 831         msto->disabled = true;
 832 }
 833
 834 static const struct drm_encoder_helper_funcs
 835 nv50_msto_help = {
 836         .disable = nv50_msto_disable,
 837         .enable = nv50_msto_enable,
 838         .atomic_check = nv50_msto_atomic_check,
 839 };
 840
 841 static void
 842 nv50_msto_destroy(struct drm_encoder *encoder)
 843 {
 844         struct nv50_msto *msto = nv50_msto(encoder);
 845         drm_encoder_cleanup(&msto->encoder);
 846         kfree(msto);
 847 }
 848
 849 static const struct drm_encoder_funcs
 850 nv50_msto = {
 851         .destroy = nv50_msto_destroy,
 852 };
 853
 854 static int
 855 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
 856               struct nv50_msto **pmsto)
 857 {
 858         struct nv50_msto *msto;
 859         int ret;
 860
 861         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
 862                 return -ENOMEM;
 863
 864         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
 865                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
 866         if (ret) {
 867                 kfree(*pmsto);
 868                 *pmsto = NULL;
 869                 return ret;
 870         }
 871
 872         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
 873         msto->encoder.possible_crtcs = heads;
 874         return 0;
 875 }
 876
 877 static struct drm_encoder *
 878 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
 879                               struct drm_connector_state *connector_state)
 880 {
 881         struct nv50_head *head = nv50_head(connector_state->crtc);
 882         struct nv50_mstc *mstc = nv50_mstc(connector);
 883
 884         return &mstc->mstm->msto[head->base.index]->encoder;
 885 }
 886
 887 static struct drm_encoder *
 888 nv50_mstc_best_encoder(struct drm_connector *connector)
 889 {
 890         struct nv50_mstc *mstc = nv50_mstc(connector);
 891
 892         return &mstc->mstm->msto[0]->encoder;
 893 }
 894
 895 static enum drm_mode_status
 896 nv50_mstc_mode_valid(struct drm_connector *connector,
 897                      struct drm_display_mode *mode)
 898 {
 899         return MODE_OK;
 900 }
 901
 902 static int
 903 nv50_mstc_get_modes(struct drm_connector *connector)
 904 {
 905         struct nv50_mstc *mstc = nv50_mstc(connector);
 906         int ret = 0;
 907
 908         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
 909         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
 910         if (mstc->edid)
 911                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
 912
 913         if (!mstc->connector.display_info.bpc)
 914                 mstc->connector.display_info.bpc = 8;
 915
 916         if (mstc->native)
 917                 drm_mode_destroy(mstc->connector.dev, mstc->native);
 918         mstc->native = nouveau_conn_native_mode(&mstc->connector);
 919         return ret;
 920 }
 921
 922 static const struct drm_connector_helper_funcs
 923 nv50_mstc_help = {
 924         .get_modes = nv50_mstc_get_modes,
 925         .mode_valid = nv50_mstc_mode_valid,
 926         .best_encoder = nv50_mstc_best_encoder,
 927         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
 928 };
 929
 930 static enum drm_connector_status
 931 nv50_mstc_detect(struct drm_connector *connector, bool force)
 932 {
 933         struct nv50_mstc *mstc = nv50_mstc(connector);
 934         enum drm_connector_status conn_status;
 935         int ret;
 936
 937         if (!mstc->port)
 938                 return connector_status_disconnected;
 939
 940         ret = pm_runtime_get_sync(connector->dev->dev);
 941         if (ret < 0 && ret != -EACCES)
 942                 return connector_status_disconnected;
 943
 944         conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
 945                                              mstc->port);
 946
 947         pm_runtime_mark_last_busy(connector->dev->dev);
 948         pm_runtime_put_autosuspend(connector->dev->dev);
 949         return conn_status;
 950 }
 951
 952 static void
 953 nv50_mstc_destroy(struct drm_connector *connector)
 954 {
 955         struct nv50_mstc *mstc = nv50_mstc(connector);
 956         drm_connector_cleanup(&mstc->connector);
 957         kfree(mstc);
 958 }
 959
 960 static const struct drm_connector_funcs
 961 nv50_mstc = {
 962         .reset = nouveau_conn_reset,
 963         .detect = nv50_mstc_detect,
 964         .fill_modes = drm_helper_probe_single_connector_modes,
 965         .destroy = nv50_mstc_destroy,
 966         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
 967         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
 968         .atomic_set_property = nouveau_conn_atomic_set_property,
 969         .atomic_get_property = nouveau_conn_atomic_get_property,
 970 };
 971
 972 static int
 973 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
 974               const char *path, struct nv50_mstc **pmstc)
 975 {
 976         struct drm_device *dev = mstm->outp->base.base.dev;
 977         struct nv50_mstc *mstc;
 978         int ret, i;
 979
 980         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
 981                 return -ENOMEM;
 982         mstc->mstm = mstm;
 983         mstc->port = port;
 984
 985         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
 986                                  DRM_MODE_CONNECTOR_DisplayPort);
 987         if (ret) {
 988                 kfree(*pmstc);
 989                 *pmstc = NULL;
 990                 return ret;
 991         }
 992
 993         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
 994
 995         mstc->connector.funcs->reset(&mstc->connector);
 996         nouveau_conn_attach_properties(&mstc->connector);
 997
 998         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
 999                 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1000
1001         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1002         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1003         drm_connector_set_path_property(&mstc->connector, path);
1004         return 0;
1005 }
1006
1007 static void
1008 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1009 {
1010         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1011         struct drm_encoder *encoder;
1012         int ret;
1013
1014         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1015         ret = drm_dp_check_act_status(&mstm->mgr);
1016
1017         ret = drm_dp_update_payload_part2(&mstm->mgr);
1018
1019         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1020                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1021                         struct nv50_msto *msto = nv50_msto(encoder);
1022                         struct nv50_mstc *mstc = msto->mstc;
1023                         if (mstc && mstc->mstm == mstm)
1024                                 nv50_msto_cleanup(msto);
1025                 }
1026         }
1027
1028         mstm->modified = false;
1029 }
1030
1031 static void
1032 nv50_mstm_prepare(struct nv50_mstm *mstm)
1033 {
1034         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1035         struct drm_encoder *encoder;
1036         int ret;
1037
1038         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1039         ret = drm_dp_update_payload_part1(&mstm->mgr);
1040
1041         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1042                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1043                         struct nv50_msto *msto = nv50_msto(encoder);
1044                         struct nv50_mstc *mstc = msto->mstc;
1045                         if (mstc && mstc->mstm == mstm)
1046                                 nv50_msto_prepare(msto);
1047                 }
1048         }
1049
1050         if (mstm->disabled) {
1051                 if (!mstm->links)
1052                         nv50_outp_release(mstm->outp);
1053                 mstm->disabled = false;
1054         }
1055 }
1056
1057 static void
1058 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1059                             struct drm_connector *connector)
1060 {
1061         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1062         struct nv50_mstc *mstc = nv50_mstc(connector);
1063
1064         drm_connector_unregister(&mstc->connector);
1065
1066         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1067
1068         drm_modeset_lock(&drm->dev->mode_config.connection_mutex, NULL);
1069         mstc->port = NULL;
1070         drm_modeset_unlock(&drm->dev->mode_config.connection_mutex);
1071
1072         drm_connector_put(&mstc->connector);
1073 }
1074
1075 static void
1076 nv50_mstm_register_connector(struct drm_connector *connector)
1077 {
1078         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1079
1080         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1081
1082         drm_connector_register(connector);
1083 }
1084
1085 static struct drm_connector *
1086 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1087                         struct drm_dp_mst_port *port, const char *path)
1088 {
1089         struct nv50_mstm *mstm = nv50_mstm(mgr);
1090         struct nv50_mstc *mstc;
1091         int ret;
1092
1093         ret = nv50_mstc_new(mstm, port, path, &mstc);
1094         if (ret)
1095                 return NULL;
1096
1097         return &mstc->connector;
1098 }
1099
1100 static const struct drm_dp_mst_topology_cbs
1101 nv50_mstm = {
1102         .add_connector = nv50_mstm_add_connector,
1103         .register_connector = nv50_mstm_register_connector,
1104         .destroy_connector = nv50_mstm_destroy_connector,
1105 };
1106
1107 void
1108 nv50_mstm_service(struct nv50_mstm *mstm)
1109 {
1110         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1111         bool handled = true;
1112         int ret;
1113         u8 esi[8] = {};
1114
1115         if (!aux)
1116                 return;
1117
1118         while (handled) {
1119                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1120                 if (ret != 8) {
1121                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1122                         return;
1123                 }
1124
1125                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1126                 if (!handled)
1127                         break;
1128
1129                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1130         }
1131 }
1132
1133 void
1134 nv50_mstm_remove(struct nv50_mstm *mstm)
1135 {
1136         if (mstm)
1137                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1138 }
1139
1140 static int
1141 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1142 {
1143         struct nouveau_encoder *outp = mstm->outp;
1144         struct {
1145                 struct nv50_disp_mthd_v1 base;
1146                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1147         } args = {
1148                 .base.version = 1,
1149                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1150                 .base.hasht = outp->dcb->hasht,
1151                 .base.hashm = outp->dcb->hashm,
1152                 .mst.state = state,
1153         };
1154         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1155         struct nvif_object *disp = &drm->display->disp.object;
1156         int ret;
1157
1158         if (dpcd >= 0x12) {
1159                 /* Even if we're enabling MST, start with disabling the
1160                  * branching unit to clear any sink-side MST topology state
1161                  * that wasn't set by us
1162                  */
1163                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1164                 if (ret < 0)
1165                         return ret;
1166
1167                 if (state) {
1168                         /* Now, start initializing */
1169                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1170                                                  DP_MST_EN);
1171                         if (ret < 0)
1172                                 return ret;
1173                 }
1174         }
1175
1176         return nvif_mthd(disp, 0, &args, sizeof(args));
1177 }
1178
1179 int
1180 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1181 {
1182         struct drm_dp_aux *aux;
1183         int ret;
1184         bool old_state, new_state;
1185         u8 mstm_ctrl;
1186
1187         if (!mstm)
1188                 return 0;
1189
1190         mutex_lock(&mstm->mgr.lock);
1191
1192         old_state = mstm->mgr.mst_state;
1193         new_state = old_state;
1194         aux = mstm->mgr.aux;
1195
1196         if (old_state) {
1197                 /* Just check that the MST hub is still as we expect it */
1198                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1199                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1200                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1201                         new_state = false;
1202                 }
1203         } else if (dpcd[0] >= 0x12) {
1204                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1205                 if (ret < 0)
1206                         goto probe_error;
1207
1208                 if (!(dpcd[1] & DP_MST_CAP))
1209                         dpcd[0] = 0x11;
1210                 else
1211                         new_state = allow;
1212         }
1213
1214         if (new_state == old_state) {
1215                 mutex_unlock(&mstm->mgr.lock);
1216                 return new_state;
1217         }
1218
1219         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1220         if (ret)
1221                 goto probe_error;
1222
1223         mutex_unlock(&mstm->mgr.lock);
1224
1225         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1226         if (ret)
1227                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1228
1229         return new_state;
1230
1231 probe_error:
1232         mutex_unlock(&mstm->mgr.lock);
1233         return ret;
1234 }
1235
1236 static void
1237 nv50_mstm_fini(struct nv50_mstm *mstm)
1238 {
1239         if (mstm && mstm->mgr.mst_state)
1240                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1241 }
1242
1243 static void
1244 nv50_mstm_init(struct nv50_mstm *mstm)
1245 {
1246         if (mstm && mstm->mgr.mst_state)
1247                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1248 }
1249
1250 static void
1251 nv50_mstm_del(struct nv50_mstm **pmstm)
1252 {
1253         struct nv50_mstm *mstm = *pmstm;
1254         if (mstm) {
1255                 kfree(*pmstm);
1256                 *pmstm = NULL;
1257         }
1258 }
1259
1260 static int
1261 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1262               int conn_base_id, struct nv50_mstm **pmstm)
1263 {
1264         const int max_payloads = hweight8(outp->dcb->heads);
1265         struct drm_device *dev = outp->base.base.dev;
1266         struct nv50_mstm *mstm;
1267         int ret, i;
1268         u8 dpcd;
1269
1270         /* This is a workaround for some monitors not functioning
1271          * correctly in MST mode on initial module load.  I think
1272          * some bad interaction with the VBIOS may be responsible.
1273          *
1274          * A good ol' off and on again seems to work here ;)
1275          */
1276         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1277         if (ret >= 0 && dpcd >= 0x12)
1278                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1279
1280         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1281                 return -ENOMEM;
1282         mstm->outp = outp;
1283         mstm->mgr.cbs = &nv50_mstm;
1284
1285         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1286                                            max_payloads, conn_base_id);
1287         if (ret)
1288                 return ret;
1289
1290         for (i = 0; i < max_payloads; i++) {
1291                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1292                                     i, &mstm->msto[i]);
1293                 if (ret)
1294                         return ret;
1295         }
1296
1297         return 0;
1298 }
1299
1300 /******************************************************************************
1301  * SOR
1302  *****************************************************************************/
1303 static void
1304 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1305                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1306 {
1307         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1308         struct nv50_core *core = disp->core;
1309
1310         if (!asyh) {
1311                 nv_encoder->ctrl &= ~BIT(head);
1312                 if (!(nv_encoder->ctrl & 0x0000000f))
1313                         nv_encoder->ctrl = 0;
1314         } else {
1315                 nv_encoder->ctrl |= proto << 8;
1316                 nv_encoder->ctrl |= BIT(head);
1317                 asyh->or.depth = depth;
1318         }
1319
1320         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1321 }
1322
1323 static void
1324 nv50_sor_disable(struct drm_encoder *encoder)
1325 {
1326         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1327         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1328
1329         nv_encoder->crtc = NULL;
1330
1331         if (nv_crtc) {
1332                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1333                 u8 pwr;
1334
1335                 if (aux) {
1336                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1337                         if (ret == 0) {
1338                                 pwr &= ~DP_SET_POWER_MASK;
1339                                 pwr |=  DP_SET_POWER_D3;
1340                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1341                         }
1342                 }
1343
1344                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1345                 nv50_audio_disable(encoder, nv_crtc);
1346                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1347                 nv50_outp_release(nv_encoder);
1348         }
1349 }
1350
1351 static void
1352 nv50_sor_enable(struct drm_encoder *encoder)
1353 {
1354         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1355         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1356         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1357         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1358         struct {
1359                 struct nv50_disp_mthd_v1 base;
1360                 struct nv50_disp_sor_lvds_script_v0 lvds;
1361         } lvds = {
1362                 .base.version = 1,
1363                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1364                 .base.hasht   = nv_encoder->dcb->hasht,
1365                 .base.hashm   = nv_encoder->dcb->hashm,
1366         };
1367         struct nv50_disp *disp = nv50_disp(encoder->dev);
1368         struct drm_device *dev = encoder->dev;
1369         struct nouveau_drm *drm = nouveau_drm(dev);
1370         struct nouveau_connector *nv_connector;
1371         struct nvbios *bios = &drm->vbios;
1372         u8 proto = 0xf;
1373         u8 depth = 0x0;
1374
1375         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1376         nv_encoder->crtc = encoder->crtc;
1377         nv50_outp_acquire(nv_encoder);
1378
1379         switch (nv_encoder->dcb->type) {
1380         case DCB_OUTPUT_TMDS:
1381                 if (nv_encoder->link & 1) {
1382                         proto = 0x1;
1383                         /* Only enable dual-link if:
1384                          *  - Need to (i.e. rate > 165MHz)
1385                          *  - DCB says we can
1386                          *  - Not an HDMI monitor, since there's no dual-link
1387                          *    on HDMI.
1388                          */
1389                         if (mode->clock >= 165000 &&
1390                             nv_encoder->dcb->duallink_possible &&
1391                             !drm_detect_hdmi_monitor(nv_connector->edid))
1392                                 proto |= 0x4;
1393                 } else {
1394                         proto = 0x2;
1395                 }
1396
1397                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1398                 break;
1399         case DCB_OUTPUT_LVDS:
1400                 proto = 0x0;
1401
1402                 if (bios->fp_no_ddc) {
1403                         if (bios->fp.dual_link)
1404                                 lvds.lvds.script |= 0x0100;
1405                         if (bios->fp.if_is_24bit)
1406                                 lvds.lvds.script |= 0x0200;
1407                 } else {
1408                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1409                                 if (((u8 *)nv_connector->edid)[121] == 2)
1410                                         lvds.lvds.script |= 0x0100;
1411                         } else
1412                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1413                                 lvds.lvds.script |= 0x0100;
1414                         }
1415
1416                         if (lvds.lvds.script & 0x0100) {
1417                                 if (bios->fp.strapless_is_24bit & 2)
1418                                         lvds.lvds.script |= 0x0200;
1419                         } else {
1420                                 if (bios->fp.strapless_is_24bit & 1)
1421                                         lvds.lvds.script |= 0x0200;
1422                         }
1423
1424                         if (nv_connector->base.display_info.bpc == 8)
1425                                 lvds.lvds.script |= 0x0200;
1426                 }
1427
1428                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1429                 break;
1430         case DCB_OUTPUT_DP:
1431                 if (nv_connector->base.display_info.bpc == 6)
1432                         depth = 0x2;
1433                 else
1434                 if (nv_connector->base.display_info.bpc == 8)
1435                         depth = 0x5;
1436                 else
1437                         depth = 0x6;
1438
1439                 if (nv_encoder->link & 1)
1440                         proto = 0x8;
1441                 else
1442                         proto = 0x9;
1443
1444                 nv50_audio_enable(encoder, mode);
1445                 break;
1446         default:
1447                 BUG();
1448                 break;
1449         }
1450
1451         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1452 }
1453
1454 static const struct drm_encoder_helper_funcs
1455 nv50_sor_help = {
1456         .atomic_check = nv50_outp_atomic_check,
1457         .enable = nv50_sor_enable,
1458         .disable = nv50_sor_disable,
1459 };
1460
1461 static void
1462 nv50_sor_destroy(struct drm_encoder *encoder)
1463 {
1464         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1465         nv50_mstm_del(&nv_encoder->dp.mstm);
1466         drm_encoder_cleanup(encoder);
1467         kfree(encoder);
1468 }
1469
1470 static const struct drm_encoder_funcs
1471 nv50_sor_func = {
1472         .destroy = nv50_sor_destroy,
1473 };
1474
1475 static int
1476 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1477 {
1478         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1479         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1480         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1481         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1482         struct nouveau_encoder *nv_encoder;
1483         struct drm_encoder *encoder;
1484         u8 ver, hdr, cnt, len;
1485         u32 data;
1486         int type, ret;
1487
1488         switch (dcbe->type) {
1489         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1490         case DCB_OUTPUT_TMDS:
1491         case DCB_OUTPUT_DP:
1492         default:
1493                 type = DRM_MODE_ENCODER_TMDS;
1494                 break;
1495         }
1496
1497         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1498         if (!nv_encoder)
1499                 return -ENOMEM;
1500         nv_encoder->dcb = dcbe;
1501         nv_encoder->update = nv50_sor_update;
1502
1503         encoder = to_drm_encoder(nv_encoder);
1504         encoder->possible_crtcs = dcbe->heads;
1505         encoder->possible_clones = 0;
1506         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1507                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1508         drm_encoder_helper_add(encoder, &nv50_sor_help);
1509
1510         drm_connector_attach_encoder(connector, encoder);
1511
1512         if (dcbe->type == DCB_OUTPUT_DP) {
1513                 struct nv50_disp *disp = nv50_disp(encoder->dev);
1514                 struct nvkm_i2c_aux *aux =
1515                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1516                 if (aux) {
1517                         if (disp->disp->object.oclass < GF110_DISP) {
1518                                 /* HW has no support for address-only
1519                                  * transactions, so we're required to
1520                                  * use custom I2C-over-AUX code.
1521                                  */
1522                                 nv_encoder->i2c = &aux->i2c;
1523                         } else {
1524                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1525                         }
1526                         nv_encoder->aux = aux;
1527                 }
1528
1529                 if ((data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1530                     ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1531                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1532                                             nv_connector->base.base.id,
1533                                             &nv_encoder->dp.mstm);
1534                         if (ret)
1535                                 return ret;
1536                 }
1537         } else {
1538                 struct nvkm_i2c_bus *bus =
1539                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1540                 if (bus)
1541                         nv_encoder->i2c = &bus->i2c;
1542         }
1543
1544         return 0;
1545 }
1546
1547 /******************************************************************************
1548  * PIOR
1549  *****************************************************************************/
1550 static int
1551 nv50_pior_atomic_check(struct drm_encoder *encoder,
1552                        struct drm_crtc_state *crtc_state,
1553                        struct drm_connector_state *conn_state)
1554 {
1555         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1556         if (ret)
1557                 return ret;
1558         crtc_state->adjusted_mode.clock *= 2;
1559         return 0;
1560 }
1561
1562 static void
1563 nv50_pior_disable(struct drm_encoder *encoder)
1564 {
1565         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1566         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1567         if (nv_encoder->crtc)
1568                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1569         nv_encoder->crtc = NULL;
1570         nv50_outp_release(nv_encoder);
1571 }
1572
1573 static void
1574 nv50_pior_enable(struct drm_encoder *encoder)
1575 {
1576         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1577         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1578         struct nouveau_connector *nv_connector;
1579         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1580         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1581         u8 owner = 1 << nv_crtc->index;
1582         u8 proto;
1583
1584         nv50_outp_acquire(nv_encoder);
1585
1586         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1587         switch (nv_connector->base.display_info.bpc) {
1588         case 10: asyh->or.depth = 0x6; break;
1589         case  8: asyh->or.depth = 0x5; break;
1590         case  6: asyh->or.depth = 0x2; break;
1591         default: asyh->or.depth = 0x0; break;
1592         }
1593
1594         switch (nv_encoder->dcb->type) {
1595         case DCB_OUTPUT_TMDS:
1596         case DCB_OUTPUT_DP:
1597                 proto = 0x0;
1598                 break;
1599         default:
1600                 BUG();
1601                 break;
1602         }
1603
1604         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1605         nv_encoder->crtc = encoder->crtc;
1606 }
1607
1608 static const struct drm_encoder_helper_funcs
1609 nv50_pior_help = {
1610         .atomic_check = nv50_pior_atomic_check,
1611         .enable = nv50_pior_enable,
1612         .disable = nv50_pior_disable,
1613 };
1614
1615 static void
1616 nv50_pior_destroy(struct drm_encoder *encoder)
1617 {
1618         drm_encoder_cleanup(encoder);
1619         kfree(encoder);
1620 }
1621
1622 static const struct drm_encoder_funcs
1623 nv50_pior_func = {
1624         .destroy = nv50_pior_destroy,
1625 };
1626
1627 static int
1628 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1629 {
1630         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1631         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1632         struct nvkm_i2c_bus *bus = NULL;
1633         struct nvkm_i2c_aux *aux = NULL;
1634         struct i2c_adapter *ddc;
1635         struct nouveau_encoder *nv_encoder;
1636         struct drm_encoder *encoder;
1637         int type;
1638
1639         switch (dcbe->type) {
1640         case DCB_OUTPUT_TMDS:
1641                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1642                 ddc  = bus ? &bus->i2c : NULL;
1643                 type = DRM_MODE_ENCODER_TMDS;
1644                 break;
1645         case DCB_OUTPUT_DP:
1646                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1647                 ddc  = aux ? &aux->i2c : NULL;
1648                 type = DRM_MODE_ENCODER_TMDS;
1649                 break;
1650         default:
1651                 return -ENODEV;
1652         }
1653
1654         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1655         if (!nv_encoder)
1656                 return -ENOMEM;
1657         nv_encoder->dcb = dcbe;
1658         nv_encoder->i2c = ddc;
1659         nv_encoder->aux = aux;
1660
1661         encoder = to_drm_encoder(nv_encoder);
1662         encoder->possible_crtcs = dcbe->heads;
1663         encoder->possible_clones = 0;
1664         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1665                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1666         drm_encoder_helper_add(encoder, &nv50_pior_help);
1667
1668         drm_connector_attach_encoder(connector, encoder);
1669         return 0;
1670 }
1671
1672 /******************************************************************************
1673  * Atomic
1674  *****************************************************************************/
1675
1676 static void
1677 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1678 {
1679         struct nouveau_drm *drm = nouveau_drm(state->dev);
1680         struct nv50_disp *disp = nv50_disp(drm->dev);
1681         struct nv50_core *core = disp->core;
1682         struct nv50_mstm *mstm;
1683         struct drm_encoder *encoder;
1684
1685         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1686
1687         drm_for_each_encoder(encoder, drm->dev) {
1688                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1689                         mstm = nouveau_encoder(encoder)->dp.mstm;
1690                         if (mstm && mstm->modified)
1691                                 nv50_mstm_prepare(mstm);
1692                 }
1693         }
1694
1695         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1696         core->func->update(core, interlock, true);
1697         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1698                                        disp->core->chan.base.device))
1699                 NV_ERROR(drm, "core notifier timeout\n");
1700
1701         drm_for_each_encoder(encoder, drm->dev) {
1702                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1703                         mstm = nouveau_encoder(encoder)->dp.mstm;
1704                         if (mstm && mstm->modified)
1705                                 nv50_mstm_cleanup(mstm);
1706                 }
1707         }
1708 }
1709
1710 static void
1711 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1712 {
1713         struct drm_plane_state *new_plane_state;
1714         struct drm_plane *plane;
1715         int i;
1716
1717         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1718                 struct nv50_wndw *wndw = nv50_wndw(plane);
1719                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1720                         if (wndw->func->update)
1721                                 wndw->func->update(wndw, interlock);
1722                 }
1723         }
1724 }
1725
1726 static void
1727 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1728 {
1729         struct drm_device *dev = state->dev;
1730         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1731         struct drm_crtc *crtc;
1732         struct drm_plane_state *new_plane_state;
1733         struct drm_plane *plane;
1734         struct nouveau_drm *drm = nouveau_drm(dev);
1735         struct nv50_disp *disp = nv50_disp(dev);
1736         struct nv50_atom *atom = nv50_atom(state);
1737         struct nv50_outp_atom *outp, *outt;
1738         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1739         int i;
1740
1741         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1742         drm_atomic_helper_wait_for_fences(dev, state, false);
1743         drm_atomic_helper_wait_for_dependencies(state);
1744         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1745
1746         if (atom->lock_core)
1747                 mutex_lock(&disp->mutex);
1748
1749         /* Disable head(s). */
1750         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1751                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1752                 struct nv50_head *head = nv50_head(crtc);
1753
1754                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1755                           asyh->clr.mask, asyh->set.mask);
1756                 if (old_crtc_state->active && !new_crtc_state->active)
1757                         drm_crtc_vblank_off(crtc);
1758
1759                 if (asyh->clr.mask) {
1760                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1761                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1762                 }
1763         }
1764
1765         /* Disable plane(s). */
1766         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1767                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1768                 struct nv50_wndw *wndw = nv50_wndw(plane);
1769
1770                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1771                           asyw->clr.mask, asyw->set.mask);
1772                 if (!asyw->clr.mask)
1773                         continue;
1774
1775                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1776         }
1777
1778         /* Disable output path(s). */
1779         list_for_each_entry(outp, &atom->outp, head) {
1780                 const struct drm_encoder_helper_funcs *help;
1781                 struct drm_encoder *encoder;
1782
1783                 encoder = outp->encoder;
1784                 help = encoder->helper_private;
1785
1786                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1787                           outp->clr.mask, outp->set.mask);
1788
1789                 if (outp->clr.mask) {
1790                         help->disable(encoder);
1791                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1792                         if (outp->flush_disable) {
1793                                 nv50_disp_atomic_commit_wndw(state, interlock);
1794                                 nv50_disp_atomic_commit_core(state, interlock);
1795                                 memset(interlock, 0x00, sizeof(interlock));
1796                         }
1797                 }
1798         }
1799
1800         /* Flush disable. */
1801         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1802                 if (atom->flush_disable) {
1803                         nv50_disp_atomic_commit_wndw(state, interlock);
1804                         nv50_disp_atomic_commit_core(state, interlock);
1805                         memset(interlock, 0x00, sizeof(interlock));
1806                 }
1807         }
1808
1809         /* Update output path(s). */
1810         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1811                 const struct drm_encoder_helper_funcs *help;
1812                 struct drm_encoder *encoder;
1813
1814                 encoder = outp->encoder;
1815                 help = encoder->helper_private;
1816
1817                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1818                           outp->set.mask, outp->clr.mask);
1819
1820                 if (outp->set.mask) {
1821                         help->enable(encoder);
1822                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1823                 }
1824
1825                 list_del(&outp->head);
1826                 kfree(outp);
1827         }
1828
1829         /* Update head(s). */
1830         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1831                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1832                 struct nv50_head *head = nv50_head(crtc);
1833
1834                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1835                           asyh->set.mask, asyh->clr.mask);
1836
1837                 if (asyh->set.mask) {
1838                         nv50_head_flush_set(head, asyh);
1839                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1840                 }
1841
1842                 if (new_crtc_state->active) {
1843                         if (!old_crtc_state->active)
1844                                 drm_crtc_vblank_on(crtc);
1845                         if (new_crtc_state->event)
1846                                 drm_crtc_vblank_get(crtc);
1847                 }
1848         }
1849
1850         /* Update plane(s). */
1851         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1852                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1853                 struct nv50_wndw *wndw = nv50_wndw(plane);
1854
1855                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1856                           asyw->set.mask, asyw->clr.mask);
1857                 if ( !asyw->set.mask &&
1858                     (!asyw->clr.mask || atom->flush_disable))
1859                         continue;
1860
1861                 nv50_wndw_flush_set(wndw, interlock, asyw);
1862         }
1863
1864         /* Flush update. */
1865         nv50_disp_atomic_commit_wndw(state, interlock);
1866
1867         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1868                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1869                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
1870                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
1871                     !atom->state.legacy_cursor_update)
1872                         nv50_disp_atomic_commit_core(state, interlock);
1873                 else
1874                         disp->core->func->update(disp->core, interlock, false);
1875         }
1876
1877         if (atom->lock_core)
1878                 mutex_unlock(&disp->mutex);
1879
1880         /* Wait for HW to signal completion. */
1881         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1882                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1883                 struct nv50_wndw *wndw = nv50_wndw(plane);
1884                 int ret = nv50_wndw_wait_armed(wndw, asyw);
1885                 if (ret)
1886                         NV_ERROR(drm, "%s: timeout\n", plane->name);
1887         }
1888
1889         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1890                 if (new_crtc_state->event) {
1891                         unsigned long flags;
1892                         /* Get correct count/ts if racing with vblank irq */
1893                         if (new_crtc_state->active)
1894                                 drm_crtc_accurate_vblank_count(crtc);
1895                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
1896                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1897                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1898
1899                         new_crtc_state->event = NULL;
1900                         if (new_crtc_state->active)
1901                                 drm_crtc_vblank_put(crtc);
1902                 }
1903         }
1904
1905         drm_atomic_helper_commit_hw_done(state);
1906         drm_atomic_helper_cleanup_planes(dev, state);
1907         drm_atomic_helper_commit_cleanup_done(state);
1908         drm_atomic_state_put(state);
1909 }
1910
1911 static void
1912 nv50_disp_atomic_commit_work(struct work_struct *work)
1913 {
1914         struct drm_atomic_state *state =
1915                 container_of(work, typeof(*state), commit_work);
1916         nv50_disp_atomic_commit_tail(state);
1917 }
1918
1919 static int
1920 nv50_disp_atomic_commit(struct drm_device *dev,
1921                         struct drm_atomic_state *state, bool nonblock)
1922 {
1923         struct nouveau_drm *drm = nouveau_drm(dev);
1924         struct drm_plane_state *new_plane_state;
1925         struct drm_plane *plane;
1926         struct drm_crtc *crtc;
1927         bool active = false;
1928         int ret, i;
1929
1930         ret = pm_runtime_get_sync(dev->dev);
1931         if (ret < 0 && ret != -EACCES)
1932                 return ret;
1933
1934         ret = drm_atomic_helper_setup_commit(state, nonblock);
1935         if (ret)
1936                 goto done;
1937
1938         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
1939
1940         ret = drm_atomic_helper_prepare_planes(dev, state);
1941         if (ret)
1942                 goto done;
1943
1944         if (!nonblock) {
1945                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
1946                 if (ret)
1947                         goto err_cleanup;
1948         }
1949
1950         ret = drm_atomic_helper_swap_state(state, true);
1951         if (ret)
1952                 goto err_cleanup;
1953
1954         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1955                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1956                 struct nv50_wndw *wndw = nv50_wndw(plane);
1957
1958                 if (asyw->set.image)
1959                         nv50_wndw_ntfy_enable(wndw, asyw);
1960         }
1961
1962         drm_atomic_state_get(state);
1963
1964         if (nonblock)
1965                 queue_work(system_unbound_wq, &state->commit_work);
1966         else
1967                 nv50_disp_atomic_commit_tail(state);
1968
1969         drm_for_each_crtc(crtc, dev) {
1970                 if (crtc->state->active) {
1971                         if (!drm->have_disp_power_ref) {
1972                                 drm->have_disp_power_ref = true;
1973                                 return 0;
1974                         }
1975                         active = true;
1976                         break;
1977                 }
1978         }
1979
1980         if (!active && drm->have_disp_power_ref) {
1981                 pm_runtime_put_autosuspend(dev->dev);
1982                 drm->have_disp_power_ref = false;
1983         }
1984
1985 err_cleanup:
1986         if (ret)
1987                 drm_atomic_helper_cleanup_planes(dev, state);
1988 done:
1989         pm_runtime_put_autosuspend(dev->dev);
1990         return ret;
1991 }
1992
1993 static struct nv50_outp_atom *
1994 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
1995 {
1996         struct nv50_outp_atom *outp;
1997
1998         list_for_each_entry(outp, &atom->outp, head) {
1999                 if (outp->encoder == encoder)
2000                         return outp;
2001         }
2002
2003         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2004         if (!outp)
2005                 return ERR_PTR(-ENOMEM);
2006
2007         list_add(&outp->head, &atom->outp);
2008         outp->encoder = encoder;
2009         return outp;
2010 }
2011
2012 static int
2013 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2014                                 struct drm_connector_state *old_connector_state)
2015 {
2016         struct drm_encoder *encoder = old_connector_state->best_encoder;
2017         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2018         struct drm_crtc *crtc;
2019         struct nv50_outp_atom *outp;
2020
2021         if (!(crtc = old_connector_state->crtc))
2022                 return 0;
2023
2024         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2025         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2026         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2027                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2028                 if (IS_ERR(outp))
2029                         return PTR_ERR(outp);
2030
2031                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2032                         outp->flush_disable = true;
2033                         atom->flush_disable = true;
2034                 }
2035                 outp->clr.ctrl = true;
2036                 atom->lock_core = true;
2037         }
2038
2039         return 0;
2040 }
2041
2042 static int
2043 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2044                                 struct drm_connector_state *connector_state)
2045 {
2046         struct drm_encoder *encoder = connector_state->best_encoder;
2047         struct drm_crtc_state *new_crtc_state;
2048         struct drm_crtc *crtc;
2049         struct nv50_outp_atom *outp;
2050
2051         if (!(crtc = connector_state->crtc))
2052                 return 0;
2053
2054         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2055         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2056                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2057                 if (IS_ERR(outp))
2058                         return PTR_ERR(outp);
2059
2060                 outp->set.ctrl = true;
2061                 atom->lock_core = true;
2062         }
2063
2064         return 0;
2065 }
2066
2067 static int
2068 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2069 {
2070         struct nv50_atom *atom = nv50_atom(state);
2071         struct drm_connector_state *old_connector_state, *new_connector_state;
2072         struct drm_connector *connector;
2073         struct drm_crtc_state *new_crtc_state;
2074         struct drm_crtc *crtc;
2075         int ret, i;
2076
2077         /* We need to handle colour management on a per-plane basis. */
2078         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2079                 if (new_crtc_state->color_mgmt_changed) {
2080                         ret = drm_atomic_add_affected_planes(state, crtc);
2081                         if (ret)
2082                                 return ret;
2083                 }
2084         }
2085
2086         ret = drm_atomic_helper_check(dev, state);
2087         if (ret)
2088                 return ret;
2089
2090         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2091                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2092                 if (ret)
2093                         return ret;
2094
2095                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2096                 if (ret)
2097                         return ret;
2098         }
2099
2100         return 0;
2101 }
2102
2103 static void
2104 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2105 {
2106         struct nv50_atom *atom = nv50_atom(state);
2107         struct nv50_outp_atom *outp, *outt;
2108
2109         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2110                 list_del(&outp->head);
2111                 kfree(outp);
2112         }
2113
2114         drm_atomic_state_default_clear(state);
2115 }
2116
2117 static void
2118 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2119 {
2120         struct nv50_atom *atom = nv50_atom(state);
2121         drm_atomic_state_default_release(&atom->state);
2122         kfree(atom);
2123 }
2124
2125 static struct drm_atomic_state *
2126 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2127 {
2128         struct nv50_atom *atom;
2129         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2130             drm_atomic_state_init(dev, &atom->state) < 0) {
2131                 kfree(atom);
2132                 return NULL;
2133         }
2134         INIT_LIST_HEAD(&atom->outp);
2135         return &atom->state;
2136 }
2137
2138 static const struct drm_mode_config_funcs
2139 nv50_disp_func = {
2140         .fb_create = nouveau_user_framebuffer_create,
2141         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2142         .atomic_check = nv50_disp_atomic_check,
2143         .atomic_commit = nv50_disp_atomic_commit,
2144         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2145         .atomic_state_clear = nv50_disp_atomic_state_clear,
2146         .atomic_state_free = nv50_disp_atomic_state_free,
2147 };
2148
2149 /******************************************************************************
2150  * Init
2151  *****************************************************************************/
2152
2153 void
2154 nv50_display_fini(struct drm_device *dev)
2155 {
2156         struct nouveau_encoder *nv_encoder;
2157         struct drm_encoder *encoder;
2158         struct drm_plane *plane;
2159
2160         drm_for_each_plane(plane, dev) {
2161                 struct nv50_wndw *wndw = nv50_wndw(plane);
2162                 if (plane->funcs != &nv50_wndw)
2163                         continue;
2164                 nv50_wndw_fini(wndw);
2165         }
2166
2167         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2168                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2169                         nv_encoder = nouveau_encoder(encoder);
2170                         nv50_mstm_fini(nv_encoder->dp.mstm);
2171                 }
2172         }
2173 }
2174
2175 int
2176 nv50_display_init(struct drm_device *dev)
2177 {
2178         struct nv50_core *core = nv50_disp(dev)->core;
2179         struct drm_encoder *encoder;
2180         struct drm_plane *plane;
2181
2182         core->func->init(core);
2183
2184         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2185                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2186                         struct nouveau_encoder *nv_encoder =
2187                                 nouveau_encoder(encoder);
2188                         nv50_mstm_init(nv_encoder->dp.mstm);
2189                 }
2190         }
2191
2192         drm_for_each_plane(plane, dev) {
2193                 struct nv50_wndw *wndw = nv50_wndw(plane);
2194                 if (plane->funcs != &nv50_wndw)
2195                         continue;
2196                 nv50_wndw_init(wndw);
2197         }
2198
2199         return 0;
2200 }
2201
2202 void
2203 nv50_display_destroy(struct drm_device *dev)
2204 {
2205         struct nv50_disp *disp = nv50_disp(dev);
2206
2207         nv50_core_del(&disp->core);
2208
2209         nouveau_bo_unmap(disp->sync);
2210         if (disp->sync)
2211                 nouveau_bo_unpin(disp->sync);
2212         nouveau_bo_ref(NULL, &disp->sync);
2213
2214         nouveau_display(dev)->priv = NULL;
2215         kfree(disp);
2216 }
2217
2218 int
2219 nv50_display_create(struct drm_device *dev)
2220 {
2221         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2222         struct nouveau_drm *drm = nouveau_drm(dev);
2223         struct dcb_table *dcb = &drm->vbios.dcb;
2224         struct drm_connector *connector, *tmp;
2225         struct nv50_disp *disp;
2226         struct dcb_output *dcbe;
2227         int crtcs, ret, i;
2228
2229         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2230         if (!disp)
2231                 return -ENOMEM;
2232
2233         mutex_init(&disp->mutex);
2234
2235         nouveau_display(dev)->priv = disp;
2236         nouveau_display(dev)->dtor = nv50_display_destroy;
2237         nouveau_display(dev)->init = nv50_display_init;
2238         nouveau_display(dev)->fini = nv50_display_fini;
2239         disp->disp = &nouveau_display(dev)->disp;
2240         dev->mode_config.funcs = &nv50_disp_func;
2241         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2242
2243         /* small shared memory area we use for notifiers and semaphores */
2244         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2245                              0, 0x0000, NULL, NULL, &disp->sync);
2246         if (!ret) {
2247                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2248                 if (!ret) {
2249                         ret = nouveau_bo_map(disp->sync);
2250                         if (ret)
2251                                 nouveau_bo_unpin(disp->sync);
2252                 }
2253                 if (ret)
2254                         nouveau_bo_ref(NULL, &disp->sync);
2255         }
2256
2257         if (ret)
2258                 goto out;
2259
2260         /* allocate master evo channel */
2261         ret = nv50_core_new(drm, &disp->core);
2262         if (ret)
2263                 goto out;
2264
2265         /* create crtc objects to represent the hw heads */
2266         if (disp->disp->object.oclass >= GV100_DISP)
2267                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2268         else
2269         if (disp->disp->object.oclass >= GF110_DISP)
2270                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2271         else
2272                 crtcs = 0x3;
2273
2274         for (i = 0; i < fls(crtcs); i++) {
2275                 if (!(crtcs & (1 << i)))
2276                         continue;
2277                 ret = nv50_head_create(dev, i);
2278                 if (ret)
2279                         goto out;
2280         }
2281
2282         /* create encoder/connector objects based on VBIOS DCB table */
2283         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2284                 connector = nouveau_connector_create(dev, dcbe->connector);
2285                 if (IS_ERR(connector))
2286                         continue;
2287
2288                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2289                         switch (dcbe->type) {
2290                         case DCB_OUTPUT_TMDS:
2291                         case DCB_OUTPUT_LVDS:
2292                         case DCB_OUTPUT_DP:
2293                                 ret = nv50_sor_create(connector, dcbe);
2294                                 break;
2295                         case DCB_OUTPUT_ANALOG:
2296                                 ret = nv50_dac_create(connector, dcbe);
2297                                 break;
2298                         default:
2299                                 ret = -ENODEV;
2300                                 break;
2301                         }
2302                 } else {
2303                         ret = nv50_pior_create(connector, dcbe);
2304                 }
2305
2306                 if (ret) {
2307                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2308                                      dcbe->location, dcbe->type,
2309                                      ffs(dcbe->or) - 1, ret);
2310                         ret = 0;
2311                 }
2312         }
2313
2314         /* cull any connectors we created that don't have an encoder */
2315         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2316                 if (connector->encoder_ids[0])
2317                         continue;
2318
2319                 NV_WARN(drm, "%s has no encoders, removing\n",
2320                         connector->name);
2321                 connector->funcs->destroy(connector);
2322         }
2323
2324         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2325         dev->vblank_disable_immediate = true;
2326
2327 out:
2328         if (ret)
2329                 nv50_display_destroy(dev);
2330         return ret;
2331 }