drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29 #include "handles.h"
  30
  31 #include <linux/dma-mapping.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/component.h>
  34
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include <drm/drm_fb_helper.h>
  39 #include <drm/drm_plane_helper.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include <drm/drm_scdc_helper.h>
  42 #include <drm/drm_vblank.h>
  43
  44 #include <nvif/push507c.h>
  45
  46 #include <nvif/class.h>
  47 #include <nvif/cl0002.h>
  48 #include <nvif/cl5070.h>
  49 #include <nvif/cl507d.h>
  50 #include <nvif/event.h>
  51 #include <nvif/timer.h>
  52
  53 #include <nvhw/class/cl507c.h>
  54 #include <nvhw/class/cl507d.h>
  55 #include <nvhw/class/cl837d.h>
  56 #include <nvhw/class/cl887d.h>
  57 #include <nvhw/class/cl907d.h>
  58 #include <nvhw/class/cl917d.h>
  59
  60 #include "nouveau_drv.h"
  61 #include "nouveau_dma.h"
  62 #include "nouveau_gem.h"
  63 #include "nouveau_connector.h"
  64 #include "nouveau_encoder.h"
  65 #include "nouveau_fence.h"
  66 #include "nouveau_fbcon.h"
  67
  68 #include <subdev/bios/dp.h>
  69
  70 /******************************************************************************
  71  * EVO channel
  72  *****************************************************************************/
  73
  74 static int
  75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  76                  const s32 *oclass, u8 head, void *data, u32 size,
  77                  struct nv50_chan *chan)
  78 {
  79         struct nvif_sclass *sclass;
  80         int ret, i, n;
  81
  82         chan->device = device;
  83
  84         ret = n = nvif_object_sclass_get(disp, &sclass);
  85         if (ret < 0)
  86                 return ret;
  87
  88         while (oclass[0]) {
  89                 for (i = 0; i < n; i++) {
  90                         if (sclass[i].oclass == oclass[0]) {
  91                                 ret = nvif_object_ctor(disp, "kmsChan", 0,
  92                                                        oclass[0], data, size,
  93                                                        &chan->user);
  94                                 if (ret == 0)
  95                                         nvif_object_map(&chan->user, NULL, 0);
  96                                 nvif_object_sclass_put(&sclass);
  97                                 return ret;
  98                         }
  99                 }
 100                 oclass++;
 101         }
 102
 103         nvif_object_sclass_put(&sclass);
 104         return -ENOSYS;
 105 }
 106
 107 static void
 108 nv50_chan_destroy(struct nv50_chan *chan)
 109 {
 110         nvif_object_dtor(&chan->user);
 111 }
 112
 113 /******************************************************************************
 114  * DMA EVO channel
 115  *****************************************************************************/
 116
 117 void
 118 nv50_dmac_destroy(struct nv50_dmac *dmac)
 119 {
 120         nvif_object_dtor(&dmac->vram);
 121         nvif_object_dtor(&dmac->sync);
 122
 123         nv50_chan_destroy(&dmac->base);
 124
 125         nvif_mem_dtor(&dmac->_push.mem);
 126 }
 127
 128 static void
 129 nv50_dmac_kick(struct nvif_push *push)
 130 {
 131         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 132
 133         dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
 134         if (dmac->put != dmac->cur) {
 135                 /* Push buffer fetches are not coherent with BAR1, we need to ensure
 136                  * writes have been flushed right through to VRAM before writing PUT.
 137                  */
 138                 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
 139                         struct nvif_device *device = dmac->base.device;
 140                         nvif_wr32(&device->object, 0x070000, 0x00000001);
 141                         nvif_msec(device, 2000,
 142                                 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 143                                         break;
 144                         );
 145                 }
 146
 147                 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
 148                 dmac->put = dmac->cur;
 149         }
 150
 151         push->bgn = push->cur;
 152 }
 153
 154 static int
 155 nv50_dmac_free(struct nv50_dmac *dmac)
 156 {
 157         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 158         if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
 159                 return get - dmac->cur - 5;
 160         return dmac->max - dmac->cur;
 161 }
 162
 163 static int
 164 nv50_dmac_wind(struct nv50_dmac *dmac)
 165 {
 166         /* Wait for GET to depart from the beginning of the push buffer to
 167          * prevent writing PUT == GET, which would be ignored by HW.
 168          */
 169         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 170         if (get == 0) {
 171                 /* Corner-case, HW idle, but non-committed work pending. */
 172                 if (dmac->put == 0)
 173                         nv50_dmac_kick(dmac->push);
 174
 175                 if (nvif_msec(dmac->base.device, 2000,
 176                         if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
 177                                 break;
 178                 ) < 0)
 179                         return -ETIMEDOUT;
 180         }
 181
 182         PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
 183         dmac->cur = 0;
 184         return 0;
 185 }
 186
 187 static int
 188 nv50_dmac_wait(struct nvif_push *push, u32 size)
 189 {
 190         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 191         int free;
 192
 193         if (WARN_ON(size > dmac->max))
 194                 return -EINVAL;
 195
 196         dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
 197         if (dmac->cur + size >= dmac->max) {
 198                 int ret = nv50_dmac_wind(dmac);
 199                 if (ret)
 200                         return ret;
 201
 202                 push->cur = dmac->_push.mem.object.map.ptr;
 203                 push->cur = push->cur + dmac->cur;
 204                 nv50_dmac_kick(push);
 205         }
 206
 207         if (nvif_msec(dmac->base.device, 2000,
 208                 if ((free = nv50_dmac_free(dmac)) >= size)
 209                         break;
 210         ) < 0) {
 211                 WARN_ON(1);
 212                 return -ETIMEDOUT;
 213         }
 214
 215         push->bgn = dmac->_push.mem.object.map.ptr;
 216         push->bgn = push->bgn + dmac->cur;
 217         push->cur = push->bgn;
 218         push->end = push->cur + free;
 219         return 0;
 220 }
 221
 222 int
 223 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 224                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 225                  struct nv50_dmac *dmac)
 226 {
 227         struct nouveau_cli *cli = (void *)device->object.client;
 228         struct nv50_disp_core_channel_dma_v0 *args = data;
 229         u8 type = NVIF_MEM_COHERENT;
 230         int ret;
 231
 232         mutex_init(&dmac->lock);
 233
 234         /* Pascal added support for 47-bit physical addresses, but some
 235          * parts of EVO still only accept 40-bit PAs.
 236          *
 237          * To avoid issues on systems with large amounts of RAM, and on
 238          * systems where an IOMMU maps pages at a high address, we need
 239          * to allocate push buffers in VRAM instead.
 240          *
 241          * This appears to match NVIDIA's behaviour on Pascal.
 242          */
 243         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 244                 type |= NVIF_MEM_VRAM;
 245
 246         ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
 247                                 &dmac->_push.mem);
 248         if (ret)
 249                 return ret;
 250
 251         dmac->ptr = dmac->_push.mem.object.map.ptr;
 252         dmac->_push.wait = nv50_dmac_wait;
 253         dmac->_push.kick = nv50_dmac_kick;
 254         dmac->push = &dmac->_push;
 255         dmac->push->bgn = dmac->_push.mem.object.map.ptr;
 256         dmac->push->cur = dmac->push->bgn;
 257         dmac->push->end = dmac->push->bgn;
 258         dmac->max = 0x1000/4 - 1;
 259
 260         args->pushbuf = nvif_handle(&dmac->_push.mem.object);
 261
 262         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 263                                &dmac->base);
 264         if (ret)
 265                 return ret;
 266
 267         if (!syncbuf)
 268                 return 0;
 269
 270         ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
 271                                NV_DMA_IN_MEMORY,
 272                                &(struct nv_dma_v0) {
 273                                         .target = NV_DMA_V0_TARGET_VRAM,
 274                                         .access = NV_DMA_V0_ACCESS_RDWR,
 275                                         .start = syncbuf + 0x0000,
 276                                         .limit = syncbuf + 0x0fff,
 277                                }, sizeof(struct nv_dma_v0),
 278                                &dmac->sync);
 279         if (ret)
 280                 return ret;
 281
 282         ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
 283                                NV_DMA_IN_MEMORY,
 284                                &(struct nv_dma_v0) {
 285                                         .target = NV_DMA_V0_TARGET_VRAM,
 286                                         .access = NV_DMA_V0_ACCESS_RDWR,
 287                                         .start = 0,
 288                                         .limit = device->info.ram_user - 1,
 289                                }, sizeof(struct nv_dma_v0),
 290                                &dmac->vram);
 291         if (ret)
 292                 return ret;
 293
 294         return ret;
 295 }
 296
 297 /******************************************************************************
 298  * Output path helpers
 299  *****************************************************************************/
 300 static void
 301 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 302 {
 303         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 304         struct {
 305                 struct nv50_disp_mthd_v1 base;
 306         } args = {
 307                 .base.version = 1,
 308                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 309                 .base.hasht  = nv_encoder->dcb->hasht,
 310                 .base.hashm  = nv_encoder->dcb->hashm,
 311         };
 312
 313         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 314         nv_encoder->or = -1;
 315         nv_encoder->link = 0;
 316 }
 317
 318 static int
 319 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
 320 {
 321         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 322         struct nv50_disp *disp = nv50_disp(drm->dev);
 323         struct {
 324                 struct nv50_disp_mthd_v1 base;
 325                 struct nv50_disp_acquire_v0 info;
 326         } args = {
 327                 .base.version = 1,
 328                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 329                 .base.hasht  = nv_encoder->dcb->hasht,
 330                 .base.hashm  = nv_encoder->dcb->hashm,
 331                 .info.hda = hda,
 332         };
 333         int ret;
 334
 335         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 336         if (ret) {
 337                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 338                 return ret;
 339         }
 340
 341         nv_encoder->or = args.info.or;
 342         nv_encoder->link = args.info.link;
 343         return 0;
 344 }
 345
 346 static int
 347 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 348                             struct drm_crtc_state *crtc_state,
 349                             struct drm_connector_state *conn_state,
 350                             struct drm_display_mode *native_mode)
 351 {
 352         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 353         struct drm_display_mode *mode = &crtc_state->mode;
 354         struct drm_connector *connector = conn_state->connector;
 355         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 356         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 357
 358         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 359         asyc->scaler.full = false;
 360         if (!native_mode)
 361                 return 0;
 362
 363         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 364                 switch (connector->connector_type) {
 365                 case DRM_MODE_CONNECTOR_LVDS:
 366                 case DRM_MODE_CONNECTOR_eDP:
 367                         /* Don't force scaler for EDID modes with
 368                          * same size as the native one (e.g. different
 369                          * refresh rate)
 370                          */
 371                         if (mode->hdisplay == native_mode->hdisplay &&
 372                             mode->vdisplay == native_mode->vdisplay &&
 373                             mode->type & DRM_MODE_TYPE_DRIVER)
 374                                 break;
 375                         mode = native_mode;
 376                         asyc->scaler.full = true;
 377                         break;
 378                 default:
 379                         break;
 380                 }
 381         } else {
 382                 mode = native_mode;
 383         }
 384
 385         if (!drm_mode_equal(adjusted_mode, mode)) {
 386                 drm_mode_copy(adjusted_mode, mode);
 387                 crtc_state->mode_changed = true;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int
 394 nv50_outp_atomic_check(struct drm_encoder *encoder,
 395                        struct drm_crtc_state *crtc_state,
 396                        struct drm_connector_state *conn_state)
 397 {
 398         struct drm_connector *connector = conn_state->connector;
 399         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 400         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 401         int ret;
 402
 403         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 404                                           nv_connector->native_mode);
 405         if (ret)
 406                 return ret;
 407
 408         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 409                 asyh->or.bpc = connector->display_info.bpc;
 410
 411         return 0;
 412 }
 413
 414 struct nouveau_connector *
 415 nv50_outp_get_new_connector(struct nouveau_encoder *outp,
 416                             struct drm_atomic_state *state)
 417 {
 418         struct drm_connector *connector;
 419         struct drm_connector_state *connector_state;
 420         struct drm_encoder *encoder = to_drm_encoder(outp);
 421         int i;
 422
 423         for_each_new_connector_in_state(state, connector, connector_state, i) {
 424                 if (connector_state->best_encoder == encoder)
 425                         return nouveau_connector(connector);
 426         }
 427
 428         return NULL;
 429 }
 430
 431 struct nouveau_connector *
 432 nv50_outp_get_old_connector(struct nouveau_encoder *outp,
 433                             struct drm_atomic_state *state)
 434 {
 435         struct drm_connector *connector;
 436         struct drm_connector_state *connector_state;
 437         struct drm_encoder *encoder = to_drm_encoder(outp);
 438         int i;
 439
 440         for_each_old_connector_in_state(state, connector, connector_state, i) {
 441                 if (connector_state->best_encoder == encoder)
 442                         return nouveau_connector(connector);
 443         }
 444
 445         return NULL;
 446 }
 447
 448 /******************************************************************************
 449  * DAC
 450  *****************************************************************************/
 451 static void
 452 nv50_dac_disable(struct drm_encoder *encoder)
 453 {
 454         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 455         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 456         const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
 457         if (nv_encoder->crtc)
 458                 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
 459         nv_encoder->crtc = NULL;
 460         nv50_outp_release(nv_encoder);
 461 }
 462
 463 static void
 464 nv50_dac_enable(struct drm_encoder *encoder)
 465 {
 466         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 467         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 468         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 469         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 470         u32 ctrl = 0;
 471
 472         switch (nv_crtc->index) {
 473         case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
 474         case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
 475         case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
 476         case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
 477         default:
 478                 WARN_ON(1);
 479                 break;
 480         }
 481
 482         ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
 483
 484         nv50_outp_acquire(nv_encoder, false);
 485
 486         core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
 487         asyh->or.depth = 0;
 488
 489         nv_encoder->crtc = encoder->crtc;
 490 }
 491
 492 static enum drm_connector_status
 493 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 494 {
 495         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 496         struct nv50_disp *disp = nv50_disp(encoder->dev);
 497         struct {
 498                 struct nv50_disp_mthd_v1 base;
 499                 struct nv50_disp_dac_load_v0 load;
 500         } args = {
 501                 .base.version = 1,
 502                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 503                 .base.hasht  = nv_encoder->dcb->hasht,
 504                 .base.hashm  = nv_encoder->dcb->hashm,
 505         };
 506         int ret;
 507
 508         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 509         if (args.load.data == 0)
 510                 args.load.data = 340;
 511
 512         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 513         if (ret || !args.load.load)
 514                 return connector_status_disconnected;
 515
 516         return connector_status_connected;
 517 }
 518
 519 static const struct drm_encoder_helper_funcs
 520 nv50_dac_help = {
 521         .atomic_check = nv50_outp_atomic_check,
 522         .enable = nv50_dac_enable,
 523         .disable = nv50_dac_disable,
 524         .detect = nv50_dac_detect
 525 };
 526
 527 static void
 528 nv50_dac_destroy(struct drm_encoder *encoder)
 529 {
 530         drm_encoder_cleanup(encoder);
 531         kfree(encoder);
 532 }
 533
 534 static const struct drm_encoder_funcs
 535 nv50_dac_func = {
 536         .destroy = nv50_dac_destroy,
 537 };
 538
 539 static int
 540 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 541 {
 542         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 543         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 544         struct nvkm_i2c_bus *bus;
 545         struct nouveau_encoder *nv_encoder;
 546         struct drm_encoder *encoder;
 547         int type = DRM_MODE_ENCODER_DAC;
 548
 549         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 550         if (!nv_encoder)
 551                 return -ENOMEM;
 552         nv_encoder->dcb = dcbe;
 553
 554         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 555         if (bus)
 556                 nv_encoder->i2c = &bus->i2c;
 557
 558         encoder = to_drm_encoder(nv_encoder);
 559         encoder->possible_crtcs = dcbe->heads;
 560         encoder->possible_clones = 0;
 561         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 562                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 563         drm_encoder_helper_add(encoder, &nv50_dac_help);
 564
 565         drm_connector_attach_encoder(connector, encoder);
 566         return 0;
 567 }
 568
 569 /*
 570  * audio component binding for ELD notification
 571  */
 572 static void
 573 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 574                                 int dev_id)
 575 {
 576         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 577                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 578                                                  port, dev_id);
 579 }
 580
 581 static int
 582 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 583                              bool *enabled, unsigned char *buf, int max_bytes)
 584 {
 585         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 586         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 587         struct drm_encoder *encoder;
 588         struct nouveau_encoder *nv_encoder;
 589         struct drm_connector *connector;
 590         struct nouveau_crtc *nv_crtc;
 591         struct drm_connector_list_iter conn_iter;
 592         int ret = 0;
 593
 594         *enabled = false;
 595
 596         drm_for_each_encoder(encoder, drm->dev) {
 597                 struct nouveau_connector *nv_connector = NULL;
 598
 599                 nv_encoder = nouveau_encoder(encoder);
 600
 601                 drm_connector_list_iter_begin(drm_dev, &conn_iter);
 602                 drm_for_each_connector_iter(connector, &conn_iter) {
 603                         if (connector->state->best_encoder == encoder) {
 604                                 nv_connector = nouveau_connector(connector);
 605                                 break;
 606                         }
 607                 }
 608                 drm_connector_list_iter_end(&conn_iter);
 609                 if (!nv_connector)
 610                         continue;
 611
 612                 nv_crtc = nouveau_crtc(encoder->crtc);
 613                 if (!nv_crtc || nv_encoder->or != port ||
 614                     nv_crtc->index != dev_id)
 615                         continue;
 616                 *enabled = nv_encoder->audio;
 617                 if (*enabled) {
 618                         ret = drm_eld_size(nv_connector->base.eld);
 619                         memcpy(buf, nv_connector->base.eld,
 620                                min(max_bytes, ret));
 621                 }
 622                 break;
 623         }
 624
 625         return ret;
 626 }
 627
 628 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 629         .get_eld = nv50_audio_component_get_eld,
 630 };
 631
 632 static int
 633 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 634                           void *data)
 635 {
 636         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 637         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 638         struct drm_audio_component *acomp = data;
 639
 640         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 641                 return -ENOMEM;
 642
 643         drm_modeset_lock_all(drm_dev);
 644         acomp->ops = &nv50_audio_component_ops;
 645         acomp->dev = kdev;
 646         drm->audio.component = acomp;
 647         drm_modeset_unlock_all(drm_dev);
 648         return 0;
 649 }
 650
 651 static void
 652 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 653                             void *data)
 654 {
 655         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 656         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 657         struct drm_audio_component *acomp = data;
 658
 659         drm_modeset_lock_all(drm_dev);
 660         drm->audio.component = NULL;
 661         acomp->ops = NULL;
 662         acomp->dev = NULL;
 663         drm_modeset_unlock_all(drm_dev);
 664 }
 665
 666 static const struct component_ops nv50_audio_component_bind_ops = {
 667         .bind   = nv50_audio_component_bind,
 668         .unbind = nv50_audio_component_unbind,
 669 };
 670
 671 static void
 672 nv50_audio_component_init(struct nouveau_drm *drm)
 673 {
 674         if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 675                 drm->audio.component_registered = true;
 676 }
 677
 678 static void
 679 nv50_audio_component_fini(struct nouveau_drm *drm)
 680 {
 681         if (drm->audio.component_registered) {
 682                 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 683                 drm->audio.component_registered = false;
 684         }
 685 }
 686
 687 /******************************************************************************
 688  * Audio
 689  *****************************************************************************/
 690 static void
 691 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 692 {
 693         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 694         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 695         struct nv50_disp *disp = nv50_disp(encoder->dev);
 696         struct {
 697                 struct nv50_disp_mthd_v1 base;
 698                 struct nv50_disp_sor_hda_eld_v0 eld;
 699         } args = {
 700                 .base.version = 1,
 701                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 702                 .base.hasht   = nv_encoder->dcb->hasht,
 703                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 704                                 (0x0100 << nv_crtc->index),
 705         };
 706
 707         if (!nv_encoder->audio)
 708                 return;
 709
 710         nv_encoder->audio = false;
 711         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 712
 713         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 714                                         nv_crtc->index);
 715 }
 716
 717 static void
 718 nv50_audio_enable(struct drm_encoder *encoder, struct drm_atomic_state *state,
 719                   struct drm_display_mode *mode)
 720 {
 721         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 722         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 723         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 724         struct nouveau_connector *nv_connector;
 725         struct nv50_disp *disp = nv50_disp(encoder->dev);
 726         struct __packed {
 727                 struct {
 728                         struct nv50_disp_mthd_v1 mthd;
 729                         struct nv50_disp_sor_hda_eld_v0 eld;
 730                 } base;
 731                 u8 data[sizeof(nv_connector->base.eld)];
 732         } args = {
 733                 .base.mthd.version = 1,
 734                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 735                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 736                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 737                                      (0x0100 << nv_crtc->index),
 738         };
 739
 740         nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
 741         if (!drm_detect_monitor_audio(nv_connector->edid))
 742                 return;
 743
 744         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 745
 746         nvif_mthd(&disp->disp->object, 0, &args,
 747                   sizeof(args.base) + drm_eld_size(args.data));
 748         nv_encoder->audio = true;
 749
 750         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 751                                         nv_crtc->index);
 752 }
 753
 754 /******************************************************************************
 755  * HDMI
 756  *****************************************************************************/
 757 static void
 758 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 759 {
 760         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 761         struct nv50_disp *disp = nv50_disp(encoder->dev);
 762         struct {
 763                 struct nv50_disp_mthd_v1 base;
 764                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 765         } args = {
 766                 .base.version = 1,
 767                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 768                 .base.hasht  = nv_encoder->dcb->hasht,
 769                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 770                                (0x0100 << nv_crtc->index),
 771         };
 772
 773         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 774 }
 775
 776 static void
 777 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_atomic_state *state,
 778                  struct drm_display_mode *mode)
 779 {
 780         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 781         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 782         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 783         struct nv50_disp *disp = nv50_disp(encoder->dev);
 784         struct {
 785                 struct nv50_disp_mthd_v1 base;
 786                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 787                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 788         } args = {
 789                 .base.version = 1,
 790                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 791                 .base.hasht  = nv_encoder->dcb->hasht,
 792                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 793                                (0x0100 << nv_crtc->index),
 794                 .pwr.state = 1,
 795                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 796         };
 797         struct nouveau_connector *nv_connector;
 798         struct drm_hdmi_info *hdmi;
 799         u32 max_ac_packet;
 800         union hdmi_infoframe avi_frame;
 801         union hdmi_infoframe vendor_frame;
 802         bool high_tmds_clock_ratio = false, scrambling = false;
 803         u8 config;
 804         int ret;
 805         int size;
 806
 807         nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
 808         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 809                 return;
 810
 811         hdmi = &nv_connector->base.display_info.hdmi;
 812
 813         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 814                                                        &nv_connector->base, mode);
 815         if (!ret) {
 816                 /* We have an AVI InfoFrame, populate it to the display */
 817                 args.pwr.avi_infoframe_length
 818                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 819         }
 820
 821         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 822                                                           &nv_connector->base, mode);
 823         if (!ret) {
 824                 /* We have a Vendor InfoFrame, populate it to the display */
 825                 args.pwr.vendor_infoframe_length
 826                         = hdmi_infoframe_pack(&vendor_frame,
 827                                               args.infoframes
 828                                               + args.pwr.avi_infoframe_length,
 829                                               17);
 830         }
 831
 832         max_ac_packet  = mode->htotal - mode->hdisplay;
 833         max_ac_packet -= args.pwr.rekey;
 834         max_ac_packet -= 18; /* constant from tegra */
 835         args.pwr.max_ac_packet = max_ac_packet / 32;
 836
 837         if (hdmi->scdc.scrambling.supported) {
 838                 high_tmds_clock_ratio = mode->clock > 340000;
 839                 scrambling = high_tmds_clock_ratio ||
 840                         hdmi->scdc.scrambling.low_rates;
 841         }
 842
 843         args.pwr.scdc =
 844                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 845                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 846
 847         size = sizeof(args.base)
 848                 + sizeof(args.pwr)
 849                 + args.pwr.avi_infoframe_length
 850                 + args.pwr.vendor_infoframe_length;
 851         nvif_mthd(&disp->disp->object, 0, &args, size);
 852
 853         nv50_audio_enable(encoder, state, mode);
 854
 855         /* If SCDC is supported by the downstream monitor, update
 856          * divider / scrambling settings to what we programmed above.
 857          */
 858         if (!hdmi->scdc.scrambling.supported)
 859                 return;
 860
 861         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 862         if (ret < 0) {
 863                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 864                 return;
 865         }
 866         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 867         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 868         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 869         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 870         if (ret < 0)
 871                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 872                          config, ret);
 873 }
 874
 875 /******************************************************************************
 876  * MST
 877  *****************************************************************************/
 878 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 879 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 880 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 881
 882 struct nv50_mstc {
 883         struct nv50_mstm *mstm;
 884         struct drm_dp_mst_port *port;
 885         struct drm_connector connector;
 886
 887         struct drm_display_mode *native;
 888         struct edid *edid;
 889 };
 890
 891 struct nv50_msto {
 892         struct drm_encoder encoder;
 893
 894         struct nv50_head *head;
 895         struct nv50_mstc *mstc;
 896         bool disabled;
 897 };
 898
 899 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
 900 {
 901         struct nv50_msto *msto;
 902
 903         if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
 904                 return nouveau_encoder(encoder);
 905
 906         msto = nv50_msto(encoder);
 907         if (!msto->mstc)
 908                 return NULL;
 909         return msto->mstc->mstm->outp;
 910 }
 911
 912 static struct drm_dp_payload *
 913 nv50_msto_payload(struct nv50_msto *msto)
 914 {
 915         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 916         struct nv50_mstc *mstc = msto->mstc;
 917         struct nv50_mstm *mstm = mstc->mstm;
 918         int vcpi = mstc->port->vcpi.vcpi, i;
 919
 920         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 921
 922         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 923         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 924                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 925                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 926                           mstm->outp->base.base.name, i, payload->vcpi,
 927                           payload->start_slot, payload->num_slots);
 928         }
 929
 930         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 931                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 932                 if (payload->vcpi == vcpi)
 933                         return payload;
 934         }
 935
 936         return NULL;
 937 }
 938
 939 static void
 940 nv50_msto_cleanup(struct nv50_msto *msto)
 941 {
 942         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 943         struct nv50_mstc *mstc = msto->mstc;
 944         struct nv50_mstm *mstm = mstc->mstm;
 945
 946         if (!msto->disabled)
 947                 return;
 948
 949         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 950
 951         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 952
 953         msto->mstc = NULL;
 954         msto->disabled = false;
 955 }
 956
 957 static void
 958 nv50_msto_prepare(struct nv50_msto *msto)
 959 {
 960         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 961         struct nv50_mstc *mstc = msto->mstc;
 962         struct nv50_mstm *mstm = mstc->mstm;
 963         struct {
 964                 struct nv50_disp_mthd_v1 base;
 965                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 966         } args = {
 967                 .base.version = 1,
 968                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 969                 .base.hasht  = mstm->outp->dcb->hasht,
 970                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 971                                (0x0100 << msto->head->base.index),
 972         };
 973
 974         mutex_lock(&mstm->mgr.payload_lock);
 975
 976         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 977         if (mstc->port->vcpi.vcpi > 0) {
 978                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 979                 if (payload) {
 980                         args.vcpi.start_slot = payload->start_slot;
 981                         args.vcpi.num_slots = payload->num_slots;
 982                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 983                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 984                 }
 985         }
 986
 987         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 988                   msto->encoder.name, msto->head->base.base.name,
 989                   args.vcpi.start_slot, args.vcpi.num_slots,
 990                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 991
 992         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 993         mutex_unlock(&mstm->mgr.payload_lock);
 994 }
 995
 996 static int
 997 nv50_msto_atomic_check(struct drm_encoder *encoder,
 998                        struct drm_crtc_state *crtc_state,
 999                        struct drm_connector_state *conn_state)
1000 {
1001         struct drm_atomic_state *state = crtc_state->state;
1002         struct drm_connector *connector = conn_state->connector;
1003         struct nv50_mstc *mstc = nv50_mstc(connector);
1004         struct nv50_mstm *mstm = mstc->mstm;
1005         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
1006         int slots;
1007         int ret;
1008
1009         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
1010                                           mstc->native);
1011         if (ret)
1012                 return ret;
1013
1014         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
1015                 return 0;
1016
1017         /*
1018          * When restoring duplicated states, we need to make sure that the bw
1019          * remains the same and avoid recalculating it, as the connector's bpc
1020          * may have changed after the state was duplicated
1021          */
1022         if (!state->duplicated) {
1023                 const int clock = crtc_state->adjusted_mode.clock;
1024
1025                 asyh->or.bpc = connector->display_info.bpc;
1026                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
1027                                                     false);
1028         }
1029
1030         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
1031                                               asyh->dp.pbn, 0);
1032         if (slots < 0)
1033                 return slots;
1034
1035         asyh->dp.tu = slots;
1036
1037         return 0;
1038 }
1039
1040 static u8
1041 nv50_dp_bpc_to_depth(unsigned int bpc)
1042 {
1043         switch (bpc) {
1044         case  6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1045         case  8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1046         case 10:
1047         default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1048         }
1049 }
1050
1051 static void
1052 nv50_msto_enable(struct drm_encoder *encoder)
1053 {
1054         struct nv50_head *head = nv50_head(encoder->crtc);
1055         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
1056         struct nv50_msto *msto = nv50_msto(encoder);
1057         struct nv50_mstc *mstc = NULL;
1058         struct nv50_mstm *mstm = NULL;
1059         struct drm_connector *connector;
1060         struct drm_connector_list_iter conn_iter;
1061         u8 proto;
1062         bool r;
1063
1064         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1065         drm_for_each_connector_iter(connector, &conn_iter) {
1066                 if (connector->state->best_encoder == &msto->encoder) {
1067                         mstc = nv50_mstc(connector);
1068                         mstm = mstc->mstm;
1069                         break;
1070                 }
1071         }
1072         drm_connector_list_iter_end(&conn_iter);
1073
1074         if (WARN_ON(!mstc))
1075                 return;
1076
1077         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
1078                                      armh->dp.tu);
1079         if (!r)
1080                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
1081
1082         if (!mstm->links++)
1083                 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
1084
1085         if (mstm->outp->link & 1)
1086                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1087         else
1088                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1089
1090         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
1091                            nv50_dp_bpc_to_depth(armh->or.bpc));
1092
1093         msto->mstc = mstc;
1094         mstm->modified = true;
1095 }
1096
1097 static void
1098 nv50_msto_disable(struct drm_encoder *encoder)
1099 {
1100         struct nv50_msto *msto = nv50_msto(encoder);
1101         struct nv50_mstc *mstc = msto->mstc;
1102         struct nv50_mstm *mstm = mstc->mstm;
1103
1104         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
1105
1106         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1107         mstm->modified = true;
1108         if (!--mstm->links)
1109                 mstm->disabled = true;
1110         msto->disabled = true;
1111 }
1112
1113 static const struct drm_encoder_helper_funcs
1114 nv50_msto_help = {
1115         .disable = nv50_msto_disable,
1116         .enable = nv50_msto_enable,
1117         .atomic_check = nv50_msto_atomic_check,
1118 };
1119
1120 static void
1121 nv50_msto_destroy(struct drm_encoder *encoder)
1122 {
1123         struct nv50_msto *msto = nv50_msto(encoder);
1124         drm_encoder_cleanup(&msto->encoder);
1125         kfree(msto);
1126 }
1127
1128 static const struct drm_encoder_funcs
1129 nv50_msto = {
1130         .destroy = nv50_msto_destroy,
1131 };
1132
1133 static struct nv50_msto *
1134 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1135 {
1136         struct nv50_msto *msto;
1137         int ret;
1138
1139         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1140         if (!msto)
1141                 return ERR_PTR(-ENOMEM);
1142
1143         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1144                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1145         if (ret) {
1146                 kfree(msto);
1147                 return ERR_PTR(ret);
1148         }
1149
1150         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1151         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1152         msto->head = head;
1153         return msto;
1154 }
1155
1156 static struct drm_encoder *
1157 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1158                               struct drm_connector_state *connector_state)
1159 {
1160         struct nv50_mstc *mstc = nv50_mstc(connector);
1161         struct drm_crtc *crtc = connector_state->crtc;
1162
1163         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1164                 return NULL;
1165
1166         return &nv50_head(crtc)->msto->encoder;
1167 }
1168
1169 static enum drm_mode_status
1170 nv50_mstc_mode_valid(struct drm_connector *connector,
1171                      struct drm_display_mode *mode)
1172 {
1173         struct nv50_mstc *mstc = nv50_mstc(connector);
1174         struct nouveau_encoder *outp = mstc->mstm->outp;
1175
1176         /* TODO: calculate the PBN from the dotclock and validate against the
1177          * MSTB's max possible PBN
1178          */
1179
1180         return nv50_dp_mode_valid(connector, outp, mode, NULL);
1181 }
1182
1183 static int
1184 nv50_mstc_get_modes(struct drm_connector *connector)
1185 {
1186         struct nv50_mstc *mstc = nv50_mstc(connector);
1187         int ret = 0;
1188
1189         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1190         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1191         if (mstc->edid)
1192                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1193
1194         /*
1195          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1196          * to 8 to save bandwidth on the topology. In the future, we'll want
1197          * to properly fix this by dynamically selecting the highest possible
1198          * bpc that would fit in the topology
1199          */
1200         if (connector->display_info.bpc)
1201                 connector->display_info.bpc =
1202                         clamp(connector->display_info.bpc, 6U, 8U);
1203         else
1204                 connector->display_info.bpc = 8;
1205
1206         if (mstc->native)
1207                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1208         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1209         return ret;
1210 }
1211
1212 static int
1213 nv50_mstc_atomic_check(struct drm_connector *connector,
1214                        struct drm_atomic_state *state)
1215 {
1216         struct nv50_mstc *mstc = nv50_mstc(connector);
1217         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1218         struct drm_connector_state *new_conn_state =
1219                 drm_atomic_get_new_connector_state(state, connector);
1220         struct drm_connector_state *old_conn_state =
1221                 drm_atomic_get_old_connector_state(state, connector);
1222         struct drm_crtc_state *crtc_state;
1223         struct drm_crtc *new_crtc = new_conn_state->crtc;
1224
1225         if (!old_conn_state->crtc)
1226                 return 0;
1227
1228         /* We only want to free VCPI if this state disables the CRTC on this
1229          * connector
1230          */
1231         if (new_crtc) {
1232                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1233
1234                 if (!crtc_state ||
1235                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1236                     crtc_state->enable)
1237                         return 0;
1238         }
1239
1240         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1241 }
1242
1243 static int
1244 nv50_mstc_detect(struct drm_connector *connector,
1245                  struct drm_modeset_acquire_ctx *ctx, bool force)
1246 {
1247         struct nv50_mstc *mstc = nv50_mstc(connector);
1248         int ret;
1249
1250         if (drm_connector_is_unregistered(connector))
1251                 return connector_status_disconnected;
1252
1253         ret = pm_runtime_get_sync(connector->dev->dev);
1254         if (ret < 0 && ret != -EACCES) {
1255                 pm_runtime_put_autosuspend(connector->dev->dev);
1256                 return connector_status_disconnected;
1257         }
1258
1259         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1260                                      mstc->port);
1261
1262         pm_runtime_mark_last_busy(connector->dev->dev);
1263         pm_runtime_put_autosuspend(connector->dev->dev);
1264         return ret;
1265 }
1266
1267 static const struct drm_connector_helper_funcs
1268 nv50_mstc_help = {
1269         .get_modes = nv50_mstc_get_modes,
1270         .mode_valid = nv50_mstc_mode_valid,
1271         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1272         .atomic_check = nv50_mstc_atomic_check,
1273         .detect_ctx = nv50_mstc_detect,
1274 };
1275
1276 static void
1277 nv50_mstc_destroy(struct drm_connector *connector)
1278 {
1279         struct nv50_mstc *mstc = nv50_mstc(connector);
1280
1281         drm_connector_cleanup(&mstc->connector);
1282         drm_dp_mst_put_port_malloc(mstc->port);
1283
1284         kfree(mstc);
1285 }
1286
1287 static const struct drm_connector_funcs
1288 nv50_mstc = {
1289         .reset = nouveau_conn_reset,
1290         .fill_modes = drm_helper_probe_single_connector_modes,
1291         .destroy = nv50_mstc_destroy,
1292         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1293         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1294         .atomic_set_property = nouveau_conn_atomic_set_property,
1295         .atomic_get_property = nouveau_conn_atomic_get_property,
1296 };
1297
1298 static int
1299 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1300               const char *path, struct nv50_mstc **pmstc)
1301 {
1302         struct drm_device *dev = mstm->outp->base.base.dev;
1303         struct drm_crtc *crtc;
1304         struct nv50_mstc *mstc;
1305         int ret;
1306
1307         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1308                 return -ENOMEM;
1309         mstc->mstm = mstm;
1310         mstc->port = port;
1311
1312         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1313                                  DRM_MODE_CONNECTOR_DisplayPort);
1314         if (ret) {
1315                 kfree(*pmstc);
1316                 *pmstc = NULL;
1317                 return ret;
1318         }
1319
1320         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1321
1322         mstc->connector.funcs->reset(&mstc->connector);
1323         nouveau_conn_attach_properties(&mstc->connector);
1324
1325         drm_for_each_crtc(crtc, dev) {
1326                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1327                         continue;
1328
1329                 drm_connector_attach_encoder(&mstc->connector,
1330                                              &nv50_head(crtc)->msto->encoder);
1331         }
1332
1333         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1334         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1335         drm_connector_set_path_property(&mstc->connector, path);
1336         drm_dp_mst_get_port_malloc(port);
1337         return 0;
1338 }
1339
1340 static void
1341 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1342 {
1343         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1344         struct drm_encoder *encoder;
1345         int ret;
1346
1347         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1348         ret = drm_dp_check_act_status(&mstm->mgr);
1349
1350         ret = drm_dp_update_payload_part2(&mstm->mgr);
1351
1352         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1353                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1354                         struct nv50_msto *msto = nv50_msto(encoder);
1355                         struct nv50_mstc *mstc = msto->mstc;
1356                         if (mstc && mstc->mstm == mstm)
1357                                 nv50_msto_cleanup(msto);
1358                 }
1359         }
1360
1361         mstm->modified = false;
1362 }
1363
1364 static void
1365 nv50_mstm_prepare(struct nv50_mstm *mstm)
1366 {
1367         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1368         struct drm_encoder *encoder;
1369         int ret;
1370
1371         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1372         ret = drm_dp_update_payload_part1(&mstm->mgr);
1373
1374         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1375                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1376                         struct nv50_msto *msto = nv50_msto(encoder);
1377                         struct nv50_mstc *mstc = msto->mstc;
1378                         if (mstc && mstc->mstm == mstm)
1379                                 nv50_msto_prepare(msto);
1380                 }
1381         }
1382
1383         if (mstm->disabled) {
1384                 if (!mstm->links)
1385                         nv50_outp_release(mstm->outp);
1386                 mstm->disabled = false;
1387         }
1388 }
1389
1390 static struct drm_connector *
1391 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1392                         struct drm_dp_mst_port *port, const char *path)
1393 {
1394         struct nv50_mstm *mstm = nv50_mstm(mgr);
1395         struct nv50_mstc *mstc;
1396         int ret;
1397
1398         ret = nv50_mstc_new(mstm, port, path, &mstc);
1399         if (ret)
1400                 return NULL;
1401
1402         return &mstc->connector;
1403 }
1404
1405 static const struct drm_dp_mst_topology_cbs
1406 nv50_mstm = {
1407         .add_connector = nv50_mstm_add_connector,
1408 };
1409
1410 bool
1411 nv50_mstm_service(struct nouveau_drm *drm,
1412                   struct nouveau_connector *nv_connector,
1413                   struct nv50_mstm *mstm)
1414 {
1415         struct drm_dp_aux *aux = &nv_connector->aux;
1416         bool handled = true, ret = true;
1417         int rc;
1418         u8 esi[8] = {};
1419
1420         while (handled) {
1421                 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1422                 if (rc != 8) {
1423                         ret = false;
1424                         break;
1425                 }
1426
1427                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1428                 if (!handled)
1429                         break;
1430
1431                 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1],
1432                                        3);
1433                 if (rc != 3) {
1434                         ret = false;
1435                         break;
1436                 }
1437         }
1438
1439         if (!ret)
1440                 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n",
1441                          nv_connector->base.name, rc);
1442
1443         return ret;
1444 }
1445
1446 void
1447 nv50_mstm_remove(struct nv50_mstm *mstm)
1448 {
1449         mstm->is_mst = false;
1450         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1451 }
1452
1453 static int
1454 nv50_mstm_enable(struct nv50_mstm *mstm, int state)
1455 {
1456         struct nouveau_encoder *outp = mstm->outp;
1457         struct {
1458                 struct nv50_disp_mthd_v1 base;
1459                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1460         } args = {
1461                 .base.version = 1,
1462                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1463                 .base.hasht = outp->dcb->hasht,
1464                 .base.hashm = outp->dcb->hashm,
1465                 .mst.state = state,
1466         };
1467         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1468         struct nvif_object *disp = &drm->display->disp.object;
1469
1470         return nvif_mthd(disp, 0, &args, sizeof(args));
1471 }
1472
1473 int
1474 nv50_mstm_detect(struct nouveau_encoder *outp)
1475 {
1476         struct nv50_mstm *mstm = outp->dp.mstm;
1477         struct drm_dp_aux *aux;
1478         int ret;
1479
1480         if (!mstm || !mstm->can_mst)
1481                 return 0;
1482
1483         aux = mstm->mgr.aux;
1484
1485         /* Clear any leftover MST state we didn't set ourselves by first
1486          * disabling MST if it was already enabled
1487          */
1488         ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1489         if (ret < 0)
1490                 return ret;
1491
1492         /* And start enabling */
1493         ret = nv50_mstm_enable(mstm, true);
1494         if (ret)
1495                 return ret;
1496
1497         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1498         if (ret) {
1499                 nv50_mstm_enable(mstm, false);
1500                 return ret;
1501         }
1502
1503         mstm->is_mst = true;
1504         return 1;
1505 }
1506
1507 static void
1508 nv50_mstm_fini(struct nouveau_encoder *outp)
1509 {
1510         struct nv50_mstm *mstm = outp->dp.mstm;
1511
1512         if (!mstm)
1513                 return;
1514
1515         /* Don't change the MST state of this connector until we've finished
1516          * resuming, since we can't safely grab hpd_irq_lock in our resume
1517          * path to protect mstm->is_mst without potentially deadlocking
1518          */
1519         mutex_lock(&outp->dp.hpd_irq_lock);
1520         mstm->suspended = true;
1521         mutex_unlock(&outp->dp.hpd_irq_lock);
1522
1523         if (mstm->is_mst)
1524                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1525 }
1526
1527 static void
1528 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime)
1529 {
1530         struct nv50_mstm *mstm = outp->dp.mstm;
1531         int ret = 0;
1532
1533         if (!mstm)
1534                 return;
1535
1536         if (mstm->is_mst) {
1537                 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1538                 if (ret == -1)
1539                         nv50_mstm_remove(mstm);
1540         }
1541
1542         mutex_lock(&outp->dp.hpd_irq_lock);
1543         mstm->suspended = false;
1544         mutex_unlock(&outp->dp.hpd_irq_lock);
1545
1546         if (ret == -1)
1547                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1548 }
1549
1550 static void
1551 nv50_mstm_del(struct nv50_mstm **pmstm)
1552 {
1553         struct nv50_mstm *mstm = *pmstm;
1554         if (mstm) {
1555                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1556                 kfree(*pmstm);
1557                 *pmstm = NULL;
1558         }
1559 }
1560
1561 static int
1562 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1563               int conn_base_id, struct nv50_mstm **pmstm)
1564 {
1565         const int max_payloads = hweight8(outp->dcb->heads);
1566         struct drm_device *dev = outp->base.base.dev;
1567         struct nv50_mstm *mstm;
1568         int ret;
1569
1570         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1571                 return -ENOMEM;
1572         mstm->outp = outp;
1573         mstm->mgr.cbs = &nv50_mstm;
1574
1575         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1576                                            max_payloads, conn_base_id);
1577         if (ret)
1578                 return ret;
1579
1580         return 0;
1581 }
1582
1583 /******************************************************************************
1584  * SOR
1585  *****************************************************************************/
1586 static void
1587 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1588                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1589 {
1590         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1591         struct nv50_core *core = disp->core;
1592
1593         if (!asyh) {
1594                 nv_encoder->ctrl &= ~BIT(head);
1595                 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1596                         nv_encoder->ctrl = 0;
1597         } else {
1598                 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1599                 nv_encoder->ctrl |= BIT(head);
1600                 asyh->or.depth = depth;
1601         }
1602
1603         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1604 }
1605
1606 static void
1607 nv50_sor_disable(struct drm_encoder *encoder,
1608                  struct drm_atomic_state *state)
1609 {
1610         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1611         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1612         struct nouveau_connector *nv_connector =
1613                 nv50_outp_get_old_connector(nv_encoder, state);
1614
1615         nv_encoder->crtc = NULL;
1616
1617         if (nv_crtc) {
1618                 struct drm_dp_aux *aux = &nv_connector->aux;
1619                 u8 pwr;
1620
1621                 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1622                         int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
1623
1624                         if (ret == 0) {
1625                                 pwr &= ~DP_SET_POWER_MASK;
1626                                 pwr |=  DP_SET_POWER_D3;
1627                                 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1628                         }
1629                 }
1630
1631                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1632                 nv50_audio_disable(encoder, nv_crtc);
1633                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1634                 nv50_outp_release(nv_encoder);
1635         }
1636 }
1637
1638 static void
1639 nv50_sor_enable(struct drm_encoder *encoder,
1640                 struct drm_atomic_state *state)
1641 {
1642         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1643         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1644         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1645         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1646         struct {
1647                 struct nv50_disp_mthd_v1 base;
1648                 struct nv50_disp_sor_lvds_script_v0 lvds;
1649         } lvds = {
1650                 .base.version = 1,
1651                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1652                 .base.hasht   = nv_encoder->dcb->hasht,
1653                 .base.hashm   = nv_encoder->dcb->hashm,
1654         };
1655         struct nv50_disp *disp = nv50_disp(encoder->dev);
1656         struct drm_device *dev = encoder->dev;
1657         struct nouveau_drm *drm = nouveau_drm(dev);
1658         struct nouveau_connector *nv_connector;
1659         struct nvbios *bios = &drm->vbios;
1660         bool hda = false;
1661         u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1662         u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1663
1664         nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
1665         nv_encoder->crtc = encoder->crtc;
1666
1667         if ((disp->disp->object.oclass == GT214_DISP ||
1668              disp->disp->object.oclass >= GF110_DISP) &&
1669             drm_detect_monitor_audio(nv_connector->edid))
1670                 hda = true;
1671         nv50_outp_acquire(nv_encoder, hda);
1672
1673         switch (nv_encoder->dcb->type) {
1674         case DCB_OUTPUT_TMDS:
1675                 if (nv_encoder->link & 1) {
1676                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1677                         /* Only enable dual-link if:
1678                          *  - Need to (i.e. rate > 165MHz)
1679                          *  - DCB says we can
1680                          *  - Not an HDMI monitor, since there's no dual-link
1681                          *    on HDMI.
1682                          */
1683                         if (mode->clock >= 165000 &&
1684                             nv_encoder->dcb->duallink_possible &&
1685                             !drm_detect_hdmi_monitor(nv_connector->edid))
1686                                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1687                 } else {
1688                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1689                 }
1690
1691                 nv50_hdmi_enable(&nv_encoder->base.base, state, mode);
1692                 break;
1693         case DCB_OUTPUT_LVDS:
1694                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1695
1696                 if (bios->fp_no_ddc) {
1697                         if (bios->fp.dual_link)
1698                                 lvds.lvds.script |= 0x0100;
1699                         if (bios->fp.if_is_24bit)
1700                                 lvds.lvds.script |= 0x0200;
1701                 } else {
1702                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1703                                 if (((u8 *)nv_connector->edid)[121] == 2)
1704                                         lvds.lvds.script |= 0x0100;
1705                         } else
1706                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1707                                 lvds.lvds.script |= 0x0100;
1708                         }
1709
1710                         if (lvds.lvds.script & 0x0100) {
1711                                 if (bios->fp.strapless_is_24bit & 2)
1712                                         lvds.lvds.script |= 0x0200;
1713                         } else {
1714                                 if (bios->fp.strapless_is_24bit & 1)
1715                                         lvds.lvds.script |= 0x0200;
1716                         }
1717
1718                         if (asyh->or.bpc == 8)
1719                                 lvds.lvds.script |= 0x0200;
1720                 }
1721
1722                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1723                 break;
1724         case DCB_OUTPUT_DP:
1725                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1726
1727                 if (nv_encoder->link & 1)
1728                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1729                 else
1730                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1731
1732                 nv50_audio_enable(encoder, state, mode);
1733                 break;
1734         default:
1735                 BUG();
1736                 break;
1737         }
1738
1739         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1740 }
1741
1742 static const struct drm_encoder_helper_funcs
1743 nv50_sor_help = {
1744         .atomic_check = nv50_outp_atomic_check,
1745         .atomic_enable = nv50_sor_enable,
1746         .atomic_disable = nv50_sor_disable,
1747 };
1748
1749 static void
1750 nv50_sor_destroy(struct drm_encoder *encoder)
1751 {
1752         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1753         nv50_mstm_del(&nv_encoder->dp.mstm);
1754         drm_encoder_cleanup(encoder);
1755
1756         if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1757                 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1758
1759         kfree(encoder);
1760 }
1761
1762 static const struct drm_encoder_funcs
1763 nv50_sor_func = {
1764         .destroy = nv50_sor_destroy,
1765 };
1766
1767 static bool nv50_has_mst(struct nouveau_drm *drm)
1768 {
1769         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1770         u32 data;
1771         u8 ver, hdr, cnt, len;
1772
1773         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1774         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1775 }
1776
1777 static int
1778 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1779 {
1780         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1781         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1782         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1783         struct nouveau_encoder *nv_encoder;
1784         struct drm_encoder *encoder;
1785         struct nv50_disp *disp = nv50_disp(connector->dev);
1786         int type, ret;
1787
1788         switch (dcbe->type) {
1789         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1790         case DCB_OUTPUT_TMDS:
1791         case DCB_OUTPUT_DP:
1792         default:
1793                 type = DRM_MODE_ENCODER_TMDS;
1794                 break;
1795         }
1796
1797         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1798         if (!nv_encoder)
1799                 return -ENOMEM;
1800         nv_encoder->dcb = dcbe;
1801         nv_encoder->update = nv50_sor_update;
1802
1803         encoder = to_drm_encoder(nv_encoder);
1804         encoder->possible_crtcs = dcbe->heads;
1805         encoder->possible_clones = 0;
1806         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1807                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1808         drm_encoder_helper_add(encoder, &nv50_sor_help);
1809
1810         drm_connector_attach_encoder(connector, encoder);
1811
1812         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1813
1814         if (dcbe->type == DCB_OUTPUT_DP) {
1815                 struct nvkm_i2c_aux *aux =
1816                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1817
1818                 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1819
1820                 if (aux) {
1821                         if (disp->disp->object.oclass < GF110_DISP) {
1822                                 /* HW has no support for address-only
1823                                  * transactions, so we're required to
1824                                  * use custom I2C-over-AUX code.
1825                                  */
1826                                 nv_encoder->i2c = &aux->i2c;
1827                         } else {
1828                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1829                         }
1830                         nv_encoder->aux = aux;
1831                 }
1832
1833                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1834                     nv50_has_mst(drm)) {
1835                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1836                                             16, nv_connector->base.base.id,
1837                                             &nv_encoder->dp.mstm);
1838                         if (ret)
1839                                 return ret;
1840                 }
1841         } else {
1842                 struct nvkm_i2c_bus *bus =
1843                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1844                 if (bus)
1845                         nv_encoder->i2c = &bus->i2c;
1846         }
1847
1848         return 0;
1849 }
1850
1851 /******************************************************************************
1852  * PIOR
1853  *****************************************************************************/
1854 static int
1855 nv50_pior_atomic_check(struct drm_encoder *encoder,
1856                        struct drm_crtc_state *crtc_state,
1857                        struct drm_connector_state *conn_state)
1858 {
1859         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1860         if (ret)
1861                 return ret;
1862         crtc_state->adjusted_mode.clock *= 2;
1863         return 0;
1864 }
1865
1866 static void
1867 nv50_pior_disable(struct drm_encoder *encoder)
1868 {
1869         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1870         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1871         const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1872         if (nv_encoder->crtc)
1873                 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1874         nv_encoder->crtc = NULL;
1875         nv50_outp_release(nv_encoder);
1876 }
1877
1878 static void
1879 nv50_pior_enable(struct drm_encoder *encoder)
1880 {
1881         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1882         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1883         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1884         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1885         u32 ctrl = 0;
1886
1887         switch (nv_crtc->index) {
1888         case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1889         case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1890         default:
1891                 WARN_ON(1);
1892                 break;
1893         }
1894
1895         nv50_outp_acquire(nv_encoder, false);
1896
1897         switch (asyh->or.bpc) {
1898         case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1899         case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1900         case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1901         default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1902         }
1903
1904         switch (nv_encoder->dcb->type) {
1905         case DCB_OUTPUT_TMDS:
1906         case DCB_OUTPUT_DP:
1907                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1908                 break;
1909         default:
1910                 BUG();
1911                 break;
1912         }
1913
1914         core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
1915         nv_encoder->crtc = encoder->crtc;
1916 }
1917
1918 static const struct drm_encoder_helper_funcs
1919 nv50_pior_help = {
1920         .atomic_check = nv50_pior_atomic_check,
1921         .enable = nv50_pior_enable,
1922         .disable = nv50_pior_disable,
1923 };
1924
1925 static void
1926 nv50_pior_destroy(struct drm_encoder *encoder)
1927 {
1928         drm_encoder_cleanup(encoder);
1929         kfree(encoder);
1930 }
1931
1932 static const struct drm_encoder_funcs
1933 nv50_pior_func = {
1934         .destroy = nv50_pior_destroy,
1935 };
1936
1937 static int
1938 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1939 {
1940         struct drm_device *dev = connector->dev;
1941         struct nouveau_drm *drm = nouveau_drm(dev);
1942         struct nv50_disp *disp = nv50_disp(dev);
1943         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1944         struct nvkm_i2c_bus *bus = NULL;
1945         struct nvkm_i2c_aux *aux = NULL;
1946         struct i2c_adapter *ddc;
1947         struct nouveau_encoder *nv_encoder;
1948         struct drm_encoder *encoder;
1949         int type;
1950
1951         switch (dcbe->type) {
1952         case DCB_OUTPUT_TMDS:
1953                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1954                 ddc  = bus ? &bus->i2c : NULL;
1955                 type = DRM_MODE_ENCODER_TMDS;
1956                 break;
1957         case DCB_OUTPUT_DP:
1958                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1959                 ddc  = aux ? &aux->i2c : NULL;
1960                 type = DRM_MODE_ENCODER_TMDS;
1961                 break;
1962         default:
1963                 return -ENODEV;
1964         }
1965
1966         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1967         if (!nv_encoder)
1968                 return -ENOMEM;
1969         nv_encoder->dcb = dcbe;
1970         nv_encoder->i2c = ddc;
1971         nv_encoder->aux = aux;
1972
1973         encoder = to_drm_encoder(nv_encoder);
1974         encoder->possible_crtcs = dcbe->heads;
1975         encoder->possible_clones = 0;
1976         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1977                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1978         drm_encoder_helper_add(encoder, &nv50_pior_help);
1979
1980         drm_connector_attach_encoder(connector, encoder);
1981
1982         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1983
1984         return 0;
1985 }
1986
1987 /******************************************************************************
1988  * Atomic
1989  *****************************************************************************/
1990
1991 static void
1992 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1993 {
1994         struct nouveau_drm *drm = nouveau_drm(state->dev);
1995         struct nv50_disp *disp = nv50_disp(drm->dev);
1996         struct nv50_core *core = disp->core;
1997         struct nv50_mstm *mstm;
1998         struct drm_encoder *encoder;
1999
2000         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2001
2002         drm_for_each_encoder(encoder, drm->dev) {
2003                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2004                         mstm = nouveau_encoder(encoder)->dp.mstm;
2005                         if (mstm && mstm->modified)
2006                                 nv50_mstm_prepare(mstm);
2007                 }
2008         }
2009
2010         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2011         core->func->update(core, interlock, true);
2012         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2013                                        disp->core->chan.base.device))
2014                 NV_ERROR(drm, "core notifier timeout\n");
2015
2016         drm_for_each_encoder(encoder, drm->dev) {
2017                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2018                         mstm = nouveau_encoder(encoder)->dp.mstm;
2019                         if (mstm && mstm->modified)
2020                                 nv50_mstm_cleanup(mstm);
2021                 }
2022         }
2023 }
2024
2025 static void
2026 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2027 {
2028         struct drm_plane_state *new_plane_state;
2029         struct drm_plane *plane;
2030         int i;
2031
2032         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2033                 struct nv50_wndw *wndw = nv50_wndw(plane);
2034                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2035                         if (wndw->func->update)
2036                                 wndw->func->update(wndw, interlock);
2037                 }
2038         }
2039 }
2040
2041 static void
2042 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2043 {
2044         struct drm_device *dev = state->dev;
2045         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2046         struct drm_crtc *crtc;
2047         struct drm_plane_state *new_plane_state;
2048         struct drm_plane *plane;
2049         struct nouveau_drm *drm = nouveau_drm(dev);
2050         struct nv50_disp *disp = nv50_disp(dev);
2051         struct nv50_atom *atom = nv50_atom(state);
2052         struct nv50_core *core = disp->core;
2053         struct nv50_outp_atom *outp, *outt;
2054         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2055         int i;
2056         bool flushed = false;
2057
2058         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2059         nv50_crc_atomic_stop_reporting(state);
2060         drm_atomic_helper_wait_for_fences(dev, state, false);
2061         drm_atomic_helper_wait_for_dependencies(state);
2062         drm_atomic_helper_update_legacy_modeset_state(dev, state);
2063
2064         if (atom->lock_core)
2065                 mutex_lock(&disp->mutex);
2066
2067         /* Disable head(s). */
2068         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2069                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2070                 struct nv50_head *head = nv50_head(crtc);
2071
2072                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2073                           asyh->clr.mask, asyh->set.mask);
2074
2075                 if (old_crtc_state->active && !new_crtc_state->active) {
2076                         pm_runtime_put_noidle(dev->dev);
2077                         drm_crtc_vblank_off(crtc);
2078                 }
2079
2080                 if (asyh->clr.mask) {
2081                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
2082                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2083                 }
2084         }
2085
2086         /* Disable plane(s). */
2087         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2088                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2089                 struct nv50_wndw *wndw = nv50_wndw(plane);
2090
2091                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2092                           asyw->clr.mask, asyw->set.mask);
2093                 if (!asyw->clr.mask)
2094                         continue;
2095
2096                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2097         }
2098
2099         /* Disable output path(s). */
2100         list_for_each_entry(outp, &atom->outp, head) {
2101                 const struct drm_encoder_helper_funcs *help;
2102                 struct drm_encoder *encoder;
2103
2104                 encoder = outp->encoder;
2105                 help = encoder->helper_private;
2106
2107                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2108                           outp->clr.mask, outp->set.mask);
2109
2110                 if (outp->clr.mask) {
2111                         help->atomic_disable(encoder, state);
2112                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2113                         if (outp->flush_disable) {
2114                                 nv50_disp_atomic_commit_wndw(state, interlock);
2115                                 nv50_disp_atomic_commit_core(state, interlock);
2116                                 memset(interlock, 0x00, sizeof(interlock));
2117
2118                                 flushed = true;
2119                         }
2120                 }
2121         }
2122
2123         /* Flush disable. */
2124         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2125                 if (atom->flush_disable) {
2126                         nv50_disp_atomic_commit_wndw(state, interlock);
2127                         nv50_disp_atomic_commit_core(state, interlock);
2128                         memset(interlock, 0x00, sizeof(interlock));
2129
2130                         flushed = true;
2131                 }
2132         }
2133
2134         if (flushed)
2135                 nv50_crc_atomic_release_notifier_contexts(state);
2136         nv50_crc_atomic_init_notifier_contexts(state);
2137
2138         /* Update output path(s). */
2139         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2140                 const struct drm_encoder_helper_funcs *help;
2141                 struct drm_encoder *encoder;
2142
2143                 encoder = outp->encoder;
2144                 help = encoder->helper_private;
2145
2146                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2147                           outp->set.mask, outp->clr.mask);
2148
2149                 if (outp->set.mask) {
2150                         help->atomic_enable(encoder, state);
2151                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2152                 }
2153
2154                 list_del(&outp->head);
2155                 kfree(outp);
2156         }
2157
2158         /* Update head(s). */
2159         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2160                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2161                 struct nv50_head *head = nv50_head(crtc);
2162
2163                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2164                           asyh->set.mask, asyh->clr.mask);
2165
2166                 if (asyh->set.mask) {
2167                         nv50_head_flush_set(head, asyh);
2168                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2169                 }
2170
2171                 if (new_crtc_state->active) {
2172                         if (!old_crtc_state->active) {
2173                                 drm_crtc_vblank_on(crtc);
2174                                 pm_runtime_get_noresume(dev->dev);
2175                         }
2176                         if (new_crtc_state->event)
2177                                 drm_crtc_vblank_get(crtc);
2178                 }
2179         }
2180
2181         /* Update window->head assignment.
2182          *
2183          * This has to happen in an update that's not interlocked with
2184          * any window channels to avoid hitting HW error checks.
2185          *
2186          *TODO: Proper handling of window ownership (Turing apparently
2187          *      supports non-fixed mappings).
2188          */
2189         if (core->assign_windows) {
2190                 core->func->wndw.owner(core);
2191                 nv50_disp_atomic_commit_core(state, interlock);
2192                 core->assign_windows = false;
2193                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2194         }
2195
2196         /* Update plane(s). */
2197         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2198                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2199                 struct nv50_wndw *wndw = nv50_wndw(plane);
2200
2201                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2202                           asyw->set.mask, asyw->clr.mask);
2203                 if ( !asyw->set.mask &&
2204                     (!asyw->clr.mask || atom->flush_disable))
2205                         continue;
2206
2207                 nv50_wndw_flush_set(wndw, interlock, asyw);
2208         }
2209
2210         /* Flush update. */
2211         nv50_disp_atomic_commit_wndw(state, interlock);
2212
2213         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2214                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2215                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2216                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2217                     !atom->state.legacy_cursor_update)
2218                         nv50_disp_atomic_commit_core(state, interlock);
2219                 else
2220                         disp->core->func->update(disp->core, interlock, false);
2221         }
2222
2223         if (atom->lock_core)
2224                 mutex_unlock(&disp->mutex);
2225
2226         /* Wait for HW to signal completion. */
2227         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2228                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2229                 struct nv50_wndw *wndw = nv50_wndw(plane);
2230                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2231                 if (ret)
2232                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2233         }
2234
2235         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2236                 if (new_crtc_state->event) {
2237                         unsigned long flags;
2238                         /* Get correct count/ts if racing with vblank irq */
2239                         if (new_crtc_state->active)
2240                                 drm_crtc_accurate_vblank_count(crtc);
2241                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2242                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2243                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2244
2245                         new_crtc_state->event = NULL;
2246                         if (new_crtc_state->active)
2247                                 drm_crtc_vblank_put(crtc);
2248                 }
2249         }
2250
2251         nv50_crc_atomic_start_reporting(state);
2252         if (!flushed)
2253                 nv50_crc_atomic_release_notifier_contexts(state);
2254         drm_atomic_helper_commit_hw_done(state);
2255         drm_atomic_helper_cleanup_planes(dev, state);
2256         drm_atomic_helper_commit_cleanup_done(state);
2257         drm_atomic_state_put(state);
2258
2259         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2260         pm_runtime_mark_last_busy(dev->dev);
2261         pm_runtime_put_autosuspend(dev->dev);
2262 }
2263
2264 static void
2265 nv50_disp_atomic_commit_work(struct work_struct *work)
2266 {
2267         struct drm_atomic_state *state =
2268                 container_of(work, typeof(*state), commit_work);
2269         nv50_disp_atomic_commit_tail(state);
2270 }
2271
2272 static int
2273 nv50_disp_atomic_commit(struct drm_device *dev,
2274                         struct drm_atomic_state *state, bool nonblock)
2275 {
2276         struct drm_plane_state *new_plane_state;
2277         struct drm_plane *plane;
2278         int ret, i;
2279
2280         ret = pm_runtime_get_sync(dev->dev);
2281         if (ret < 0 && ret != -EACCES) {
2282                 pm_runtime_put_autosuspend(dev->dev);
2283                 return ret;
2284         }
2285
2286         ret = drm_atomic_helper_setup_commit(state, nonblock);
2287         if (ret)
2288                 goto done;
2289
2290         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2291
2292         ret = drm_atomic_helper_prepare_planes(dev, state);
2293         if (ret)
2294                 goto done;
2295
2296         if (!nonblock) {
2297                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2298                 if (ret)
2299                         goto err_cleanup;
2300         }
2301
2302         ret = drm_atomic_helper_swap_state(state, true);
2303         if (ret)
2304                 goto err_cleanup;
2305
2306         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2307                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2308                 struct nv50_wndw *wndw = nv50_wndw(plane);
2309
2310                 if (asyw->set.image)
2311                         nv50_wndw_ntfy_enable(wndw, asyw);
2312         }
2313
2314         drm_atomic_state_get(state);
2315
2316         /*
2317          * Grab another RPM ref for the commit tail, which will release the
2318          * ref when it's finished
2319          */
2320         pm_runtime_get_noresume(dev->dev);
2321
2322         if (nonblock)
2323                 queue_work(system_unbound_wq, &state->commit_work);
2324         else
2325                 nv50_disp_atomic_commit_tail(state);
2326
2327 err_cleanup:
2328         if (ret)
2329                 drm_atomic_helper_cleanup_planes(dev, state);
2330 done:
2331         pm_runtime_put_autosuspend(dev->dev);
2332         return ret;
2333 }
2334
2335 static struct nv50_outp_atom *
2336 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2337 {
2338         struct nv50_outp_atom *outp;
2339
2340         list_for_each_entry(outp, &atom->outp, head) {
2341                 if (outp->encoder == encoder)
2342                         return outp;
2343         }
2344
2345         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2346         if (!outp)
2347                 return ERR_PTR(-ENOMEM);
2348
2349         list_add(&outp->head, &atom->outp);
2350         outp->encoder = encoder;
2351         return outp;
2352 }
2353
2354 static int
2355 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2356                                 struct drm_connector_state *old_connector_state)
2357 {
2358         struct drm_encoder *encoder = old_connector_state->best_encoder;
2359         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2360         struct drm_crtc *crtc;
2361         struct nv50_outp_atom *outp;
2362
2363         if (!(crtc = old_connector_state->crtc))
2364                 return 0;
2365
2366         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2367         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2368         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2369                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2370                 if (IS_ERR(outp))
2371                         return PTR_ERR(outp);
2372
2373                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2374                         outp->flush_disable = true;
2375                         atom->flush_disable = true;
2376                 }
2377                 outp->clr.ctrl = true;
2378                 atom->lock_core = true;
2379         }
2380
2381         return 0;
2382 }
2383
2384 static int
2385 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2386                                 struct drm_connector_state *connector_state)
2387 {
2388         struct drm_encoder *encoder = connector_state->best_encoder;
2389         struct drm_crtc_state *new_crtc_state;
2390         struct drm_crtc *crtc;
2391         struct nv50_outp_atom *outp;
2392
2393         if (!(crtc = connector_state->crtc))
2394                 return 0;
2395
2396         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2397         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2398                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2399                 if (IS_ERR(outp))
2400                         return PTR_ERR(outp);
2401
2402                 outp->set.ctrl = true;
2403                 atom->lock_core = true;
2404         }
2405
2406         return 0;
2407 }
2408
2409 static int
2410 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2411 {
2412         struct nv50_atom *atom = nv50_atom(state);
2413         struct nv50_core *core = nv50_disp(dev)->core;
2414         struct drm_connector_state *old_connector_state, *new_connector_state;
2415         struct drm_connector *connector;
2416         struct drm_crtc_state *new_crtc_state;
2417         struct drm_crtc *crtc;
2418         struct nv50_head *head;
2419         struct nv50_head_atom *asyh;
2420         int ret, i;
2421
2422         if (core->assign_windows && core->func->head->static_wndw_map) {
2423                 drm_for_each_crtc(crtc, dev) {
2424                         new_crtc_state = drm_atomic_get_crtc_state(state,
2425                                                                    crtc);
2426                         if (IS_ERR(new_crtc_state))
2427                                 return PTR_ERR(new_crtc_state);
2428
2429                         head = nv50_head(crtc);
2430                         asyh = nv50_head_atom(new_crtc_state);
2431                         core->func->head->static_wndw_map(head, asyh);
2432                 }
2433         }
2434
2435         /* We need to handle colour management on a per-plane basis. */
2436         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2437                 if (new_crtc_state->color_mgmt_changed) {
2438                         ret = drm_atomic_add_affected_planes(state, crtc);
2439                         if (ret)
2440                                 return ret;
2441                 }
2442         }
2443
2444         ret = drm_atomic_helper_check(dev, state);
2445         if (ret)
2446                 return ret;
2447
2448         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2449                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2450                 if (ret)
2451                         return ret;
2452
2453                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2454                 if (ret)
2455                         return ret;
2456         }
2457
2458         ret = drm_dp_mst_atomic_check(state);
2459         if (ret)
2460                 return ret;
2461
2462         nv50_crc_atomic_check_outp(atom);
2463
2464         return 0;
2465 }
2466
2467 static void
2468 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2469 {
2470         struct nv50_atom *atom = nv50_atom(state);
2471         struct nv50_outp_atom *outp, *outt;
2472
2473         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2474                 list_del(&outp->head);
2475                 kfree(outp);
2476         }
2477
2478         drm_atomic_state_default_clear(state);
2479 }
2480
2481 static void
2482 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2483 {
2484         struct nv50_atom *atom = nv50_atom(state);
2485         drm_atomic_state_default_release(&atom->state);
2486         kfree(atom);
2487 }
2488
2489 static struct drm_atomic_state *
2490 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2491 {
2492         struct nv50_atom *atom;
2493         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2494             drm_atomic_state_init(dev, &atom->state) < 0) {
2495                 kfree(atom);
2496                 return NULL;
2497         }
2498         INIT_LIST_HEAD(&atom->outp);
2499         return &atom->state;
2500 }
2501
2502 static const struct drm_mode_config_funcs
2503 nv50_disp_func = {
2504         .fb_create = nouveau_user_framebuffer_create,
2505         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2506         .atomic_check = nv50_disp_atomic_check,
2507         .atomic_commit = nv50_disp_atomic_commit,
2508         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2509         .atomic_state_clear = nv50_disp_atomic_state_clear,
2510         .atomic_state_free = nv50_disp_atomic_state_free,
2511 };
2512
2513 /******************************************************************************
2514  * Init
2515  *****************************************************************************/
2516
2517 static void
2518 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend)
2519 {
2520         struct nouveau_drm *drm = nouveau_drm(dev);
2521         struct drm_encoder *encoder;
2522         struct drm_plane *plane;
2523
2524         drm_for_each_plane(plane, dev) {
2525                 struct nv50_wndw *wndw = nv50_wndw(plane);
2526                 if (plane->funcs != &nv50_wndw)
2527                         continue;
2528                 nv50_wndw_fini(wndw);
2529         }
2530
2531         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2532                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2533                         nv50_mstm_fini(nouveau_encoder(encoder));
2534         }
2535
2536         if (!runtime)
2537                 cancel_work_sync(&drm->hpd_work);
2538 }
2539
2540 static int
2541 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2542 {
2543         struct nv50_core *core = nv50_disp(dev)->core;
2544         struct drm_encoder *encoder;
2545         struct drm_plane *plane;
2546
2547         if (resume || runtime)
2548                 core->func->init(core);
2549
2550         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2551                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2552                         struct nouveau_encoder *nv_encoder =
2553                                 nouveau_encoder(encoder);
2554                         nv50_mstm_init(nv_encoder, runtime);
2555                 }
2556         }
2557
2558         drm_for_each_plane(plane, dev) {
2559                 struct nv50_wndw *wndw = nv50_wndw(plane);
2560                 if (plane->funcs != &nv50_wndw)
2561                         continue;
2562                 nv50_wndw_init(wndw);
2563         }
2564
2565         return 0;
2566 }
2567
2568 static void
2569 nv50_display_destroy(struct drm_device *dev)
2570 {
2571         struct nv50_disp *disp = nv50_disp(dev);
2572
2573         nv50_audio_component_fini(nouveau_drm(dev));
2574
2575         nvif_object_unmap(&disp->caps);
2576         nvif_object_dtor(&disp->caps);
2577         nv50_core_del(&disp->core);
2578
2579         nouveau_bo_unmap(disp->sync);
2580         if (disp->sync)
2581                 nouveau_bo_unpin(disp->sync);
2582         nouveau_bo_ref(NULL, &disp->sync);
2583
2584         nouveau_display(dev)->priv = NULL;
2585         kfree(disp);
2586 }
2587
2588 int
2589 nv50_display_create(struct drm_device *dev)
2590 {
2591         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2592         struct nouveau_drm *drm = nouveau_drm(dev);
2593         struct dcb_table *dcb = &drm->vbios.dcb;
2594         struct drm_connector *connector, *tmp;
2595         struct nv50_disp *disp;
2596         struct dcb_output *dcbe;
2597         int crtcs, ret, i;
2598         bool has_mst = nv50_has_mst(drm);
2599
2600         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2601         if (!disp)
2602                 return -ENOMEM;
2603
2604         mutex_init(&disp->mutex);
2605
2606         nouveau_display(dev)->priv = disp;
2607         nouveau_display(dev)->dtor = nv50_display_destroy;
2608         nouveau_display(dev)->init = nv50_display_init;
2609         nouveau_display(dev)->fini = nv50_display_fini;
2610         disp->disp = &nouveau_display(dev)->disp;
2611         dev->mode_config.funcs = &nv50_disp_func;
2612         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2613         dev->mode_config.normalize_zpos = true;
2614
2615         /* small shared memory area we use for notifiers and semaphores */
2616         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2617                              0, 0x0000, NULL, NULL, &disp->sync);
2618         if (!ret) {
2619                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2620                 if (!ret) {
2621                         ret = nouveau_bo_map(disp->sync);
2622                         if (ret)
2623                                 nouveau_bo_unpin(disp->sync);
2624                 }
2625                 if (ret)
2626                         nouveau_bo_ref(NULL, &disp->sync);
2627         }
2628
2629         if (ret)
2630                 goto out;
2631
2632         /* allocate master evo channel */
2633         ret = nv50_core_new(drm, &disp->core);
2634         if (ret)
2635                 goto out;
2636
2637         disp->core->func->init(disp->core);
2638         if (disp->core->func->caps_init) {
2639                 ret = disp->core->func->caps_init(drm, disp);
2640                 if (ret)
2641                         goto out;
2642         }
2643
2644         /* Assign the correct format modifiers */
2645         if (disp->disp->object.oclass >= TU102_DISP)
2646                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2647         else
2648         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2649                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2650         else
2651                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2652
2653         /* create crtc objects to represent the hw heads */
2654         if (disp->disp->object.oclass >= GV100_DISP)
2655                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2656         else
2657         if (disp->disp->object.oclass >= GF110_DISP)
2658                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2659         else
2660                 crtcs = 0x3;
2661
2662         for (i = 0; i < fls(crtcs); i++) {
2663                 struct nv50_head *head;
2664
2665                 if (!(crtcs & (1 << i)))
2666                         continue;
2667
2668                 head = nv50_head_create(dev, i);
2669                 if (IS_ERR(head)) {
2670                         ret = PTR_ERR(head);
2671                         goto out;
2672                 }
2673
2674                 if (has_mst) {
2675                         head->msto = nv50_msto_new(dev, head, i);
2676                         if (IS_ERR(head->msto)) {
2677                                 ret = PTR_ERR(head->msto);
2678                                 head->msto = NULL;
2679                                 goto out;
2680                         }
2681
2682                         /*
2683                          * FIXME: This is a hack to workaround the following
2684                          * issues:
2685                          *
2686                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2687                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2688                          *
2689                          * Once these issues are closed, this should be
2690                          * removed
2691                          */
2692                         head->msto->encoder.possible_crtcs = crtcs;
2693                 }
2694         }
2695
2696         /* create encoder/connector objects based on VBIOS DCB table */
2697         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2698                 connector = nouveau_connector_create(dev, dcbe);
2699                 if (IS_ERR(connector))
2700                         continue;
2701
2702                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2703                         switch (dcbe->type) {
2704                         case DCB_OUTPUT_TMDS:
2705                         case DCB_OUTPUT_LVDS:
2706                         case DCB_OUTPUT_DP:
2707                                 ret = nv50_sor_create(connector, dcbe);
2708                                 break;
2709                         case DCB_OUTPUT_ANALOG:
2710                                 ret = nv50_dac_create(connector, dcbe);
2711                                 break;
2712                         default:
2713                                 ret = -ENODEV;
2714                                 break;
2715                         }
2716                 } else {
2717                         ret = nv50_pior_create(connector, dcbe);
2718                 }
2719
2720                 if (ret) {
2721                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2722                                      dcbe->location, dcbe->type,
2723                                      ffs(dcbe->or) - 1, ret);
2724                         ret = 0;
2725                 }
2726         }
2727
2728         /* cull any connectors we created that don't have an encoder */
2729         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2730                 if (connector->possible_encoders)
2731                         continue;
2732
2733                 NV_WARN(drm, "%s has no encoders, removing\n",
2734                         connector->name);
2735                 connector->funcs->destroy(connector);
2736         }
2737
2738         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2739         dev->vblank_disable_immediate = true;
2740
2741         nv50_audio_component_init(drm);
2742
2743 out:
2744         if (ret)
2745                 nv50_display_destroy(dev);
2746         return ret;
2747 }
2748
2749 /******************************************************************************
2750  * Format modifiers
2751  *****************************************************************************/
2752
2753 /****************************************************************
2754  *            Log2(block height) ----------------------------+  *
2755  *            Page Kind ----------------------------------+  |  *
2756  *            Gob Height/Page Kind Generation ------+     |  |  *
2757  *                          Sector layout -------+  |     |  |  *
2758  *                          Compression ------+  |  |     |  |  */
2759 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2760         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2761         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2762         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2763         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2764         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2765         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2766         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2767         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2768         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2769         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2770         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2771         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2772         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2773         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2774         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2775         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2776         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2777         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2778         DRM_FORMAT_MOD_LINEAR,
2779         DRM_FORMAT_MOD_INVALID
2780 };
2781
2782 /****************************************************************
2783  *            Log2(block height) ----------------------------+  *
2784  *            Page Kind ----------------------------------+  |  *
2785  *            Gob Height/Page Kind Generation ------+     |  |  *
2786  *                          Sector layout -------+  |     |  |  *
2787  *                          Compression ------+  |  |     |  |  */
2788 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2789         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2790         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2791         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2792         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2793         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2794         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2795         DRM_FORMAT_MOD_LINEAR,
2796         DRM_FORMAT_MOD_INVALID
2797 };