drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29 #include "handles.h"
  30
  31 #include <linux/dma-mapping.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/component.h>
  34
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_dp_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include <drm/drm_fb_helper.h>
  39 #include <drm/drm_plane_helper.h>
  40 #include <drm/drm_probe_helper.h>
  41 #include <drm/drm_scdc_helper.h>
  42 #include <drm/drm_vblank.h>
  43
  44 #include <nvif/push507c.h>
  45
  46 #include <nvif/class.h>
  47 #include <nvif/cl0002.h>
  48 #include <nvif/cl5070.h>
  49 #include <nvif/cl507d.h>
  50 #include <nvif/event.h>
  51 #include <nvif/timer.h>
  52
  53 #include <nvhw/class/cl507c.h>
  54 #include <nvhw/class/cl507d.h>
  55 #include <nvhw/class/cl837d.h>
  56 #include <nvhw/class/cl887d.h>
  57 #include <nvhw/class/cl907d.h>
  58 #include <nvhw/class/cl917d.h>
  59
  60 #include "nouveau_drv.h"
  61 #include "nouveau_dma.h"
  62 #include "nouveau_gem.h"
  63 #include "nouveau_connector.h"
  64 #include "nouveau_encoder.h"
  65 #include "nouveau_fence.h"
  66 #include "nouveau_fbcon.h"
  67
  68 #include <subdev/bios/dp.h>
  69
  70 /******************************************************************************
  71  * EVO channel
  72  *****************************************************************************/
  73
  74 static int
  75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  76                  const s32 *oclass, u8 head, void *data, u32 size,
  77                  struct nv50_chan *chan)
  78 {
  79         struct nvif_sclass *sclass;
  80         int ret, i, n;
  81
  82         chan->device = device;
  83
  84         ret = n = nvif_object_sclass_get(disp, &sclass);
  85         if (ret < 0)
  86                 return ret;
  87
  88         while (oclass[0]) {
  89                 for (i = 0; i < n; i++) {
  90                         if (sclass[i].oclass == oclass[0]) {
  91                                 ret = nvif_object_ctor(disp, "kmsChan", 0,
  92                                                        oclass[0], data, size,
  93                                                        &chan->user);
  94                                 if (ret == 0)
  95                                         nvif_object_map(&chan->user, NULL, 0);
  96                                 nvif_object_sclass_put(&sclass);
  97                                 return ret;
  98                         }
  99                 }
 100                 oclass++;
 101         }
 102
 103         nvif_object_sclass_put(&sclass);
 104         return -ENOSYS;
 105 }
 106
 107 static void
 108 nv50_chan_destroy(struct nv50_chan *chan)
 109 {
 110         nvif_object_dtor(&chan->user);
 111 }
 112
 113 /******************************************************************************
 114  * DMA EVO channel
 115  *****************************************************************************/
 116
 117 void
 118 nv50_dmac_destroy(struct nv50_dmac *dmac)
 119 {
 120         nvif_object_dtor(&dmac->vram);
 121         nvif_object_dtor(&dmac->sync);
 122
 123         nv50_chan_destroy(&dmac->base);
 124
 125         nvif_mem_dtor(&dmac->_push.mem);
 126 }
 127
 128 static void
 129 nv50_dmac_kick(struct nvif_push *push)
 130 {
 131         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 132
 133         dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
 134         if (dmac->put != dmac->cur) {
 135                 /* Push buffer fetches are not coherent with BAR1, we need to ensure
 136                  * writes have been flushed right through to VRAM before writing PUT.
 137                  */
 138                 if (dmac->push->mem.type & NVIF_MEM_VRAM) {
 139                         struct nvif_device *device = dmac->base.device;
 140                         nvif_wr32(&device->object, 0x070000, 0x00000001);
 141                         nvif_msec(device, 2000,
 142                                 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 143                                         break;
 144                         );
 145                 }
 146
 147                 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
 148                 dmac->put = dmac->cur;
 149         }
 150
 151         push->bgn = push->cur;
 152 }
 153
 154 static int
 155 nv50_dmac_free(struct nv50_dmac *dmac)
 156 {
 157         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 158         if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
 159                 return get - dmac->cur - 5;
 160         return dmac->max - dmac->cur;
 161 }
 162
 163 static int
 164 nv50_dmac_wind(struct nv50_dmac *dmac)
 165 {
 166         /* Wait for GET to depart from the beginning of the push buffer to
 167          * prevent writing PUT == GET, which would be ignored by HW.
 168          */
 169         u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
 170         if (get == 0) {
 171                 /* Corner-case, HW idle, but non-committed work pending. */
 172                 if (dmac->put == 0)
 173                         nv50_dmac_kick(dmac->push);
 174
 175                 if (nvif_msec(dmac->base.device, 2000,
 176                         if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
 177                                 break;
 178                 ) < 0)
 179                         return -ETIMEDOUT;
 180         }
 181
 182         PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0));
 183         dmac->cur = 0;
 184         return 0;
 185 }
 186
 187 static int
 188 nv50_dmac_wait(struct nvif_push *push, u32 size)
 189 {
 190         struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push);
 191         int free;
 192
 193         if (WARN_ON(size > dmac->max))
 194                 return -EINVAL;
 195
 196         dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr;
 197         if (dmac->cur + size >= dmac->max) {
 198                 int ret = nv50_dmac_wind(dmac);
 199                 if (ret)
 200                         return ret;
 201
 202                 push->cur = dmac->_push.mem.object.map.ptr;
 203                 push->cur = push->cur + dmac->cur;
 204                 nv50_dmac_kick(push);
 205         }
 206
 207         if (nvif_msec(dmac->base.device, 2000,
 208                 if ((free = nv50_dmac_free(dmac)) >= size)
 209                         break;
 210         ) < 0) {
 211                 WARN_ON(1);
 212                 return -ETIMEDOUT;
 213         }
 214
 215         push->bgn = dmac->_push.mem.object.map.ptr;
 216         push->bgn = push->bgn + dmac->cur;
 217         push->cur = push->bgn;
 218         push->end = push->cur + free;
 219         return 0;
 220 }
 221
 222 int
 223 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 224                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 225                  struct nv50_dmac *dmac)
 226 {
 227         struct nouveau_cli *cli = (void *)device->object.client;
 228         struct nv50_disp_core_channel_dma_v0 *args = data;
 229         u8 type = NVIF_MEM_COHERENT;
 230         int ret;
 231
 232         mutex_init(&dmac->lock);
 233
 234         /* Pascal added support for 47-bit physical addresses, but some
 235          * parts of EVO still only accept 40-bit PAs.
 236          *
 237          * To avoid issues on systems with large amounts of RAM, and on
 238          * systems where an IOMMU maps pages at a high address, we need
 239          * to allocate push buffers in VRAM instead.
 240          *
 241          * This appears to match NVIDIA's behaviour on Pascal.
 242          */
 243         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 244                 type |= NVIF_MEM_VRAM;
 245
 246         ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000,
 247                                 &dmac->_push.mem);
 248         if (ret)
 249                 return ret;
 250
 251         dmac->ptr = dmac->_push.mem.object.map.ptr;
 252         dmac->_push.wait = nv50_dmac_wait;
 253         dmac->_push.kick = nv50_dmac_kick;
 254         dmac->push = &dmac->_push;
 255         dmac->push->bgn = dmac->_push.mem.object.map.ptr;
 256         dmac->push->cur = dmac->push->bgn;
 257         dmac->push->end = dmac->push->bgn;
 258         dmac->max = 0x1000/4 - 1;
 259
 260         args->pushbuf = nvif_handle(&dmac->_push.mem.object);
 261
 262         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 263                                &dmac->base);
 264         if (ret)
 265                 return ret;
 266
 267         if (!syncbuf)
 268                 return 0;
 269
 270         ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
 271                                NV_DMA_IN_MEMORY,
 272                                &(struct nv_dma_v0) {
 273                                         .target = NV_DMA_V0_TARGET_VRAM,
 274                                         .access = NV_DMA_V0_ACCESS_RDWR,
 275                                         .start = syncbuf + 0x0000,
 276                                         .limit = syncbuf + 0x0fff,
 277                                }, sizeof(struct nv_dma_v0),
 278                                &dmac->sync);
 279         if (ret)
 280                 return ret;
 281
 282         ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
 283                                NV_DMA_IN_MEMORY,
 284                                &(struct nv_dma_v0) {
 285                                         .target = NV_DMA_V0_TARGET_VRAM,
 286                                         .access = NV_DMA_V0_ACCESS_RDWR,
 287                                         .start = 0,
 288                                         .limit = device->info.ram_user - 1,
 289                                }, sizeof(struct nv_dma_v0),
 290                                &dmac->vram);
 291         if (ret)
 292                 return ret;
 293
 294         return ret;
 295 }
 296
 297 /******************************************************************************
 298  * Output path helpers
 299  *****************************************************************************/
 300 static void
 301 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 302 {
 303         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 304         struct {
 305                 struct nv50_disp_mthd_v1 base;
 306         } args = {
 307                 .base.version = 1,
 308                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 309                 .base.hasht  = nv_encoder->dcb->hasht,
 310                 .base.hashm  = nv_encoder->dcb->hashm,
 311         };
 312
 313         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 314         nv_encoder->or = -1;
 315         nv_encoder->link = 0;
 316 }
 317
 318 static int
 319 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
 320 {
 321         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 322         struct nv50_disp *disp = nv50_disp(drm->dev);
 323         struct {
 324                 struct nv50_disp_mthd_v1 base;
 325                 struct nv50_disp_acquire_v0 info;
 326         } args = {
 327                 .base.version = 1,
 328                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 329                 .base.hasht  = nv_encoder->dcb->hasht,
 330                 .base.hashm  = nv_encoder->dcb->hashm,
 331                 .info.hda = hda,
 332         };
 333         int ret;
 334
 335         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 336         if (ret) {
 337                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 338                 return ret;
 339         }
 340
 341         nv_encoder->or = args.info.or;
 342         nv_encoder->link = args.info.link;
 343         return 0;
 344 }
 345
 346 static int
 347 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 348                             struct drm_crtc_state *crtc_state,
 349                             struct drm_connector_state *conn_state,
 350                             struct drm_display_mode *native_mode)
 351 {
 352         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 353         struct drm_display_mode *mode = &crtc_state->mode;
 354         struct drm_connector *connector = conn_state->connector;
 355         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 356         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 357
 358         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 359         asyc->scaler.full = false;
 360         if (!native_mode)
 361                 return 0;
 362
 363         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 364                 switch (connector->connector_type) {
 365                 case DRM_MODE_CONNECTOR_LVDS:
 366                 case DRM_MODE_CONNECTOR_eDP:
 367                         /* Don't force scaler for EDID modes with
 368                          * same size as the native one (e.g. different
 369                          * refresh rate)
 370                          */
 371                         if (mode->hdisplay == native_mode->hdisplay &&
 372                             mode->vdisplay == native_mode->vdisplay &&
 373                             mode->type & DRM_MODE_TYPE_DRIVER)
 374                                 break;
 375                         mode = native_mode;
 376                         asyc->scaler.full = true;
 377                         break;
 378                 default:
 379                         break;
 380                 }
 381         } else {
 382                 mode = native_mode;
 383         }
 384
 385         if (!drm_mode_equal(adjusted_mode, mode)) {
 386                 drm_mode_copy(adjusted_mode, mode);
 387                 crtc_state->mode_changed = true;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int
 394 nv50_outp_atomic_check(struct drm_encoder *encoder,
 395                        struct drm_crtc_state *crtc_state,
 396                        struct drm_connector_state *conn_state)
 397 {
 398         struct drm_connector *connector = conn_state->connector;
 399         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 400         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 401         int ret;
 402
 403         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 404                                           nv_connector->native_mode);
 405         if (ret)
 406                 return ret;
 407
 408         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 409                 asyh->or.bpc = connector->display_info.bpc;
 410
 411         return 0;
 412 }
 413
 414 struct nouveau_connector *
 415 nv50_outp_get_new_connector(struct nouveau_encoder *outp,
 416                             struct drm_atomic_state *state)
 417 {
 418         struct drm_connector *connector;
 419         struct drm_connector_state *connector_state;
 420         struct drm_encoder *encoder = to_drm_encoder(outp);
 421         int i;
 422
 423         for_each_new_connector_in_state(state, connector, connector_state, i) {
 424                 if (connector_state->best_encoder == encoder)
 425                         return nouveau_connector(connector);
 426         }
 427
 428         return NULL;
 429 }
 430
 431 struct nouveau_connector *
 432 nv50_outp_get_old_connector(struct nouveau_encoder *outp,
 433                             struct drm_atomic_state *state)
 434 {
 435         struct drm_connector *connector;
 436         struct drm_connector_state *connector_state;
 437         struct drm_encoder *encoder = to_drm_encoder(outp);
 438         int i;
 439
 440         for_each_old_connector_in_state(state, connector, connector_state, i) {
 441                 if (connector_state->best_encoder == encoder)
 442                         return nouveau_connector(connector);
 443         }
 444
 445         return NULL;
 446 }
 447
 448 /******************************************************************************
 449  * DAC
 450  *****************************************************************************/
 451 static void
 452 nv50_dac_disable(struct drm_encoder *encoder)
 453 {
 454         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 455         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 456         const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE);
 457         if (nv_encoder->crtc)
 458                 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL);
 459         nv_encoder->crtc = NULL;
 460         nv50_outp_release(nv_encoder);
 461 }
 462
 463 static void
 464 nv50_dac_enable(struct drm_encoder *encoder)
 465 {
 466         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 467         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 468         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 469         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 470         u32 ctrl = 0;
 471
 472         switch (nv_crtc->index) {
 473         case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break;
 474         case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break;
 475         case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break;
 476         case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break;
 477         default:
 478                 WARN_ON(1);
 479                 break;
 480         }
 481
 482         ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT);
 483
 484         nv50_outp_acquire(nv_encoder, false);
 485
 486         core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh);
 487         asyh->or.depth = 0;
 488
 489         nv_encoder->crtc = encoder->crtc;
 490 }
 491
 492 static enum drm_connector_status
 493 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 494 {
 495         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 496         struct nv50_disp *disp = nv50_disp(encoder->dev);
 497         struct {
 498                 struct nv50_disp_mthd_v1 base;
 499                 struct nv50_disp_dac_load_v0 load;
 500         } args = {
 501                 .base.version = 1,
 502                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 503                 .base.hasht  = nv_encoder->dcb->hasht,
 504                 .base.hashm  = nv_encoder->dcb->hashm,
 505         };
 506         int ret;
 507
 508         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 509         if (args.load.data == 0)
 510                 args.load.data = 340;
 511
 512         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 513         if (ret || !args.load.load)
 514                 return connector_status_disconnected;
 515
 516         return connector_status_connected;
 517 }
 518
 519 static const struct drm_encoder_helper_funcs
 520 nv50_dac_help = {
 521         .atomic_check = nv50_outp_atomic_check,
 522         .enable = nv50_dac_enable,
 523         .disable = nv50_dac_disable,
 524         .detect = nv50_dac_detect
 525 };
 526
 527 static void
 528 nv50_dac_destroy(struct drm_encoder *encoder)
 529 {
 530         drm_encoder_cleanup(encoder);
 531         kfree(encoder);
 532 }
 533
 534 static const struct drm_encoder_funcs
 535 nv50_dac_func = {
 536         .destroy = nv50_dac_destroy,
 537 };
 538
 539 static int
 540 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 541 {
 542         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 543         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 544         struct nvkm_i2c_bus *bus;
 545         struct nouveau_encoder *nv_encoder;
 546         struct drm_encoder *encoder;
 547         int type = DRM_MODE_ENCODER_DAC;
 548
 549         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 550         if (!nv_encoder)
 551                 return -ENOMEM;
 552         nv_encoder->dcb = dcbe;
 553
 554         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 555         if (bus)
 556                 nv_encoder->i2c = &bus->i2c;
 557
 558         encoder = to_drm_encoder(nv_encoder);
 559         encoder->possible_crtcs = dcbe->heads;
 560         encoder->possible_clones = 0;
 561         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 562                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 563         drm_encoder_helper_add(encoder, &nv50_dac_help);
 564
 565         drm_connector_attach_encoder(connector, encoder);
 566         return 0;
 567 }
 568
 569 /*
 570  * audio component binding for ELD notification
 571  */
 572 static void
 573 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 574                                 int dev_id)
 575 {
 576         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 577                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 578                                                  port, dev_id);
 579 }
 580
 581 static int
 582 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 583                              bool *enabled, unsigned char *buf, int max_bytes)
 584 {
 585         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 586         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 587         struct drm_encoder *encoder;
 588         struct nouveau_encoder *nv_encoder;
 589         struct drm_connector *connector;
 590         struct nouveau_crtc *nv_crtc;
 591         struct drm_connector_list_iter conn_iter;
 592         int ret = 0;
 593
 594         *enabled = false;
 595
 596         drm_for_each_encoder(encoder, drm->dev) {
 597                 struct nouveau_connector *nv_connector = NULL;
 598
 599                 nv_encoder = nouveau_encoder(encoder);
 600
 601                 drm_connector_list_iter_begin(drm_dev, &conn_iter);
 602                 drm_for_each_connector_iter(connector, &conn_iter) {
 603                         if (connector->state->best_encoder == encoder) {
 604                                 nv_connector = nouveau_connector(connector);
 605                                 break;
 606                         }
 607                 }
 608                 drm_connector_list_iter_end(&conn_iter);
 609                 if (!nv_connector)
 610                         continue;
 611
 612                 nv_crtc = nouveau_crtc(encoder->crtc);
 613                 if (!nv_crtc || nv_encoder->or != port ||
 614                     nv_crtc->index != dev_id)
 615                         continue;
 616                 *enabled = nv_encoder->audio;
 617                 if (*enabled) {
 618                         ret = drm_eld_size(nv_connector->base.eld);
 619                         memcpy(buf, nv_connector->base.eld,
 620                                min(max_bytes, ret));
 621                 }
 622                 break;
 623         }
 624
 625         return ret;
 626 }
 627
 628 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 629         .get_eld = nv50_audio_component_get_eld,
 630 };
 631
 632 static int
 633 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 634                           void *data)
 635 {
 636         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 637         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 638         struct drm_audio_component *acomp = data;
 639
 640         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 641                 return -ENOMEM;
 642
 643         drm_modeset_lock_all(drm_dev);
 644         acomp->ops = &nv50_audio_component_ops;
 645         acomp->dev = kdev;
 646         drm->audio.component = acomp;
 647         drm_modeset_unlock_all(drm_dev);
 648         return 0;
 649 }
 650
 651 static void
 652 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 653                             void *data)
 654 {
 655         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 656         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 657         struct drm_audio_component *acomp = data;
 658
 659         drm_modeset_lock_all(drm_dev);
 660         drm->audio.component = NULL;
 661         acomp->ops = NULL;
 662         acomp->dev = NULL;
 663         drm_modeset_unlock_all(drm_dev);
 664 }
 665
 666 static const struct component_ops nv50_audio_component_bind_ops = {
 667         .bind   = nv50_audio_component_bind,
 668         .unbind = nv50_audio_component_unbind,
 669 };
 670
 671 static void
 672 nv50_audio_component_init(struct nouveau_drm *drm)
 673 {
 674         if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 675                 drm->audio.component_registered = true;
 676 }
 677
 678 static void
 679 nv50_audio_component_fini(struct nouveau_drm *drm)
 680 {
 681         if (drm->audio.component_registered) {
 682                 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 683                 drm->audio.component_registered = false;
 684         }
 685 }
 686
 687 /******************************************************************************
 688  * Audio
 689  *****************************************************************************/
 690 static void
 691 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 692 {
 693         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 694         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 695         struct nv50_disp *disp = nv50_disp(encoder->dev);
 696         struct {
 697                 struct nv50_disp_mthd_v1 base;
 698                 struct nv50_disp_sor_hda_eld_v0 eld;
 699         } args = {
 700                 .base.version = 1,
 701                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 702                 .base.hasht   = nv_encoder->dcb->hasht,
 703                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 704                                 (0x0100 << nv_crtc->index),
 705         };
 706
 707         if (!nv_encoder->audio)
 708                 return;
 709
 710         nv_encoder->audio = false;
 711         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 712
 713         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 714                                         nv_crtc->index);
 715 }
 716
 717 static void
 718 nv50_audio_enable(struct drm_encoder *encoder, struct drm_atomic_state *state,
 719                   struct drm_display_mode *mode)
 720 {
 721         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 722         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 723         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 724         struct nouveau_connector *nv_connector;
 725         struct nv50_disp *disp = nv50_disp(encoder->dev);
 726         struct __packed {
 727                 struct {
 728                         struct nv50_disp_mthd_v1 mthd;
 729                         struct nv50_disp_sor_hda_eld_v0 eld;
 730                 } base;
 731                 u8 data[sizeof(nv_connector->base.eld)];
 732         } args = {
 733                 .base.mthd.version = 1,
 734                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 735                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 736                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 737                                      (0x0100 << nv_crtc->index),
 738         };
 739
 740         nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
 741         if (!drm_detect_monitor_audio(nv_connector->edid))
 742                 return;
 743
 744         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 745
 746         nvif_mthd(&disp->disp->object, 0, &args,
 747                   sizeof(args.base) + drm_eld_size(args.data));
 748         nv_encoder->audio = true;
 749
 750         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 751                                         nv_crtc->index);
 752 }
 753
 754 /******************************************************************************
 755  * HDMI
 756  *****************************************************************************/
 757 static void
 758 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 759 {
 760         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 761         struct nv50_disp *disp = nv50_disp(encoder->dev);
 762         struct {
 763                 struct nv50_disp_mthd_v1 base;
 764                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 765         } args = {
 766                 .base.version = 1,
 767                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 768                 .base.hasht  = nv_encoder->dcb->hasht,
 769                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 770                                (0x0100 << nv_crtc->index),
 771         };
 772
 773         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 774 }
 775
 776 static void
 777 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_atomic_state *state,
 778                  struct drm_display_mode *mode)
 779 {
 780         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 781         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 782         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 783         struct nv50_disp *disp = nv50_disp(encoder->dev);
 784         struct {
 785                 struct nv50_disp_mthd_v1 base;
 786                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 787                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 788         } args = {
 789                 .base.version = 1,
 790                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 791                 .base.hasht  = nv_encoder->dcb->hasht,
 792                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 793                                (0x0100 << nv_crtc->index),
 794                 .pwr.state = 1,
 795                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 796         };
 797         struct nouveau_connector *nv_connector;
 798         struct drm_hdmi_info *hdmi;
 799         u32 max_ac_packet;
 800         union hdmi_infoframe avi_frame;
 801         union hdmi_infoframe vendor_frame;
 802         bool high_tmds_clock_ratio = false, scrambling = false;
 803         u8 config;
 804         int ret;
 805         int size;
 806
 807         nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
 808         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 809                 return;
 810
 811         hdmi = &nv_connector->base.display_info.hdmi;
 812
 813         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 814                                                        &nv_connector->base, mode);
 815         if (!ret) {
 816                 /* We have an AVI InfoFrame, populate it to the display */
 817                 args.pwr.avi_infoframe_length
 818                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 819         }
 820
 821         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 822                                                           &nv_connector->base, mode);
 823         if (!ret) {
 824                 /* We have a Vendor InfoFrame, populate it to the display */
 825                 args.pwr.vendor_infoframe_length
 826                         = hdmi_infoframe_pack(&vendor_frame,
 827                                               args.infoframes
 828                                               + args.pwr.avi_infoframe_length,
 829                                               17);
 830         }
 831
 832         max_ac_packet  = mode->htotal - mode->hdisplay;
 833         max_ac_packet -= args.pwr.rekey;
 834         max_ac_packet -= 18; /* constant from tegra */
 835         args.pwr.max_ac_packet = max_ac_packet / 32;
 836
 837         if (hdmi->scdc.scrambling.supported) {
 838                 high_tmds_clock_ratio = mode->clock > 340000;
 839                 scrambling = high_tmds_clock_ratio ||
 840                         hdmi->scdc.scrambling.low_rates;
 841         }
 842
 843         args.pwr.scdc =
 844                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 845                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 846
 847         size = sizeof(args.base)
 848                 + sizeof(args.pwr)
 849                 + args.pwr.avi_infoframe_length
 850                 + args.pwr.vendor_infoframe_length;
 851         nvif_mthd(&disp->disp->object, 0, &args, size);
 852
 853         nv50_audio_enable(encoder, state, mode);
 854
 855         /* If SCDC is supported by the downstream monitor, update
 856          * divider / scrambling settings to what we programmed above.
 857          */
 858         if (!hdmi->scdc.scrambling.supported)
 859                 return;
 860
 861         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 862         if (ret < 0) {
 863                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 864                 return;
 865         }
 866         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 867         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 868         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 869         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 870         if (ret < 0)
 871                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 872                          config, ret);
 873 }
 874
 875 /******************************************************************************
 876  * MST
 877  *****************************************************************************/
 878 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 879 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 880 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 881
 882 struct nv50_mstm {
 883         struct nouveau_encoder *outp;
 884
 885         struct drm_dp_mst_topology_mgr mgr;
 886
 887         bool modified;
 888         bool disabled;
 889         int links;
 890 };
 891
 892 struct nv50_mstc {
 893         struct nv50_mstm *mstm;
 894         struct drm_dp_mst_port *port;
 895         struct drm_connector connector;
 896
 897         struct drm_display_mode *native;
 898         struct edid *edid;
 899 };
 900
 901 struct nv50_msto {
 902         struct drm_encoder encoder;
 903
 904         struct nv50_head *head;
 905         struct nv50_mstc *mstc;
 906         bool disabled;
 907 };
 908
 909 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder)
 910 {
 911         struct nv50_msto *msto;
 912
 913         if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
 914                 return nouveau_encoder(encoder);
 915
 916         msto = nv50_msto(encoder);
 917         if (!msto->mstc)
 918                 return NULL;
 919         return msto->mstc->mstm->outp;
 920 }
 921
 922 static struct drm_dp_payload *
 923 nv50_msto_payload(struct nv50_msto *msto)
 924 {
 925         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 926         struct nv50_mstc *mstc = msto->mstc;
 927         struct nv50_mstm *mstm = mstc->mstm;
 928         int vcpi = mstc->port->vcpi.vcpi, i;
 929
 930         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 931
 932         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 933         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 934                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 935                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 936                           mstm->outp->base.base.name, i, payload->vcpi,
 937                           payload->start_slot, payload->num_slots);
 938         }
 939
 940         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 941                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 942                 if (payload->vcpi == vcpi)
 943                         return payload;
 944         }
 945
 946         return NULL;
 947 }
 948
 949 static void
 950 nv50_msto_cleanup(struct nv50_msto *msto)
 951 {
 952         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 953         struct nv50_mstc *mstc = msto->mstc;
 954         struct nv50_mstm *mstm = mstc->mstm;
 955
 956         if (!msto->disabled)
 957                 return;
 958
 959         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 960
 961         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 962
 963         msto->mstc = NULL;
 964         msto->disabled = false;
 965 }
 966
 967 static void
 968 nv50_msto_prepare(struct nv50_msto *msto)
 969 {
 970         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 971         struct nv50_mstc *mstc = msto->mstc;
 972         struct nv50_mstm *mstm = mstc->mstm;
 973         struct {
 974                 struct nv50_disp_mthd_v1 base;
 975                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 976         } args = {
 977                 .base.version = 1,
 978                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 979                 .base.hasht  = mstm->outp->dcb->hasht,
 980                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 981                                (0x0100 << msto->head->base.index),
 982         };
 983
 984         mutex_lock(&mstm->mgr.payload_lock);
 985
 986         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 987         if (mstc->port->vcpi.vcpi > 0) {
 988                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 989                 if (payload) {
 990                         args.vcpi.start_slot = payload->start_slot;
 991                         args.vcpi.num_slots = payload->num_slots;
 992                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 993                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 994                 }
 995         }
 996
 997         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 998                   msto->encoder.name, msto->head->base.base.name,
 999                   args.vcpi.start_slot, args.vcpi.num_slots,
1000                   args.vcpi.pbn, args.vcpi.aligned_pbn);
1001
1002         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
1003         mutex_unlock(&mstm->mgr.payload_lock);
1004 }
1005
1006 static int
1007 nv50_msto_atomic_check(struct drm_encoder *encoder,
1008                        struct drm_crtc_state *crtc_state,
1009                        struct drm_connector_state *conn_state)
1010 {
1011         struct drm_atomic_state *state = crtc_state->state;
1012         struct drm_connector *connector = conn_state->connector;
1013         struct nv50_mstc *mstc = nv50_mstc(connector);
1014         struct nv50_mstm *mstm = mstc->mstm;
1015         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
1016         int slots;
1017         int ret;
1018
1019         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
1020                                           mstc->native);
1021         if (ret)
1022                 return ret;
1023
1024         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
1025                 return 0;
1026
1027         /*
1028          * When restoring duplicated states, we need to make sure that the bw
1029          * remains the same and avoid recalculating it, as the connector's bpc
1030          * may have changed after the state was duplicated
1031          */
1032         if (!state->duplicated) {
1033                 const int clock = crtc_state->adjusted_mode.clock;
1034
1035                 asyh->or.bpc = connector->display_info.bpc;
1036                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
1037                                                     false);
1038         }
1039
1040         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
1041                                               asyh->dp.pbn, 0);
1042         if (slots < 0)
1043                 return slots;
1044
1045         asyh->dp.tu = slots;
1046
1047         return 0;
1048 }
1049
1050 static u8
1051 nv50_dp_bpc_to_depth(unsigned int bpc)
1052 {
1053         switch (bpc) {
1054         case  6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
1055         case  8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
1056         case 10:
1057         default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
1058         }
1059 }
1060
1061 static void
1062 nv50_msto_enable(struct drm_encoder *encoder)
1063 {
1064         struct nv50_head *head = nv50_head(encoder->crtc);
1065         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
1066         struct nv50_msto *msto = nv50_msto(encoder);
1067         struct nv50_mstc *mstc = NULL;
1068         struct nv50_mstm *mstm = NULL;
1069         struct drm_connector *connector;
1070         struct drm_connector_list_iter conn_iter;
1071         u8 proto;
1072         bool r;
1073
1074         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1075         drm_for_each_connector_iter(connector, &conn_iter) {
1076                 if (connector->state->best_encoder == &msto->encoder) {
1077                         mstc = nv50_mstc(connector);
1078                         mstm = mstc->mstm;
1079                         break;
1080                 }
1081         }
1082         drm_connector_list_iter_end(&conn_iter);
1083
1084         if (WARN_ON(!mstc))
1085                 return;
1086
1087         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
1088                                      armh->dp.tu);
1089         if (!r)
1090                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
1091
1092         if (!mstm->links++)
1093                 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
1094
1095         if (mstm->outp->link & 1)
1096                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1097         else
1098                 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1099
1100         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
1101                            nv50_dp_bpc_to_depth(armh->or.bpc));
1102
1103         msto->mstc = mstc;
1104         mstm->modified = true;
1105 }
1106
1107 static void
1108 nv50_msto_disable(struct drm_encoder *encoder)
1109 {
1110         struct nv50_msto *msto = nv50_msto(encoder);
1111         struct nv50_mstc *mstc = msto->mstc;
1112         struct nv50_mstm *mstm = mstc->mstm;
1113
1114         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
1115
1116         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1117         mstm->modified = true;
1118         if (!--mstm->links)
1119                 mstm->disabled = true;
1120         msto->disabled = true;
1121 }
1122
1123 static const struct drm_encoder_helper_funcs
1124 nv50_msto_help = {
1125         .disable = nv50_msto_disable,
1126         .enable = nv50_msto_enable,
1127         .atomic_check = nv50_msto_atomic_check,
1128 };
1129
1130 static void
1131 nv50_msto_destroy(struct drm_encoder *encoder)
1132 {
1133         struct nv50_msto *msto = nv50_msto(encoder);
1134         drm_encoder_cleanup(&msto->encoder);
1135         kfree(msto);
1136 }
1137
1138 static const struct drm_encoder_funcs
1139 nv50_msto = {
1140         .destroy = nv50_msto_destroy,
1141 };
1142
1143 static struct nv50_msto *
1144 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1145 {
1146         struct nv50_msto *msto;
1147         int ret;
1148
1149         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1150         if (!msto)
1151                 return ERR_PTR(-ENOMEM);
1152
1153         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1154                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1155         if (ret) {
1156                 kfree(msto);
1157                 return ERR_PTR(ret);
1158         }
1159
1160         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1161         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1162         msto->head = head;
1163         return msto;
1164 }
1165
1166 static struct drm_encoder *
1167 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1168                               struct drm_connector_state *connector_state)
1169 {
1170         struct nv50_mstc *mstc = nv50_mstc(connector);
1171         struct drm_crtc *crtc = connector_state->crtc;
1172
1173         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1174                 return NULL;
1175
1176         return &nv50_head(crtc)->msto->encoder;
1177 }
1178
1179 static enum drm_mode_status
1180 nv50_mstc_mode_valid(struct drm_connector *connector,
1181                      struct drm_display_mode *mode)
1182 {
1183         struct nv50_mstc *mstc = nv50_mstc(connector);
1184         struct nouveau_encoder *outp = mstc->mstm->outp;
1185
1186         /* TODO: calculate the PBN from the dotclock and validate against the
1187          * MSTB's max possible PBN
1188          */
1189
1190         return nv50_dp_mode_valid(connector, outp, mode, NULL);
1191 }
1192
1193 static int
1194 nv50_mstc_get_modes(struct drm_connector *connector)
1195 {
1196         struct nv50_mstc *mstc = nv50_mstc(connector);
1197         int ret = 0;
1198
1199         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1200         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1201         if (mstc->edid)
1202                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1203
1204         /*
1205          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1206          * to 8 to save bandwidth on the topology. In the future, we'll want
1207          * to properly fix this by dynamically selecting the highest possible
1208          * bpc that would fit in the topology
1209          */
1210         if (connector->display_info.bpc)
1211                 connector->display_info.bpc =
1212                         clamp(connector->display_info.bpc, 6U, 8U);
1213         else
1214                 connector->display_info.bpc = 8;
1215
1216         if (mstc->native)
1217                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1218         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1219         return ret;
1220 }
1221
1222 static int
1223 nv50_mstc_atomic_check(struct drm_connector *connector,
1224                        struct drm_atomic_state *state)
1225 {
1226         struct nv50_mstc *mstc = nv50_mstc(connector);
1227         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1228         struct drm_connector_state *new_conn_state =
1229                 drm_atomic_get_new_connector_state(state, connector);
1230         struct drm_connector_state *old_conn_state =
1231                 drm_atomic_get_old_connector_state(state, connector);
1232         struct drm_crtc_state *crtc_state;
1233         struct drm_crtc *new_crtc = new_conn_state->crtc;
1234
1235         if (!old_conn_state->crtc)
1236                 return 0;
1237
1238         /* We only want to free VCPI if this state disables the CRTC on this
1239          * connector
1240          */
1241         if (new_crtc) {
1242                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1243
1244                 if (!crtc_state ||
1245                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1246                     crtc_state->enable)
1247                         return 0;
1248         }
1249
1250         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1251 }
1252
1253 static int
1254 nv50_mstc_detect(struct drm_connector *connector,
1255                  struct drm_modeset_acquire_ctx *ctx, bool force)
1256 {
1257         struct nv50_mstc *mstc = nv50_mstc(connector);
1258         int ret;
1259
1260         if (drm_connector_is_unregistered(connector))
1261                 return connector_status_disconnected;
1262
1263         ret = pm_runtime_get_sync(connector->dev->dev);
1264         if (ret < 0 && ret != -EACCES) {
1265                 pm_runtime_put_autosuspend(connector->dev->dev);
1266                 return connector_status_disconnected;
1267         }
1268
1269         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1270                                      mstc->port);
1271
1272         pm_runtime_mark_last_busy(connector->dev->dev);
1273         pm_runtime_put_autosuspend(connector->dev->dev);
1274         return ret;
1275 }
1276
1277 static const struct drm_connector_helper_funcs
1278 nv50_mstc_help = {
1279         .get_modes = nv50_mstc_get_modes,
1280         .mode_valid = nv50_mstc_mode_valid,
1281         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1282         .atomic_check = nv50_mstc_atomic_check,
1283         .detect_ctx = nv50_mstc_detect,
1284 };
1285
1286 static void
1287 nv50_mstc_destroy(struct drm_connector *connector)
1288 {
1289         struct nv50_mstc *mstc = nv50_mstc(connector);
1290
1291         drm_connector_cleanup(&mstc->connector);
1292         drm_dp_mst_put_port_malloc(mstc->port);
1293
1294         kfree(mstc);
1295 }
1296
1297 static const struct drm_connector_funcs
1298 nv50_mstc = {
1299         .reset = nouveau_conn_reset,
1300         .fill_modes = drm_helper_probe_single_connector_modes,
1301         .destroy = nv50_mstc_destroy,
1302         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1303         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1304         .atomic_set_property = nouveau_conn_atomic_set_property,
1305         .atomic_get_property = nouveau_conn_atomic_get_property,
1306 };
1307
1308 static int
1309 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1310               const char *path, struct nv50_mstc **pmstc)
1311 {
1312         struct drm_device *dev = mstm->outp->base.base.dev;
1313         struct drm_crtc *crtc;
1314         struct nv50_mstc *mstc;
1315         int ret;
1316
1317         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1318                 return -ENOMEM;
1319         mstc->mstm = mstm;
1320         mstc->port = port;
1321
1322         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1323                                  DRM_MODE_CONNECTOR_DisplayPort);
1324         if (ret) {
1325                 kfree(*pmstc);
1326                 *pmstc = NULL;
1327                 return ret;
1328         }
1329
1330         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1331
1332         mstc->connector.funcs->reset(&mstc->connector);
1333         nouveau_conn_attach_properties(&mstc->connector);
1334
1335         drm_for_each_crtc(crtc, dev) {
1336                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1337                         continue;
1338
1339                 drm_connector_attach_encoder(&mstc->connector,
1340                                              &nv50_head(crtc)->msto->encoder);
1341         }
1342
1343         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1344         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1345         drm_connector_set_path_property(&mstc->connector, path);
1346         drm_dp_mst_get_port_malloc(port);
1347         return 0;
1348 }
1349
1350 static void
1351 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1352 {
1353         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1354         struct drm_encoder *encoder;
1355         int ret;
1356
1357         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1358         ret = drm_dp_check_act_status(&mstm->mgr);
1359
1360         ret = drm_dp_update_payload_part2(&mstm->mgr);
1361
1362         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1363                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1364                         struct nv50_msto *msto = nv50_msto(encoder);
1365                         struct nv50_mstc *mstc = msto->mstc;
1366                         if (mstc && mstc->mstm == mstm)
1367                                 nv50_msto_cleanup(msto);
1368                 }
1369         }
1370
1371         mstm->modified = false;
1372 }
1373
1374 static void
1375 nv50_mstm_prepare(struct nv50_mstm *mstm)
1376 {
1377         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1378         struct drm_encoder *encoder;
1379         int ret;
1380
1381         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1382         ret = drm_dp_update_payload_part1(&mstm->mgr);
1383
1384         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1385                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1386                         struct nv50_msto *msto = nv50_msto(encoder);
1387                         struct nv50_mstc *mstc = msto->mstc;
1388                         if (mstc && mstc->mstm == mstm)
1389                                 nv50_msto_prepare(msto);
1390                 }
1391         }
1392
1393         if (mstm->disabled) {
1394                 if (!mstm->links)
1395                         nv50_outp_release(mstm->outp);
1396                 mstm->disabled = false;
1397         }
1398 }
1399
1400 static struct drm_connector *
1401 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1402                         struct drm_dp_mst_port *port, const char *path)
1403 {
1404         struct nv50_mstm *mstm = nv50_mstm(mgr);
1405         struct nv50_mstc *mstc;
1406         int ret;
1407
1408         ret = nv50_mstc_new(mstm, port, path, &mstc);
1409         if (ret)
1410                 return NULL;
1411
1412         return &mstc->connector;
1413 }
1414
1415 static const struct drm_dp_mst_topology_cbs
1416 nv50_mstm = {
1417         .add_connector = nv50_mstm_add_connector,
1418 };
1419
1420 void
1421 nv50_mstm_service(struct nv50_mstm *mstm)
1422 {
1423         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1424         bool handled = true;
1425         int ret;
1426         u8 esi[8] = {};
1427
1428         if (!aux)
1429                 return;
1430
1431         while (handled) {
1432                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1433                 if (ret != 8) {
1434                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1435                         return;
1436                 }
1437
1438                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1439                 if (!handled)
1440                         break;
1441
1442                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1443         }
1444 }
1445
1446 void
1447 nv50_mstm_remove(struct nv50_mstm *mstm)
1448 {
1449         if (mstm)
1450                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1451 }
1452
1453 static int
1454 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1455 {
1456         struct nouveau_encoder *outp = mstm->outp;
1457         struct {
1458                 struct nv50_disp_mthd_v1 base;
1459                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1460         } args = {
1461                 .base.version = 1,
1462                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1463                 .base.hasht = outp->dcb->hasht,
1464                 .base.hashm = outp->dcb->hashm,
1465                 .mst.state = state,
1466         };
1467         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1468         struct nvif_object *disp = &drm->display->disp.object;
1469         int ret;
1470
1471         if (dpcd >= 0x12) {
1472                 /* Even if we're enabling MST, start with disabling the
1473                  * branching unit to clear any sink-side MST topology state
1474                  * that wasn't set by us
1475                  */
1476                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1477                 if (ret < 0)
1478                         return ret;
1479
1480                 if (state) {
1481                         /* Now, start initializing */
1482                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1483                                                  DP_MST_EN);
1484                         if (ret < 0)
1485                                 return ret;
1486                 }
1487         }
1488
1489         return nvif_mthd(disp, 0, &args, sizeof(args));
1490 }
1491
1492 int
1493 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1494 {
1495         struct drm_dp_aux *aux;
1496         int ret;
1497         bool old_state, new_state;
1498         u8 mstm_ctrl;
1499
1500         if (!mstm)
1501                 return 0;
1502
1503         mutex_lock(&mstm->mgr.lock);
1504
1505         old_state = mstm->mgr.mst_state;
1506         new_state = old_state;
1507         aux = mstm->mgr.aux;
1508
1509         if (old_state) {
1510                 /* Just check that the MST hub is still as we expect it */
1511                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1512                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1513                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1514                         new_state = false;
1515                 }
1516         } else if (dpcd[0] >= 0x12) {
1517                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1518                 if (ret < 0)
1519                         goto probe_error;
1520
1521                 if (!(dpcd[1] & DP_MST_CAP))
1522                         dpcd[0] = 0x11;
1523                 else
1524                         new_state = allow;
1525         }
1526
1527         if (new_state == old_state) {
1528                 mutex_unlock(&mstm->mgr.lock);
1529                 return new_state;
1530         }
1531
1532         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1533         if (ret)
1534                 goto probe_error;
1535
1536         mutex_unlock(&mstm->mgr.lock);
1537
1538         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1539         if (ret)
1540                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1541
1542         return new_state;
1543
1544 probe_error:
1545         mutex_unlock(&mstm->mgr.lock);
1546         return ret;
1547 }
1548
1549 static void
1550 nv50_mstm_fini(struct nv50_mstm *mstm)
1551 {
1552         if (mstm && mstm->mgr.mst_state)
1553                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1554 }
1555
1556 static void
1557 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1558 {
1559         int ret;
1560
1561         if (!mstm || !mstm->mgr.mst_state)
1562                 return;
1563
1564         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1565         if (ret == -1) {
1566                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1567                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1568         }
1569 }
1570
1571 static void
1572 nv50_mstm_del(struct nv50_mstm **pmstm)
1573 {
1574         struct nv50_mstm *mstm = *pmstm;
1575         if (mstm) {
1576                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1577                 kfree(*pmstm);
1578                 *pmstm = NULL;
1579         }
1580 }
1581
1582 static int
1583 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1584               int conn_base_id, struct nv50_mstm **pmstm)
1585 {
1586         const int max_payloads = hweight8(outp->dcb->heads);
1587         struct drm_device *dev = outp->base.base.dev;
1588         struct nv50_mstm *mstm;
1589         int ret;
1590
1591         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1592                 return -ENOMEM;
1593         mstm->outp = outp;
1594         mstm->mgr.cbs = &nv50_mstm;
1595
1596         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1597                                            max_payloads, conn_base_id);
1598         if (ret)
1599                 return ret;
1600
1601         return 0;
1602 }
1603
1604 /******************************************************************************
1605  * SOR
1606  *****************************************************************************/
1607 static void
1608 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1609                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1610 {
1611         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1612         struct nv50_core *core = disp->core;
1613
1614         if (!asyh) {
1615                 nv_encoder->ctrl &= ~BIT(head);
1616                 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1617                         nv_encoder->ctrl = 0;
1618         } else {
1619                 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1620                 nv_encoder->ctrl |= BIT(head);
1621                 asyh->or.depth = depth;
1622         }
1623
1624         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1625 }
1626
1627 static void
1628 nv50_sor_disable(struct drm_encoder *encoder,
1629                  struct drm_atomic_state *state)
1630 {
1631         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1632         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1633
1634         nv_encoder->crtc = NULL;
1635
1636         if (nv_crtc) {
1637                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1638                 u8 pwr;
1639
1640                 if (aux) {
1641                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1642                         if (ret == 0) {
1643                                 pwr &= ~DP_SET_POWER_MASK;
1644                                 pwr |=  DP_SET_POWER_D3;
1645                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1646                         }
1647                 }
1648
1649                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1650                 nv50_audio_disable(encoder, nv_crtc);
1651                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1652                 nv50_outp_release(nv_encoder);
1653         }
1654 }
1655
1656 static void
1657 nv50_sor_enable(struct drm_encoder *encoder,
1658                 struct drm_atomic_state *state)
1659 {
1660         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1661         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1662         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1663         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1664         struct {
1665                 struct nv50_disp_mthd_v1 base;
1666                 struct nv50_disp_sor_lvds_script_v0 lvds;
1667         } lvds = {
1668                 .base.version = 1,
1669                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1670                 .base.hasht   = nv_encoder->dcb->hasht,
1671                 .base.hashm   = nv_encoder->dcb->hashm,
1672         };
1673         struct nv50_disp *disp = nv50_disp(encoder->dev);
1674         struct drm_device *dev = encoder->dev;
1675         struct nouveau_drm *drm = nouveau_drm(dev);
1676         struct nouveau_connector *nv_connector;
1677         struct nvbios *bios = &drm->vbios;
1678         bool hda = false;
1679         u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
1680         u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
1681
1682         nv_connector = nv50_outp_get_new_connector(nv_encoder, state);
1683         nv_encoder->crtc = encoder->crtc;
1684
1685         if ((disp->disp->object.oclass == GT214_DISP ||
1686              disp->disp->object.oclass >= GF110_DISP) &&
1687             drm_detect_monitor_audio(nv_connector->edid))
1688                 hda = true;
1689         nv50_outp_acquire(nv_encoder, hda);
1690
1691         switch (nv_encoder->dcb->type) {
1692         case DCB_OUTPUT_TMDS:
1693                 if (nv_encoder->link & 1) {
1694                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1695                         /* Only enable dual-link if:
1696                          *  - Need to (i.e. rate > 165MHz)
1697                          *  - DCB says we can
1698                          *  - Not an HDMI monitor, since there's no dual-link
1699                          *    on HDMI.
1700                          */
1701                         if (mode->clock >= 165000 &&
1702                             nv_encoder->dcb->duallink_possible &&
1703                             !drm_detect_hdmi_monitor(nv_connector->edid))
1704                                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1705                 } else {
1706                         proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1707                 }
1708
1709                 nv50_hdmi_enable(&nv_encoder->base.base, state, mode);
1710                 break;
1711         case DCB_OUTPUT_LVDS:
1712                 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1713
1714                 if (bios->fp_no_ddc) {
1715                         if (bios->fp.dual_link)
1716                                 lvds.lvds.script |= 0x0100;
1717                         if (bios->fp.if_is_24bit)
1718                                 lvds.lvds.script |= 0x0200;
1719                 } else {
1720                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1721                                 if (((u8 *)nv_connector->edid)[121] == 2)
1722                                         lvds.lvds.script |= 0x0100;
1723                         } else
1724                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1725                                 lvds.lvds.script |= 0x0100;
1726                         }
1727
1728                         if (lvds.lvds.script & 0x0100) {
1729                                 if (bios->fp.strapless_is_24bit & 2)
1730                                         lvds.lvds.script |= 0x0200;
1731                         } else {
1732                                 if (bios->fp.strapless_is_24bit & 1)
1733                                         lvds.lvds.script |= 0x0200;
1734                         }
1735
1736                         if (asyh->or.bpc == 8)
1737                                 lvds.lvds.script |= 0x0200;
1738                 }
1739
1740                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1741                 break;
1742         case DCB_OUTPUT_DP:
1743                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1744
1745                 if (nv_encoder->link & 1)
1746                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A;
1747                 else
1748                         proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
1749
1750                 nv50_audio_enable(encoder, state, mode);
1751                 break;
1752         default:
1753                 BUG();
1754                 break;
1755         }
1756
1757         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1758 }
1759
1760 static const struct drm_encoder_helper_funcs
1761 nv50_sor_help = {
1762         .atomic_check = nv50_outp_atomic_check,
1763         .atomic_enable = nv50_sor_enable,
1764         .atomic_disable = nv50_sor_disable,
1765 };
1766
1767 static void
1768 nv50_sor_destroy(struct drm_encoder *encoder)
1769 {
1770         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1771         nv50_mstm_del(&nv_encoder->dp.mstm);
1772         drm_encoder_cleanup(encoder);
1773         kfree(encoder);
1774 }
1775
1776 static const struct drm_encoder_funcs
1777 nv50_sor_func = {
1778         .destroy = nv50_sor_destroy,
1779 };
1780
1781 static bool nv50_has_mst(struct nouveau_drm *drm)
1782 {
1783         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1784         u32 data;
1785         u8 ver, hdr, cnt, len;
1786
1787         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1788         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1789 }
1790
1791 static int
1792 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1793 {
1794         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1795         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1796         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1797         struct nouveau_encoder *nv_encoder;
1798         struct drm_encoder *encoder;
1799         struct nv50_disp *disp = nv50_disp(connector->dev);
1800         int type, ret;
1801
1802         switch (dcbe->type) {
1803         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1804         case DCB_OUTPUT_TMDS:
1805         case DCB_OUTPUT_DP:
1806         default:
1807                 type = DRM_MODE_ENCODER_TMDS;
1808                 break;
1809         }
1810
1811         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1812         if (!nv_encoder)
1813                 return -ENOMEM;
1814         nv_encoder->dcb = dcbe;
1815         nv_encoder->update = nv50_sor_update;
1816
1817         encoder = to_drm_encoder(nv_encoder);
1818         encoder->possible_crtcs = dcbe->heads;
1819         encoder->possible_clones = 0;
1820         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1821                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1822         drm_encoder_helper_add(encoder, &nv50_sor_help);
1823
1824         drm_connector_attach_encoder(connector, encoder);
1825
1826         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1827
1828         if (dcbe->type == DCB_OUTPUT_DP) {
1829                 struct nvkm_i2c_aux *aux =
1830                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1831
1832                 if (aux) {
1833                         if (disp->disp->object.oclass < GF110_DISP) {
1834                                 /* HW has no support for address-only
1835                                  * transactions, so we're required to
1836                                  * use custom I2C-over-AUX code.
1837                                  */
1838                                 nv_encoder->i2c = &aux->i2c;
1839                         } else {
1840                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1841                         }
1842                         nv_encoder->aux = aux;
1843                 }
1844
1845                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1846                     nv50_has_mst(drm)) {
1847                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1848                                             16, nv_connector->base.base.id,
1849                                             &nv_encoder->dp.mstm);
1850                         if (ret)
1851                                 return ret;
1852                 }
1853         } else {
1854                 struct nvkm_i2c_bus *bus =
1855                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1856                 if (bus)
1857                         nv_encoder->i2c = &bus->i2c;
1858         }
1859
1860         return 0;
1861 }
1862
1863 /******************************************************************************
1864  * PIOR
1865  *****************************************************************************/
1866 static int
1867 nv50_pior_atomic_check(struct drm_encoder *encoder,
1868                        struct drm_crtc_state *crtc_state,
1869                        struct drm_connector_state *conn_state)
1870 {
1871         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1872         if (ret)
1873                 return ret;
1874         crtc_state->adjusted_mode.clock *= 2;
1875         return 0;
1876 }
1877
1878 static void
1879 nv50_pior_disable(struct drm_encoder *encoder)
1880 {
1881         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1882         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1883         const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE);
1884         if (nv_encoder->crtc)
1885                 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL);
1886         nv_encoder->crtc = NULL;
1887         nv50_outp_release(nv_encoder);
1888 }
1889
1890 static void
1891 nv50_pior_enable(struct drm_encoder *encoder)
1892 {
1893         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1894         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1895         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1896         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1897         u32 ctrl = 0;
1898
1899         switch (nv_crtc->index) {
1900         case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break;
1901         case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break;
1902         default:
1903                 WARN_ON(1);
1904                 break;
1905         }
1906
1907         nv50_outp_acquire(nv_encoder, false);
1908
1909         switch (asyh->or.bpc) {
1910         case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
1911         case  8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1912         case  6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1913         default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1914         }
1915
1916         switch (nv_encoder->dcb->type) {
1917         case DCB_OUTPUT_TMDS:
1918         case DCB_OUTPUT_DP:
1919                 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1920                 break;
1921         default:
1922                 BUG();
1923                 break;
1924         }
1925
1926         core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh);
1927         nv_encoder->crtc = encoder->crtc;
1928 }
1929
1930 static const struct drm_encoder_helper_funcs
1931 nv50_pior_help = {
1932         .atomic_check = nv50_pior_atomic_check,
1933         .enable = nv50_pior_enable,
1934         .disable = nv50_pior_disable,
1935 };
1936
1937 static void
1938 nv50_pior_destroy(struct drm_encoder *encoder)
1939 {
1940         drm_encoder_cleanup(encoder);
1941         kfree(encoder);
1942 }
1943
1944 static const struct drm_encoder_funcs
1945 nv50_pior_func = {
1946         .destroy = nv50_pior_destroy,
1947 };
1948
1949 static int
1950 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1951 {
1952         struct drm_device *dev = connector->dev;
1953         struct nouveau_drm *drm = nouveau_drm(dev);
1954         struct nv50_disp *disp = nv50_disp(dev);
1955         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1956         struct nvkm_i2c_bus *bus = NULL;
1957         struct nvkm_i2c_aux *aux = NULL;
1958         struct i2c_adapter *ddc;
1959         struct nouveau_encoder *nv_encoder;
1960         struct drm_encoder *encoder;
1961         int type;
1962
1963         switch (dcbe->type) {
1964         case DCB_OUTPUT_TMDS:
1965                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1966                 ddc  = bus ? &bus->i2c : NULL;
1967                 type = DRM_MODE_ENCODER_TMDS;
1968                 break;
1969         case DCB_OUTPUT_DP:
1970                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1971                 ddc  = aux ? &aux->i2c : NULL;
1972                 type = DRM_MODE_ENCODER_TMDS;
1973                 break;
1974         default:
1975                 return -ENODEV;
1976         }
1977
1978         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1979         if (!nv_encoder)
1980                 return -ENOMEM;
1981         nv_encoder->dcb = dcbe;
1982         nv_encoder->i2c = ddc;
1983         nv_encoder->aux = aux;
1984
1985         encoder = to_drm_encoder(nv_encoder);
1986         encoder->possible_crtcs = dcbe->heads;
1987         encoder->possible_clones = 0;
1988         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1989                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1990         drm_encoder_helper_add(encoder, &nv50_pior_help);
1991
1992         drm_connector_attach_encoder(connector, encoder);
1993
1994         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1995
1996         return 0;
1997 }
1998
1999 /******************************************************************************
2000  * Atomic
2001  *****************************************************************************/
2002
2003 static void
2004 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
2005 {
2006         struct nouveau_drm *drm = nouveau_drm(state->dev);
2007         struct nv50_disp *disp = nv50_disp(drm->dev);
2008         struct nv50_core *core = disp->core;
2009         struct nv50_mstm *mstm;
2010         struct drm_encoder *encoder;
2011
2012         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
2013
2014         drm_for_each_encoder(encoder, drm->dev) {
2015                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2016                         mstm = nouveau_encoder(encoder)->dp.mstm;
2017                         if (mstm && mstm->modified)
2018                                 nv50_mstm_prepare(mstm);
2019                 }
2020         }
2021
2022         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2023         core->func->update(core, interlock, true);
2024         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2025                                        disp->core->chan.base.device))
2026                 NV_ERROR(drm, "core notifier timeout\n");
2027
2028         drm_for_each_encoder(encoder, drm->dev) {
2029                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2030                         mstm = nouveau_encoder(encoder)->dp.mstm;
2031                         if (mstm && mstm->modified)
2032                                 nv50_mstm_cleanup(mstm);
2033                 }
2034         }
2035 }
2036
2037 static void
2038 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
2039 {
2040         struct drm_plane_state *new_plane_state;
2041         struct drm_plane *plane;
2042         int i;
2043
2044         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2045                 struct nv50_wndw *wndw = nv50_wndw(plane);
2046                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2047                         if (wndw->func->update)
2048                                 wndw->func->update(wndw, interlock);
2049                 }
2050         }
2051 }
2052
2053 static void
2054 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
2055 {
2056         struct drm_device *dev = state->dev;
2057         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
2058         struct drm_crtc *crtc;
2059         struct drm_plane_state *new_plane_state;
2060         struct drm_plane *plane;
2061         struct nouveau_drm *drm = nouveau_drm(dev);
2062         struct nv50_disp *disp = nv50_disp(dev);
2063         struct nv50_atom *atom = nv50_atom(state);
2064         struct nv50_core *core = disp->core;
2065         struct nv50_outp_atom *outp, *outt;
2066         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
2067         int i;
2068         bool flushed = false;
2069
2070         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2071         nv50_crc_atomic_stop_reporting(state);
2072         drm_atomic_helper_wait_for_fences(dev, state, false);
2073         drm_atomic_helper_wait_for_dependencies(state);
2074         drm_atomic_helper_update_legacy_modeset_state(dev, state);
2075
2076         if (atom->lock_core)
2077                 mutex_lock(&disp->mutex);
2078
2079         /* Disable head(s). */
2080         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2081                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2082                 struct nv50_head *head = nv50_head(crtc);
2083
2084                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2085                           asyh->clr.mask, asyh->set.mask);
2086
2087                 if (old_crtc_state->active && !new_crtc_state->active) {
2088                         pm_runtime_put_noidle(dev->dev);
2089                         drm_crtc_vblank_off(crtc);
2090                 }
2091
2092                 if (asyh->clr.mask) {
2093                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
2094                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2095                 }
2096         }
2097
2098         /* Disable plane(s). */
2099         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2100                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2101                 struct nv50_wndw *wndw = nv50_wndw(plane);
2102
2103                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2104                           asyw->clr.mask, asyw->set.mask);
2105                 if (!asyw->clr.mask)
2106                         continue;
2107
2108                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2109         }
2110
2111         /* Disable output path(s). */
2112         list_for_each_entry(outp, &atom->outp, head) {
2113                 const struct drm_encoder_helper_funcs *help;
2114                 struct drm_encoder *encoder;
2115
2116                 encoder = outp->encoder;
2117                 help = encoder->helper_private;
2118
2119                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2120                           outp->clr.mask, outp->set.mask);
2121
2122                 if (outp->clr.mask) {
2123                         help->atomic_disable(encoder, state);
2124                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
2125                         if (outp->flush_disable) {
2126                                 nv50_disp_atomic_commit_wndw(state, interlock);
2127                                 nv50_disp_atomic_commit_core(state, interlock);
2128                                 memset(interlock, 0x00, sizeof(interlock));
2129
2130                                 flushed = true;
2131                         }
2132                 }
2133         }
2134
2135         /* Flush disable. */
2136         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2137                 if (atom->flush_disable) {
2138                         nv50_disp_atomic_commit_wndw(state, interlock);
2139                         nv50_disp_atomic_commit_core(state, interlock);
2140                         memset(interlock, 0x00, sizeof(interlock));
2141
2142                         flushed = true;
2143                 }
2144         }
2145
2146         if (flushed)
2147                 nv50_crc_atomic_release_notifier_contexts(state);
2148         nv50_crc_atomic_init_notifier_contexts(state);
2149
2150         /* Update output path(s). */
2151         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2152                 const struct drm_encoder_helper_funcs *help;
2153                 struct drm_encoder *encoder;
2154
2155                 encoder = outp->encoder;
2156                 help = encoder->helper_private;
2157
2158                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2159                           outp->set.mask, outp->clr.mask);
2160
2161                 if (outp->set.mask) {
2162                         help->atomic_enable(encoder, state);
2163                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2164                 }
2165
2166                 list_del(&outp->head);
2167                 kfree(outp);
2168         }
2169
2170         /* Update head(s). */
2171         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2172                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2173                 struct nv50_head *head = nv50_head(crtc);
2174
2175                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2176                           asyh->set.mask, asyh->clr.mask);
2177
2178                 if (asyh->set.mask) {
2179                         nv50_head_flush_set(head, asyh);
2180                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2181                 }
2182
2183                 if (new_crtc_state->active) {
2184                         if (!old_crtc_state->active) {
2185                                 drm_crtc_vblank_on(crtc);
2186                                 pm_runtime_get_noresume(dev->dev);
2187                         }
2188                         if (new_crtc_state->event)
2189                                 drm_crtc_vblank_get(crtc);
2190                 }
2191         }
2192
2193         /* Update window->head assignment.
2194          *
2195          * This has to happen in an update that's not interlocked with
2196          * any window channels to avoid hitting HW error checks.
2197          *
2198          *TODO: Proper handling of window ownership (Turing apparently
2199          *      supports non-fixed mappings).
2200          */
2201         if (core->assign_windows) {
2202                 core->func->wndw.owner(core);
2203                 nv50_disp_atomic_commit_core(state, interlock);
2204                 core->assign_windows = false;
2205                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2206         }
2207
2208         /* Update plane(s). */
2209         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2210                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2211                 struct nv50_wndw *wndw = nv50_wndw(plane);
2212
2213                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2214                           asyw->set.mask, asyw->clr.mask);
2215                 if ( !asyw->set.mask &&
2216                     (!asyw->clr.mask || atom->flush_disable))
2217                         continue;
2218
2219                 nv50_wndw_flush_set(wndw, interlock, asyw);
2220         }
2221
2222         /* Flush update. */
2223         nv50_disp_atomic_commit_wndw(state, interlock);
2224
2225         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2226                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2227                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2228                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2229                     !atom->state.legacy_cursor_update)
2230                         nv50_disp_atomic_commit_core(state, interlock);
2231                 else
2232                         disp->core->func->update(disp->core, interlock, false);
2233         }
2234
2235         if (atom->lock_core)
2236                 mutex_unlock(&disp->mutex);
2237
2238         /* Wait for HW to signal completion. */
2239         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2240                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2241                 struct nv50_wndw *wndw = nv50_wndw(plane);
2242                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2243                 if (ret)
2244                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2245         }
2246
2247         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2248                 if (new_crtc_state->event) {
2249                         unsigned long flags;
2250                         /* Get correct count/ts if racing with vblank irq */
2251                         if (new_crtc_state->active)
2252                                 drm_crtc_accurate_vblank_count(crtc);
2253                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2254                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2255                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2256
2257                         new_crtc_state->event = NULL;
2258                         if (new_crtc_state->active)
2259                                 drm_crtc_vblank_put(crtc);
2260                 }
2261         }
2262
2263         nv50_crc_atomic_start_reporting(state);
2264         if (!flushed)
2265                 nv50_crc_atomic_release_notifier_contexts(state);
2266         drm_atomic_helper_commit_hw_done(state);
2267         drm_atomic_helper_cleanup_planes(dev, state);
2268         drm_atomic_helper_commit_cleanup_done(state);
2269         drm_atomic_state_put(state);
2270
2271         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2272         pm_runtime_mark_last_busy(dev->dev);
2273         pm_runtime_put_autosuspend(dev->dev);
2274 }
2275
2276 static void
2277 nv50_disp_atomic_commit_work(struct work_struct *work)
2278 {
2279         struct drm_atomic_state *state =
2280                 container_of(work, typeof(*state), commit_work);
2281         nv50_disp_atomic_commit_tail(state);
2282 }
2283
2284 static int
2285 nv50_disp_atomic_commit(struct drm_device *dev,
2286                         struct drm_atomic_state *state, bool nonblock)
2287 {
2288         struct drm_plane_state *new_plane_state;
2289         struct drm_plane *plane;
2290         int ret, i;
2291
2292         ret = pm_runtime_get_sync(dev->dev);
2293         if (ret < 0 && ret != -EACCES) {
2294                 pm_runtime_put_autosuspend(dev->dev);
2295                 return ret;
2296         }
2297
2298         ret = drm_atomic_helper_setup_commit(state, nonblock);
2299         if (ret)
2300                 goto done;
2301
2302         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2303
2304         ret = drm_atomic_helper_prepare_planes(dev, state);
2305         if (ret)
2306                 goto done;
2307
2308         if (!nonblock) {
2309                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2310                 if (ret)
2311                         goto err_cleanup;
2312         }
2313
2314         ret = drm_atomic_helper_swap_state(state, true);
2315         if (ret)
2316                 goto err_cleanup;
2317
2318         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2319                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2320                 struct nv50_wndw *wndw = nv50_wndw(plane);
2321
2322                 if (asyw->set.image)
2323                         nv50_wndw_ntfy_enable(wndw, asyw);
2324         }
2325
2326         drm_atomic_state_get(state);
2327
2328         /*
2329          * Grab another RPM ref for the commit tail, which will release the
2330          * ref when it's finished
2331          */
2332         pm_runtime_get_noresume(dev->dev);
2333
2334         if (nonblock)
2335                 queue_work(system_unbound_wq, &state->commit_work);
2336         else
2337                 nv50_disp_atomic_commit_tail(state);
2338
2339 err_cleanup:
2340         if (ret)
2341                 drm_atomic_helper_cleanup_planes(dev, state);
2342 done:
2343         pm_runtime_put_autosuspend(dev->dev);
2344         return ret;
2345 }
2346
2347 static struct nv50_outp_atom *
2348 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2349 {
2350         struct nv50_outp_atom *outp;
2351
2352         list_for_each_entry(outp, &atom->outp, head) {
2353                 if (outp->encoder == encoder)
2354                         return outp;
2355         }
2356
2357         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2358         if (!outp)
2359                 return ERR_PTR(-ENOMEM);
2360
2361         list_add(&outp->head, &atom->outp);
2362         outp->encoder = encoder;
2363         return outp;
2364 }
2365
2366 static int
2367 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2368                                 struct drm_connector_state *old_connector_state)
2369 {
2370         struct drm_encoder *encoder = old_connector_state->best_encoder;
2371         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2372         struct drm_crtc *crtc;
2373         struct nv50_outp_atom *outp;
2374
2375         if (!(crtc = old_connector_state->crtc))
2376                 return 0;
2377
2378         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2379         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2380         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2381                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2382                 if (IS_ERR(outp))
2383                         return PTR_ERR(outp);
2384
2385                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2386                         outp->flush_disable = true;
2387                         atom->flush_disable = true;
2388                 }
2389                 outp->clr.ctrl = true;
2390                 atom->lock_core = true;
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int
2397 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2398                                 struct drm_connector_state *connector_state)
2399 {
2400         struct drm_encoder *encoder = connector_state->best_encoder;
2401         struct drm_crtc_state *new_crtc_state;
2402         struct drm_crtc *crtc;
2403         struct nv50_outp_atom *outp;
2404
2405         if (!(crtc = connector_state->crtc))
2406                 return 0;
2407
2408         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2409         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2410                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2411                 if (IS_ERR(outp))
2412                         return PTR_ERR(outp);
2413
2414                 outp->set.ctrl = true;
2415                 atom->lock_core = true;
2416         }
2417
2418         return 0;
2419 }
2420
2421 static int
2422 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2423 {
2424         struct nv50_atom *atom = nv50_atom(state);
2425         struct nv50_core *core = nv50_disp(dev)->core;
2426         struct drm_connector_state *old_connector_state, *new_connector_state;
2427         struct drm_connector *connector;
2428         struct drm_crtc_state *new_crtc_state;
2429         struct drm_crtc *crtc;
2430         struct nv50_head *head;
2431         struct nv50_head_atom *asyh;
2432         int ret, i;
2433
2434         if (core->assign_windows && core->func->head->static_wndw_map) {
2435                 drm_for_each_crtc(crtc, dev) {
2436                         new_crtc_state = drm_atomic_get_crtc_state(state,
2437                                                                    crtc);
2438                         if (IS_ERR(new_crtc_state))
2439                                 return PTR_ERR(new_crtc_state);
2440
2441                         head = nv50_head(crtc);
2442                         asyh = nv50_head_atom(new_crtc_state);
2443                         core->func->head->static_wndw_map(head, asyh);
2444                 }
2445         }
2446
2447         /* We need to handle colour management on a per-plane basis. */
2448         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2449                 if (new_crtc_state->color_mgmt_changed) {
2450                         ret = drm_atomic_add_affected_planes(state, crtc);
2451                         if (ret)
2452                                 return ret;
2453                 }
2454         }
2455
2456         ret = drm_atomic_helper_check(dev, state);
2457         if (ret)
2458                 return ret;
2459
2460         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2461                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2462                 if (ret)
2463                         return ret;
2464
2465                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2466                 if (ret)
2467                         return ret;
2468         }
2469
2470         ret = drm_dp_mst_atomic_check(state);
2471         if (ret)
2472                 return ret;
2473
2474         nv50_crc_atomic_check_outp(atom);
2475
2476         return 0;
2477 }
2478
2479 static void
2480 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2481 {
2482         struct nv50_atom *atom = nv50_atom(state);
2483         struct nv50_outp_atom *outp, *outt;
2484
2485         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2486                 list_del(&outp->head);
2487                 kfree(outp);
2488         }
2489
2490         drm_atomic_state_default_clear(state);
2491 }
2492
2493 static void
2494 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2495 {
2496         struct nv50_atom *atom = nv50_atom(state);
2497         drm_atomic_state_default_release(&atom->state);
2498         kfree(atom);
2499 }
2500
2501 static struct drm_atomic_state *
2502 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2503 {
2504         struct nv50_atom *atom;
2505         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2506             drm_atomic_state_init(dev, &atom->state) < 0) {
2507                 kfree(atom);
2508                 return NULL;
2509         }
2510         INIT_LIST_HEAD(&atom->outp);
2511         return &atom->state;
2512 }
2513
2514 static const struct drm_mode_config_funcs
2515 nv50_disp_func = {
2516         .fb_create = nouveau_user_framebuffer_create,
2517         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2518         .atomic_check = nv50_disp_atomic_check,
2519         .atomic_commit = nv50_disp_atomic_commit,
2520         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2521         .atomic_state_clear = nv50_disp_atomic_state_clear,
2522         .atomic_state_free = nv50_disp_atomic_state_free,
2523 };
2524
2525 /******************************************************************************
2526  * Init
2527  *****************************************************************************/
2528
2529 static void
2530 nv50_display_fini(struct drm_device *dev, bool suspend)
2531 {
2532         struct nouveau_encoder *nv_encoder;
2533         struct drm_encoder *encoder;
2534         struct drm_plane *plane;
2535
2536         drm_for_each_plane(plane, dev) {
2537                 struct nv50_wndw *wndw = nv50_wndw(plane);
2538                 if (plane->funcs != &nv50_wndw)
2539                         continue;
2540                 nv50_wndw_fini(wndw);
2541         }
2542
2543         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2544                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2545                         nv_encoder = nouveau_encoder(encoder);
2546                         nv50_mstm_fini(nv_encoder->dp.mstm);
2547                 }
2548         }
2549 }
2550
2551 static int
2552 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2553 {
2554         struct nv50_core *core = nv50_disp(dev)->core;
2555         struct drm_encoder *encoder;
2556         struct drm_plane *plane;
2557
2558         if (resume || runtime)
2559                 core->func->init(core);
2560
2561         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2562                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2563                         struct nouveau_encoder *nv_encoder =
2564                                 nouveau_encoder(encoder);
2565                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2566                 }
2567         }
2568
2569         drm_for_each_plane(plane, dev) {
2570                 struct nv50_wndw *wndw = nv50_wndw(plane);
2571                 if (plane->funcs != &nv50_wndw)
2572                         continue;
2573                 nv50_wndw_init(wndw);
2574         }
2575
2576         return 0;
2577 }
2578
2579 static void
2580 nv50_display_destroy(struct drm_device *dev)
2581 {
2582         struct nv50_disp *disp = nv50_disp(dev);
2583
2584         nv50_audio_component_fini(nouveau_drm(dev));
2585
2586         nvif_object_unmap(&disp->caps);
2587         nvif_object_dtor(&disp->caps);
2588         nv50_core_del(&disp->core);
2589
2590         nouveau_bo_unmap(disp->sync);
2591         if (disp->sync)
2592                 nouveau_bo_unpin(disp->sync);
2593         nouveau_bo_ref(NULL, &disp->sync);
2594
2595         nouveau_display(dev)->priv = NULL;
2596         kfree(disp);
2597 }
2598
2599 int
2600 nv50_display_create(struct drm_device *dev)
2601 {
2602         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2603         struct nouveau_drm *drm = nouveau_drm(dev);
2604         struct dcb_table *dcb = &drm->vbios.dcb;
2605         struct drm_connector *connector, *tmp;
2606         struct nv50_disp *disp;
2607         struct dcb_output *dcbe;
2608         int crtcs, ret, i;
2609         bool has_mst = nv50_has_mst(drm);
2610
2611         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2612         if (!disp)
2613                 return -ENOMEM;
2614
2615         mutex_init(&disp->mutex);
2616
2617         nouveau_display(dev)->priv = disp;
2618         nouveau_display(dev)->dtor = nv50_display_destroy;
2619         nouveau_display(dev)->init = nv50_display_init;
2620         nouveau_display(dev)->fini = nv50_display_fini;
2621         disp->disp = &nouveau_display(dev)->disp;
2622         dev->mode_config.funcs = &nv50_disp_func;
2623         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2624         dev->mode_config.normalize_zpos = true;
2625
2626         /* small shared memory area we use for notifiers and semaphores */
2627         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2628                              0, 0x0000, NULL, NULL, &disp->sync);
2629         if (!ret) {
2630                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2631                 if (!ret) {
2632                         ret = nouveau_bo_map(disp->sync);
2633                         if (ret)
2634                                 nouveau_bo_unpin(disp->sync);
2635                 }
2636                 if (ret)
2637                         nouveau_bo_ref(NULL, &disp->sync);
2638         }
2639
2640         if (ret)
2641                 goto out;
2642
2643         /* allocate master evo channel */
2644         ret = nv50_core_new(drm, &disp->core);
2645         if (ret)
2646                 goto out;
2647
2648         disp->core->func->init(disp->core);
2649         if (disp->core->func->caps_init) {
2650                 ret = disp->core->func->caps_init(drm, disp);
2651                 if (ret)
2652                         goto out;
2653         }
2654
2655         /* Assign the correct format modifiers */
2656         if (disp->disp->object.oclass >= TU102_DISP)
2657                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2658         else
2659         if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2660                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2661         else
2662                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2663
2664         /* create crtc objects to represent the hw heads */
2665         if (disp->disp->object.oclass >= GV100_DISP)
2666                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2667         else
2668         if (disp->disp->object.oclass >= GF110_DISP)
2669                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2670         else
2671                 crtcs = 0x3;
2672
2673         for (i = 0; i < fls(crtcs); i++) {
2674                 struct nv50_head *head;
2675
2676                 if (!(crtcs & (1 << i)))
2677                         continue;
2678
2679                 head = nv50_head_create(dev, i);
2680                 if (IS_ERR(head)) {
2681                         ret = PTR_ERR(head);
2682                         goto out;
2683                 }
2684
2685                 if (has_mst) {
2686                         head->msto = nv50_msto_new(dev, head, i);
2687                         if (IS_ERR(head->msto)) {
2688                                 ret = PTR_ERR(head->msto);
2689                                 head->msto = NULL;
2690                                 goto out;
2691                         }
2692
2693                         /*
2694                          * FIXME: This is a hack to workaround the following
2695                          * issues:
2696                          *
2697                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2698                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2699                          *
2700                          * Once these issues are closed, this should be
2701                          * removed
2702                          */
2703                         head->msto->encoder.possible_crtcs = crtcs;
2704                 }
2705         }
2706
2707         /* create encoder/connector objects based on VBIOS DCB table */
2708         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2709                 connector = nouveau_connector_create(dev, dcbe);
2710                 if (IS_ERR(connector))
2711                         continue;
2712
2713                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2714                         switch (dcbe->type) {
2715                         case DCB_OUTPUT_TMDS:
2716                         case DCB_OUTPUT_LVDS:
2717                         case DCB_OUTPUT_DP:
2718                                 ret = nv50_sor_create(connector, dcbe);
2719                                 break;
2720                         case DCB_OUTPUT_ANALOG:
2721                                 ret = nv50_dac_create(connector, dcbe);
2722                                 break;
2723                         default:
2724                                 ret = -ENODEV;
2725                                 break;
2726                         }
2727                 } else {
2728                         ret = nv50_pior_create(connector, dcbe);
2729                 }
2730
2731                 if (ret) {
2732                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2733                                      dcbe->location, dcbe->type,
2734                                      ffs(dcbe->or) - 1, ret);
2735                         ret = 0;
2736                 }
2737         }
2738
2739         /* cull any connectors we created that don't have an encoder */
2740         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2741                 if (connector->possible_encoders)
2742                         continue;
2743
2744                 NV_WARN(drm, "%s has no encoders, removing\n",
2745                         connector->name);
2746                 connector->funcs->destroy(connector);
2747         }
2748
2749         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2750         dev->vblank_disable_immediate = true;
2751
2752         nv50_audio_component_init(drm);
2753
2754 out:
2755         if (ret)
2756                 nv50_display_destroy(dev);
2757         return ret;
2758 }
2759
2760 /******************************************************************************
2761  * Format modifiers
2762  *****************************************************************************/
2763
2764 /****************************************************************
2765  *            Log2(block height) ----------------------------+  *
2766  *            Page Kind ----------------------------------+  |  *
2767  *            Gob Height/Page Kind Generation ------+     |  |  *
2768  *                          Sector layout -------+  |     |  |  *
2769  *                          Compression ------+  |  |     |  |  */
2770 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2771         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2772         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2773         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2774         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2775         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2776         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2777         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2778         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2779         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2780         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2781         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2782         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2783         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2784         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2785         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2786         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2787         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2788         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2789         DRM_FORMAT_MOD_LINEAR,
2790         DRM_FORMAT_MOD_INVALID
2791 };
2792
2793 /****************************************************************
2794  *            Log2(block height) ----------------------------+  *
2795  *            Page Kind ----------------------------------+  |  *
2796  *            Gob Height/Page Kind Generation ------+     |  |  *
2797  *                          Sector layout -------+  |     |  |  *
2798  *                          Compression ------+  |  |     |  |  */
2799 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2800         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2801         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2802         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2803         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2804         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2805         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2806         DRM_FORMAT_MOD_LINEAR,
2807         DRM_FORMAT_MOD_INVALID
2808 };