drivers/gpu/drm/nouveau/dispnv50/disp.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "disp.h"
  25 #include "atom.h"
  26 #include "core.h"
  27 #include "head.h"
  28 #include "wndw.h"
  29
  30 #include <linux/dma-mapping.h>
  31 #include <linux/hdmi.h>
  32 #include <linux/component.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_dp_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_plane_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_scdc_helper.h>
  41 #include <drm/drm_vblank.h>
  42
  43 #include <nvif/class.h>
  44 #include <nvif/cl0002.h>
  45 #include <nvif/cl5070.h>
  46 #include <nvif/cl507d.h>
  47 #include <nvif/event.h>
  48 #include <nvif/timer.h>
  49
  50 #include "nouveau_drv.h"
  51 #include "nouveau_dma.h"
  52 #include "nouveau_gem.h"
  53 #include "nouveau_connector.h"
  54 #include "nouveau_encoder.h"
  55 #include "nouveau_fence.h"
  56 #include "nouveau_fbcon.h"
  57
  58 #include <subdev/bios/dp.h>
  59
  60 /******************************************************************************
  61  * EVO channel
  62  *****************************************************************************/
  63
  64 static int
  65 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  66                  const s32 *oclass, u8 head, void *data, u32 size,
  67                  struct nv50_chan *chan)
  68 {
  69         struct nvif_sclass *sclass;
  70         int ret, i, n;
  71
  72         chan->device = device;
  73
  74         ret = n = nvif_object_sclass_get(disp, &sclass);
  75         if (ret < 0)
  76                 return ret;
  77
  78         while (oclass[0]) {
  79                 for (i = 0; i < n; i++) {
  80                         if (sclass[i].oclass == oclass[0]) {
  81                                 ret = nvif_object_init(disp, 0, oclass[0],
  82                                                        data, size, &chan->user);
  83                                 if (ret == 0)
  84                                         nvif_object_map(&chan->user, NULL, 0);
  85                                 nvif_object_sclass_put(&sclass);
  86                                 return ret;
  87                         }
  88                 }
  89                 oclass++;
  90         }
  91
  92         nvif_object_sclass_put(&sclass);
  93         return -ENOSYS;
  94 }
  95
  96 static void
  97 nv50_chan_destroy(struct nv50_chan *chan)
  98 {
  99         nvif_object_fini(&chan->user);
 100 }
 101
 102 /******************************************************************************
 103  * DMA EVO channel
 104  *****************************************************************************/
 105
 106 void
 107 nv50_dmac_destroy(struct nv50_dmac *dmac)
 108 {
 109         nvif_object_fini(&dmac->vram);
 110         nvif_object_fini(&dmac->sync);
 111
 112         nv50_chan_destroy(&dmac->base);
 113
 114         nvif_mem_fini(&dmac->push);
 115 }
 116
 117 int
 118 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 119                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 120                  struct nv50_dmac *dmac)
 121 {
 122         struct nouveau_cli *cli = (void *)device->object.client;
 123         struct nv50_disp_core_channel_dma_v0 *args = data;
 124         u8 type = NVIF_MEM_COHERENT;
 125         int ret;
 126
 127         mutex_init(&dmac->lock);
 128
 129         /* Pascal added support for 47-bit physical addresses, but some
 130          * parts of EVO still only accept 40-bit PAs.
 131          *
 132          * To avoid issues on systems with large amounts of RAM, and on
 133          * systems where an IOMMU maps pages at a high address, we need
 134          * to allocate push buffers in VRAM instead.
 135          *
 136          * This appears to match NVIDIA's behaviour on Pascal.
 137          */
 138         if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
 139                 type |= NVIF_MEM_VRAM;
 140
 141         ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
 142         if (ret)
 143                 return ret;
 144
 145         dmac->ptr = dmac->push.object.map.ptr;
 146
 147         args->pushbuf = nvif_handle(&dmac->push.object);
 148
 149         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 150                                &dmac->base);
 151         if (ret)
 152                 return ret;
 153
 154         if (!syncbuf)
 155                 return 0;
 156
 157         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 158                                &(struct nv_dma_v0) {
 159                                         .target = NV_DMA_V0_TARGET_VRAM,
 160                                         .access = NV_DMA_V0_ACCESS_RDWR,
 161                                         .start = syncbuf + 0x0000,
 162                                         .limit = syncbuf + 0x0fff,
 163                                }, sizeof(struct nv_dma_v0),
 164                                &dmac->sync);
 165         if (ret)
 166                 return ret;
 167
 168         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 169                                &(struct nv_dma_v0) {
 170                                         .target = NV_DMA_V0_TARGET_VRAM,
 171                                         .access = NV_DMA_V0_ACCESS_RDWR,
 172                                         .start = 0,
 173                                         .limit = device->info.ram_user - 1,
 174                                }, sizeof(struct nv_dma_v0),
 175                                &dmac->vram);
 176         if (ret)
 177                 return ret;
 178
 179         return ret;
 180 }
 181
 182 /******************************************************************************
 183  * EVO channel helpers
 184  *****************************************************************************/
 185 static void
 186 evo_flush(struct nv50_dmac *dmac)
 187 {
 188         /* Push buffer fetches are not coherent with BAR1, we need to ensure
 189          * writes have been flushed right through to VRAM before writing PUT.
 190          */
 191         if (dmac->push.type & NVIF_MEM_VRAM) {
 192                 struct nvif_device *device = dmac->base.device;
 193                 nvif_wr32(&device->object, 0x070000, 0x00000001);
 194                 nvif_msec(device, 2000,
 195                         if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
 196                                 break;
 197                 );
 198         }
 199 }
 200
 201 u32 *
 202 evo_wait(struct nv50_dmac *evoc, int nr)
 203 {
 204         struct nv50_dmac *dmac = evoc;
 205         struct nvif_device *device = dmac->base.device;
 206         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 207
 208         mutex_lock(&dmac->lock);
 209         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 210                 dmac->ptr[put] = 0x20000000;
 211                 evo_flush(dmac);
 212
 213                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 214                 if (nvif_msec(device, 2000,
 215                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 216                                 break;
 217                 ) < 0) {
 218                         mutex_unlock(&dmac->lock);
 219                         pr_err("nouveau: evo channel stalled\n");
 220                         return NULL;
 221                 }
 222
 223                 put = 0;
 224         }
 225
 226         return dmac->ptr + put;
 227 }
 228
 229 void
 230 evo_kick(u32 *push, struct nv50_dmac *evoc)
 231 {
 232         struct nv50_dmac *dmac = evoc;
 233
 234         evo_flush(dmac);
 235
 236         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 237         mutex_unlock(&dmac->lock);
 238 }
 239
 240 /******************************************************************************
 241  * Output path helpers
 242  *****************************************************************************/
 243 static void
 244 nv50_outp_release(struct nouveau_encoder *nv_encoder)
 245 {
 246         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
 247         struct {
 248                 struct nv50_disp_mthd_v1 base;
 249         } args = {
 250                 .base.version = 1,
 251                 .base.method = NV50_DISP_MTHD_V1_RELEASE,
 252                 .base.hasht  = nv_encoder->dcb->hasht,
 253                 .base.hashm  = nv_encoder->dcb->hashm,
 254         };
 255
 256         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 257         nv_encoder->or = -1;
 258         nv_encoder->link = 0;
 259 }
 260
 261 static int
 262 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda)
 263 {
 264         struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
 265         struct nv50_disp *disp = nv50_disp(drm->dev);
 266         struct {
 267                 struct nv50_disp_mthd_v1 base;
 268                 struct nv50_disp_acquire_v0 info;
 269         } args = {
 270                 .base.version = 1,
 271                 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
 272                 .base.hasht  = nv_encoder->dcb->hasht,
 273                 .base.hashm  = nv_encoder->dcb->hashm,
 274                 .info.hda = hda,
 275         };
 276         int ret;
 277
 278         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 279         if (ret) {
 280                 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
 281                 return ret;
 282         }
 283
 284         nv_encoder->or = args.info.or;
 285         nv_encoder->link = args.info.link;
 286         return 0;
 287 }
 288
 289 static int
 290 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 291                             struct drm_crtc_state *crtc_state,
 292                             struct drm_connector_state *conn_state,
 293                             struct drm_display_mode *native_mode)
 294 {
 295         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 296         struct drm_display_mode *mode = &crtc_state->mode;
 297         struct drm_connector *connector = conn_state->connector;
 298         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
 299         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 300
 301         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
 302         asyc->scaler.full = false;
 303         if (!native_mode)
 304                 return 0;
 305
 306         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
 307                 switch (connector->connector_type) {
 308                 case DRM_MODE_CONNECTOR_LVDS:
 309                 case DRM_MODE_CONNECTOR_eDP:
 310                         /* Don't force scaler for EDID modes with
 311                          * same size as the native one (e.g. different
 312                          * refresh rate)
 313                          */
 314                         if (mode->hdisplay == native_mode->hdisplay &&
 315                             mode->vdisplay == native_mode->vdisplay &&
 316                             mode->type & DRM_MODE_TYPE_DRIVER)
 317                                 break;
 318                         mode = native_mode;
 319                         asyc->scaler.full = true;
 320                         break;
 321                 default:
 322                         break;
 323                 }
 324         } else {
 325                 mode = native_mode;
 326         }
 327
 328         if (!drm_mode_equal(adjusted_mode, mode)) {
 329                 drm_mode_copy(adjusted_mode, mode);
 330                 crtc_state->mode_changed = true;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int
 337 nv50_outp_atomic_check(struct drm_encoder *encoder,
 338                        struct drm_crtc_state *crtc_state,
 339                        struct drm_connector_state *conn_state)
 340 {
 341         struct drm_connector *connector = conn_state->connector;
 342         struct nouveau_connector *nv_connector = nouveau_connector(connector);
 343         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 344         int ret;
 345
 346         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 347                                           nv_connector->native_mode);
 348         if (ret)
 349                 return ret;
 350
 351         if (crtc_state->mode_changed || crtc_state->connectors_changed)
 352                 asyh->or.bpc = connector->display_info.bpc;
 353
 354         return 0;
 355 }
 356
 357 /******************************************************************************
 358  * DAC
 359  *****************************************************************************/
 360 static void
 361 nv50_dac_disable(struct drm_encoder *encoder)
 362 {
 363         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 364         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 365         if (nv_encoder->crtc)
 366                 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
 367         nv_encoder->crtc = NULL;
 368         nv50_outp_release(nv_encoder);
 369 }
 370
 371 static void
 372 nv50_dac_enable(struct drm_encoder *encoder)
 373 {
 374         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 375         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 376         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
 377         struct nv50_core *core = nv50_disp(encoder->dev)->core;
 378
 379         nv50_outp_acquire(nv_encoder, false);
 380
 381         core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
 382         asyh->or.depth = 0;
 383
 384         nv_encoder->crtc = encoder->crtc;
 385 }
 386
 387 static enum drm_connector_status
 388 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 389 {
 390         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 391         struct nv50_disp *disp = nv50_disp(encoder->dev);
 392         struct {
 393                 struct nv50_disp_mthd_v1 base;
 394                 struct nv50_disp_dac_load_v0 load;
 395         } args = {
 396                 .base.version = 1,
 397                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
 398                 .base.hasht  = nv_encoder->dcb->hasht,
 399                 .base.hashm  = nv_encoder->dcb->hashm,
 400         };
 401         int ret;
 402
 403         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
 404         if (args.load.data == 0)
 405                 args.load.data = 340;
 406
 407         ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 408         if (ret || !args.load.load)
 409                 return connector_status_disconnected;
 410
 411         return connector_status_connected;
 412 }
 413
 414 static const struct drm_encoder_helper_funcs
 415 nv50_dac_help = {
 416         .atomic_check = nv50_outp_atomic_check,
 417         .enable = nv50_dac_enable,
 418         .disable = nv50_dac_disable,
 419         .detect = nv50_dac_detect
 420 };
 421
 422 static void
 423 nv50_dac_destroy(struct drm_encoder *encoder)
 424 {
 425         drm_encoder_cleanup(encoder);
 426         kfree(encoder);
 427 }
 428
 429 static const struct drm_encoder_funcs
 430 nv50_dac_func = {
 431         .destroy = nv50_dac_destroy,
 432 };
 433
 434 static int
 435 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
 436 {
 437         struct nouveau_drm *drm = nouveau_drm(connector->dev);
 438         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
 439         struct nvkm_i2c_bus *bus;
 440         struct nouveau_encoder *nv_encoder;
 441         struct drm_encoder *encoder;
 442         int type = DRM_MODE_ENCODER_DAC;
 443
 444         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 445         if (!nv_encoder)
 446                 return -ENOMEM;
 447         nv_encoder->dcb = dcbe;
 448
 449         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
 450         if (bus)
 451                 nv_encoder->i2c = &bus->i2c;
 452
 453         encoder = to_drm_encoder(nv_encoder);
 454         encoder->possible_crtcs = dcbe->heads;
 455         encoder->possible_clones = 0;
 456         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
 457                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
 458         drm_encoder_helper_add(encoder, &nv50_dac_help);
 459
 460         drm_connector_attach_encoder(connector, encoder);
 461         return 0;
 462 }
 463
 464 /*
 465  * audio component binding for ELD notification
 466  */
 467 static void
 468 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
 469                                 int dev_id)
 470 {
 471         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
 472                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 473                                                  port, dev_id);
 474 }
 475
 476 static int
 477 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
 478                              bool *enabled, unsigned char *buf, int max_bytes)
 479 {
 480         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 481         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 482         struct drm_encoder *encoder;
 483         struct nouveau_encoder *nv_encoder;
 484         struct nouveau_connector *nv_connector;
 485         struct nouveau_crtc *nv_crtc;
 486         int ret = 0;
 487
 488         *enabled = false;
 489         drm_for_each_encoder(encoder, drm->dev) {
 490                 nv_encoder = nouveau_encoder(encoder);
 491                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 492                 nv_crtc = nouveau_crtc(encoder->crtc);
 493                 if (!nv_connector || !nv_crtc || nv_encoder->or != port ||
 494                     nv_crtc->index != dev_id)
 495                         continue;
 496                 *enabled = nv_encoder->audio;
 497                 if (*enabled) {
 498                         ret = drm_eld_size(nv_connector->base.eld);
 499                         memcpy(buf, nv_connector->base.eld,
 500                                min(max_bytes, ret));
 501                 }
 502                 break;
 503         }
 504         return ret;
 505 }
 506
 507 static const struct drm_audio_component_ops nv50_audio_component_ops = {
 508         .get_eld = nv50_audio_component_get_eld,
 509 };
 510
 511 static int
 512 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev,
 513                           void *data)
 514 {
 515         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 516         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 517         struct drm_audio_component *acomp = data;
 518
 519         if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS)))
 520                 return -ENOMEM;
 521
 522         drm_modeset_lock_all(drm_dev);
 523         acomp->ops = &nv50_audio_component_ops;
 524         acomp->dev = kdev;
 525         drm->audio.component = acomp;
 526         drm_modeset_unlock_all(drm_dev);
 527         return 0;
 528 }
 529
 530 static void
 531 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev,
 532                             void *data)
 533 {
 534         struct drm_device *drm_dev = dev_get_drvdata(kdev);
 535         struct nouveau_drm *drm = nouveau_drm(drm_dev);
 536         struct drm_audio_component *acomp = data;
 537
 538         drm_modeset_lock_all(drm_dev);
 539         drm->audio.component = NULL;
 540         acomp->ops = NULL;
 541         acomp->dev = NULL;
 542         drm_modeset_unlock_all(drm_dev);
 543 }
 544
 545 static const struct component_ops nv50_audio_component_bind_ops = {
 546         .bind   = nv50_audio_component_bind,
 547         .unbind = nv50_audio_component_unbind,
 548 };
 549
 550 static void
 551 nv50_audio_component_init(struct nouveau_drm *drm)
 552 {
 553         if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
 554                 drm->audio.component_registered = true;
 555 }
 556
 557 static void
 558 nv50_audio_component_fini(struct nouveau_drm *drm)
 559 {
 560         if (drm->audio.component_registered) {
 561                 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
 562                 drm->audio.component_registered = false;
 563         }
 564 }
 565
 566 /******************************************************************************
 567  * Audio
 568  *****************************************************************************/
 569 static void
 570 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 571 {
 572         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 573         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 574         struct nv50_disp *disp = nv50_disp(encoder->dev);
 575         struct {
 576                 struct nv50_disp_mthd_v1 base;
 577                 struct nv50_disp_sor_hda_eld_v0 eld;
 578         } args = {
 579                 .base.version = 1,
 580                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 581                 .base.hasht   = nv_encoder->dcb->hasht,
 582                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 583                                 (0x0100 << nv_crtc->index),
 584         };
 585
 586         nv_encoder->audio = false;
 587         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 588
 589         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 590                                         nv_crtc->index);
 591 }
 592
 593 static void
 594 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 595 {
 596         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 597         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 598         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 599         struct nouveau_connector *nv_connector;
 600         struct nv50_disp *disp = nv50_disp(encoder->dev);
 601         struct __packed {
 602                 struct {
 603                         struct nv50_disp_mthd_v1 mthd;
 604                         struct nv50_disp_sor_hda_eld_v0 eld;
 605                 } base;
 606                 u8 data[sizeof(nv_connector->base.eld)];
 607         } args = {
 608                 .base.mthd.version = 1,
 609                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
 610                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
 611                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
 612                                      (0x0100 << nv_crtc->index),
 613         };
 614
 615         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 616         if (!drm_detect_monitor_audio(nv_connector->edid))
 617                 return;
 618
 619         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
 620
 621         nvif_mthd(&disp->disp->object, 0, &args,
 622                   sizeof(args.base) + drm_eld_size(args.data));
 623         nv_encoder->audio = true;
 624
 625         nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or,
 626                                         nv_crtc->index);
 627 }
 628
 629 /******************************************************************************
 630  * HDMI
 631  *****************************************************************************/
 632 static void
 633 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
 634 {
 635         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 636         struct nv50_disp *disp = nv50_disp(encoder->dev);
 637         struct {
 638                 struct nv50_disp_mthd_v1 base;
 639                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 640         } args = {
 641                 .base.version = 1,
 642                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 643                 .base.hasht  = nv_encoder->dcb->hasht,
 644                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 645                                (0x0100 << nv_crtc->index),
 646         };
 647
 648         nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
 649 }
 650
 651 static void
 652 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 653 {
 654         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 655         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 656         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 657         struct nv50_disp *disp = nv50_disp(encoder->dev);
 658         struct {
 659                 struct nv50_disp_mthd_v1 base;
 660                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
 661                 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
 662         } args = {
 663                 .base.version = 1,
 664                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
 665                 .base.hasht  = nv_encoder->dcb->hasht,
 666                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
 667                                (0x0100 << nv_crtc->index),
 668                 .pwr.state = 1,
 669                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
 670         };
 671         struct nouveau_connector *nv_connector;
 672         struct drm_hdmi_info *hdmi;
 673         u32 max_ac_packet;
 674         union hdmi_infoframe avi_frame;
 675         union hdmi_infoframe vendor_frame;
 676         bool high_tmds_clock_ratio = false, scrambling = false;
 677         u8 config;
 678         int ret;
 679         int size;
 680
 681         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 682         if (!drm_detect_hdmi_monitor(nv_connector->edid))
 683                 return;
 684
 685         hdmi = &nv_connector->base.display_info.hdmi;
 686
 687         ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
 688                                                        &nv_connector->base, mode);
 689         if (!ret) {
 690                 /* We have an AVI InfoFrame, populate it to the display */
 691                 args.pwr.avi_infoframe_length
 692                         = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
 693         }
 694
 695         ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
 696                                                           &nv_connector->base, mode);
 697         if (!ret) {
 698                 /* We have a Vendor InfoFrame, populate it to the display */
 699                 args.pwr.vendor_infoframe_length
 700                         = hdmi_infoframe_pack(&vendor_frame,
 701                                               args.infoframes
 702                                               + args.pwr.avi_infoframe_length,
 703                                               17);
 704         }
 705
 706         max_ac_packet  = mode->htotal - mode->hdisplay;
 707         max_ac_packet -= args.pwr.rekey;
 708         max_ac_packet -= 18; /* constant from tegra */
 709         args.pwr.max_ac_packet = max_ac_packet / 32;
 710
 711         if (hdmi->scdc.scrambling.supported) {
 712                 high_tmds_clock_ratio = mode->clock > 340000;
 713                 scrambling = high_tmds_clock_ratio ||
 714                         hdmi->scdc.scrambling.low_rates;
 715         }
 716
 717         args.pwr.scdc =
 718                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
 719                 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
 720
 721         size = sizeof(args.base)
 722                 + sizeof(args.pwr)
 723                 + args.pwr.avi_infoframe_length
 724                 + args.pwr.vendor_infoframe_length;
 725         nvif_mthd(&disp->disp->object, 0, &args, size);
 726
 727         nv50_audio_enable(encoder, mode);
 728
 729         /* If SCDC is supported by the downstream monitor, update
 730          * divider / scrambling settings to what we programmed above.
 731          */
 732         if (!hdmi->scdc.scrambling.supported)
 733                 return;
 734
 735         ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
 736         if (ret < 0) {
 737                 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
 738                 return;
 739         }
 740         config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
 741         config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
 742         config |= SCDC_SCRAMBLING_ENABLE * scrambling;
 743         ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
 744         if (ret < 0)
 745                 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
 746                          config, ret);
 747 }
 748
 749 /******************************************************************************
 750  * MST
 751  *****************************************************************************/
 752 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
 753 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
 754 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
 755
 756 struct nv50_mstm {
 757         struct nouveau_encoder *outp;
 758
 759         struct drm_dp_mst_topology_mgr mgr;
 760
 761         bool modified;
 762         bool disabled;
 763         int links;
 764 };
 765
 766 struct nv50_mstc {
 767         struct nv50_mstm *mstm;
 768         struct drm_dp_mst_port *port;
 769         struct drm_connector connector;
 770
 771         struct drm_display_mode *native;
 772         struct edid *edid;
 773 };
 774
 775 struct nv50_msto {
 776         struct drm_encoder encoder;
 777
 778         struct nv50_head *head;
 779         struct nv50_mstc *mstc;
 780         bool disabled;
 781 };
 782
 783 static struct drm_dp_payload *
 784 nv50_msto_payload(struct nv50_msto *msto)
 785 {
 786         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 787         struct nv50_mstc *mstc = msto->mstc;
 788         struct nv50_mstm *mstm = mstc->mstm;
 789         int vcpi = mstc->port->vcpi.vcpi, i;
 790
 791         WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
 792
 793         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
 794         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 795                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 796                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
 797                           mstm->outp->base.base.name, i, payload->vcpi,
 798                           payload->start_slot, payload->num_slots);
 799         }
 800
 801         for (i = 0; i < mstm->mgr.max_payloads; i++) {
 802                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
 803                 if (payload->vcpi == vcpi)
 804                         return payload;
 805         }
 806
 807         return NULL;
 808 }
 809
 810 static void
 811 nv50_msto_cleanup(struct nv50_msto *msto)
 812 {
 813         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 814         struct nv50_mstc *mstc = msto->mstc;
 815         struct nv50_mstm *mstm = mstc->mstm;
 816
 817         if (!msto->disabled)
 818                 return;
 819
 820         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
 821
 822         drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
 823
 824         msto->mstc = NULL;
 825         msto->disabled = false;
 826 }
 827
 828 static void
 829 nv50_msto_prepare(struct nv50_msto *msto)
 830 {
 831         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
 832         struct nv50_mstc *mstc = msto->mstc;
 833         struct nv50_mstm *mstm = mstc->mstm;
 834         struct {
 835                 struct nv50_disp_mthd_v1 base;
 836                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
 837         } args = {
 838                 .base.version = 1,
 839                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
 840                 .base.hasht  = mstm->outp->dcb->hasht,
 841                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
 842                                (0x0100 << msto->head->base.index),
 843         };
 844
 845         mutex_lock(&mstm->mgr.payload_lock);
 846
 847         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
 848         if (mstc->port->vcpi.vcpi > 0) {
 849                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
 850                 if (payload) {
 851                         args.vcpi.start_slot = payload->start_slot;
 852                         args.vcpi.num_slots = payload->num_slots;
 853                         args.vcpi.pbn = mstc->port->vcpi.pbn;
 854                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
 855                 }
 856         }
 857
 858         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
 859                   msto->encoder.name, msto->head->base.base.name,
 860                   args.vcpi.start_slot, args.vcpi.num_slots,
 861                   args.vcpi.pbn, args.vcpi.aligned_pbn);
 862
 863         nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
 864         mutex_unlock(&mstm->mgr.payload_lock);
 865 }
 866
 867 static int
 868 nv50_msto_atomic_check(struct drm_encoder *encoder,
 869                        struct drm_crtc_state *crtc_state,
 870                        struct drm_connector_state *conn_state)
 871 {
 872         struct drm_atomic_state *state = crtc_state->state;
 873         struct drm_connector *connector = conn_state->connector;
 874         struct nv50_mstc *mstc = nv50_mstc(connector);
 875         struct nv50_mstm *mstm = mstc->mstm;
 876         struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 877         int slots;
 878         int ret;
 879
 880         ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
 881                                           mstc->native);
 882         if (ret)
 883                 return ret;
 884
 885         if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
 886                 return 0;
 887
 888         /*
 889          * When restoring duplicated states, we need to make sure that the bw
 890          * remains the same and avoid recalculating it, as the connector's bpc
 891          * may have changed after the state was duplicated
 892          */
 893         if (!state->duplicated) {
 894                 const int clock = crtc_state->adjusted_mode.clock;
 895
 896                 asyh->or.bpc = connector->display_info.bpc;
 897                 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
 898                                                     false);
 899         }
 900
 901         slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
 902                                               asyh->dp.pbn, 0);
 903         if (slots < 0)
 904                 return slots;
 905
 906         asyh->dp.tu = slots;
 907
 908         return 0;
 909 }
 910
 911 static u8
 912 nv50_dp_bpc_to_depth(unsigned int bpc)
 913 {
 914         switch (bpc) {
 915         case  6: return 0x2;
 916         case  8: return 0x5;
 917         case 10: /* fall-through */
 918         default: return 0x6;
 919         }
 920 }
 921
 922 static void
 923 nv50_msto_enable(struct drm_encoder *encoder)
 924 {
 925         struct nv50_head *head = nv50_head(encoder->crtc);
 926         struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
 927         struct nv50_msto *msto = nv50_msto(encoder);
 928         struct nv50_mstc *mstc = NULL;
 929         struct nv50_mstm *mstm = NULL;
 930         struct drm_connector *connector;
 931         struct drm_connector_list_iter conn_iter;
 932         u8 proto;
 933         bool r;
 934
 935         drm_connector_list_iter_begin(encoder->dev, &conn_iter);
 936         drm_for_each_connector_iter(connector, &conn_iter) {
 937                 if (connector->state->best_encoder == &msto->encoder) {
 938                         mstc = nv50_mstc(connector);
 939                         mstm = mstc->mstm;
 940                         break;
 941                 }
 942         }
 943         drm_connector_list_iter_end(&conn_iter);
 944
 945         if (WARN_ON(!mstc))
 946                 return;
 947
 948         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
 949                                      armh->dp.tu);
 950         if (!r)
 951                 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
 952
 953         if (!mstm->links++)
 954                 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/);
 955
 956         if (mstm->outp->link & 1)
 957                 proto = 0x8;
 958         else
 959                 proto = 0x9;
 960
 961         mstm->outp->update(mstm->outp, head->base.index, armh, proto,
 962                            nv50_dp_bpc_to_depth(armh->or.bpc));
 963
 964         msto->mstc = mstc;
 965         mstm->modified = true;
 966 }
 967
 968 static void
 969 nv50_msto_disable(struct drm_encoder *encoder)
 970 {
 971         struct nv50_msto *msto = nv50_msto(encoder);
 972         struct nv50_mstc *mstc = msto->mstc;
 973         struct nv50_mstm *mstm = mstc->mstm;
 974
 975         drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
 976
 977         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
 978         mstm->modified = true;
 979         if (!--mstm->links)
 980                 mstm->disabled = true;
 981         msto->disabled = true;
 982 }
 983
 984 static const struct drm_encoder_helper_funcs
 985 nv50_msto_help = {
 986         .disable = nv50_msto_disable,
 987         .enable = nv50_msto_enable,
 988         .atomic_check = nv50_msto_atomic_check,
 989 };
 990
 991 static void
 992 nv50_msto_destroy(struct drm_encoder *encoder)
 993 {
 994         struct nv50_msto *msto = nv50_msto(encoder);
 995         drm_encoder_cleanup(&msto->encoder);
 996         kfree(msto);
 997 }
 998
 999 static const struct drm_encoder_funcs
1000 nv50_msto = {
1001         .destroy = nv50_msto_destroy,
1002 };
1003
1004 static struct nv50_msto *
1005 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1006 {
1007         struct nv50_msto *msto;
1008         int ret;
1009
1010         msto = kzalloc(sizeof(*msto), GFP_KERNEL);
1011         if (!msto)
1012                 return ERR_PTR(-ENOMEM);
1013
1014         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1015                                DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1016         if (ret) {
1017                 kfree(msto);
1018                 return ERR_PTR(ret);
1019         }
1020
1021         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1022         msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1023         msto->head = head;
1024         return msto;
1025 }
1026
1027 static struct drm_encoder *
1028 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
1029                               struct drm_connector_state *connector_state)
1030 {
1031         struct nv50_mstc *mstc = nv50_mstc(connector);
1032         struct drm_crtc *crtc = connector_state->crtc;
1033
1034         if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1035                 return NULL;
1036
1037         return &nv50_head(crtc)->msto->encoder;
1038 }
1039
1040 static enum drm_mode_status
1041 nv50_mstc_mode_valid(struct drm_connector *connector,
1042                      struct drm_display_mode *mode)
1043 {
1044         struct nv50_mstc *mstc = nv50_mstc(connector);
1045         struct nouveau_encoder *outp = mstc->mstm->outp;
1046
1047         /* TODO: calculate the PBN from the dotclock and validate against the
1048          * MSTB's max possible PBN
1049          */
1050
1051         return nv50_dp_mode_valid(connector, outp, mode, NULL);
1052 }
1053
1054 static int
1055 nv50_mstc_get_modes(struct drm_connector *connector)
1056 {
1057         struct nv50_mstc *mstc = nv50_mstc(connector);
1058         int ret = 0;
1059
1060         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1061         drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1062         if (mstc->edid)
1063                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1064
1065         /*
1066          * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
1067          * to 8 to save bandwidth on the topology. In the future, we'll want
1068          * to properly fix this by dynamically selecting the highest possible
1069          * bpc that would fit in the topology
1070          */
1071         if (connector->display_info.bpc)
1072                 connector->display_info.bpc =
1073                         clamp(connector->display_info.bpc, 6U, 8U);
1074         else
1075                 connector->display_info.bpc = 8;
1076
1077         if (mstc->native)
1078                 drm_mode_destroy(mstc->connector.dev, mstc->native);
1079         mstc->native = nouveau_conn_native_mode(&mstc->connector);
1080         return ret;
1081 }
1082
1083 static int
1084 nv50_mstc_atomic_check(struct drm_connector *connector,
1085                        struct drm_atomic_state *state)
1086 {
1087         struct nv50_mstc *mstc = nv50_mstc(connector);
1088         struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1089         struct drm_connector_state *new_conn_state =
1090                 drm_atomic_get_new_connector_state(state, connector);
1091         struct drm_connector_state *old_conn_state =
1092                 drm_atomic_get_old_connector_state(state, connector);
1093         struct drm_crtc_state *crtc_state;
1094         struct drm_crtc *new_crtc = new_conn_state->crtc;
1095
1096         if (!old_conn_state->crtc)
1097                 return 0;
1098
1099         /* We only want to free VCPI if this state disables the CRTC on this
1100          * connector
1101          */
1102         if (new_crtc) {
1103                 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1104
1105                 if (!crtc_state ||
1106                     !drm_atomic_crtc_needs_modeset(crtc_state) ||
1107                     crtc_state->enable)
1108                         return 0;
1109         }
1110
1111         return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1112 }
1113
1114 static int
1115 nv50_mstc_detect(struct drm_connector *connector,
1116                  struct drm_modeset_acquire_ctx *ctx, bool force)
1117 {
1118         struct nv50_mstc *mstc = nv50_mstc(connector);
1119         int ret;
1120
1121         if (drm_connector_is_unregistered(connector))
1122                 return connector_status_disconnected;
1123
1124         ret = pm_runtime_get_sync(connector->dev->dev);
1125         if (ret < 0 && ret != -EACCES) {
1126                 pm_runtime_put_autosuspend(connector->dev->dev);
1127                 return connector_status_disconnected;
1128         }
1129
1130         ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1131                                      mstc->port);
1132
1133         pm_runtime_mark_last_busy(connector->dev->dev);
1134         pm_runtime_put_autosuspend(connector->dev->dev);
1135         return ret;
1136 }
1137
1138 static const struct drm_connector_helper_funcs
1139 nv50_mstc_help = {
1140         .get_modes = nv50_mstc_get_modes,
1141         .mode_valid = nv50_mstc_mode_valid,
1142         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1143         .atomic_check = nv50_mstc_atomic_check,
1144         .detect_ctx = nv50_mstc_detect,
1145 };
1146
1147 static void
1148 nv50_mstc_destroy(struct drm_connector *connector)
1149 {
1150         struct nv50_mstc *mstc = nv50_mstc(connector);
1151
1152         drm_connector_cleanup(&mstc->connector);
1153         drm_dp_mst_put_port_malloc(mstc->port);
1154
1155         kfree(mstc);
1156 }
1157
1158 static const struct drm_connector_funcs
1159 nv50_mstc = {
1160         .reset = nouveau_conn_reset,
1161         .fill_modes = drm_helper_probe_single_connector_modes,
1162         .destroy = nv50_mstc_destroy,
1163         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1164         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1165         .atomic_set_property = nouveau_conn_atomic_set_property,
1166         .atomic_get_property = nouveau_conn_atomic_get_property,
1167 };
1168
1169 static int
1170 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1171               const char *path, struct nv50_mstc **pmstc)
1172 {
1173         struct drm_device *dev = mstm->outp->base.base.dev;
1174         struct drm_crtc *crtc;
1175         struct nv50_mstc *mstc;
1176         int ret;
1177
1178         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1179                 return -ENOMEM;
1180         mstc->mstm = mstm;
1181         mstc->port = port;
1182
1183         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1184                                  DRM_MODE_CONNECTOR_DisplayPort);
1185         if (ret) {
1186                 kfree(*pmstc);
1187                 *pmstc = NULL;
1188                 return ret;
1189         }
1190
1191         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1192
1193         mstc->connector.funcs->reset(&mstc->connector);
1194         nouveau_conn_attach_properties(&mstc->connector);
1195
1196         drm_for_each_crtc(crtc, dev) {
1197                 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1198                         continue;
1199
1200                 drm_connector_attach_encoder(&mstc->connector,
1201                                              &nv50_head(crtc)->msto->encoder);
1202         }
1203
1204         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1205         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1206         drm_connector_set_path_property(&mstc->connector, path);
1207         drm_dp_mst_get_port_malloc(port);
1208         return 0;
1209 }
1210
1211 static void
1212 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1213 {
1214         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1215         struct drm_encoder *encoder;
1216         int ret;
1217
1218         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1219         ret = drm_dp_check_act_status(&mstm->mgr);
1220
1221         ret = drm_dp_update_payload_part2(&mstm->mgr);
1222
1223         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1224                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1225                         struct nv50_msto *msto = nv50_msto(encoder);
1226                         struct nv50_mstc *mstc = msto->mstc;
1227                         if (mstc && mstc->mstm == mstm)
1228                                 nv50_msto_cleanup(msto);
1229                 }
1230         }
1231
1232         mstm->modified = false;
1233 }
1234
1235 static void
1236 nv50_mstm_prepare(struct nv50_mstm *mstm)
1237 {
1238         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1239         struct drm_encoder *encoder;
1240         int ret;
1241
1242         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1243         ret = drm_dp_update_payload_part1(&mstm->mgr);
1244
1245         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1246                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1247                         struct nv50_msto *msto = nv50_msto(encoder);
1248                         struct nv50_mstc *mstc = msto->mstc;
1249                         if (mstc && mstc->mstm == mstm)
1250                                 nv50_msto_prepare(msto);
1251                 }
1252         }
1253
1254         if (mstm->disabled) {
1255                 if (!mstm->links)
1256                         nv50_outp_release(mstm->outp);
1257                 mstm->disabled = false;
1258         }
1259 }
1260
1261 static struct drm_connector *
1262 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1263                         struct drm_dp_mst_port *port, const char *path)
1264 {
1265         struct nv50_mstm *mstm = nv50_mstm(mgr);
1266         struct nv50_mstc *mstc;
1267         int ret;
1268
1269         ret = nv50_mstc_new(mstm, port, path, &mstc);
1270         if (ret)
1271                 return NULL;
1272
1273         return &mstc->connector;
1274 }
1275
1276 static const struct drm_dp_mst_topology_cbs
1277 nv50_mstm = {
1278         .add_connector = nv50_mstm_add_connector,
1279 };
1280
1281 void
1282 nv50_mstm_service(struct nv50_mstm *mstm)
1283 {
1284         struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1285         bool handled = true;
1286         int ret;
1287         u8 esi[8] = {};
1288
1289         if (!aux)
1290                 return;
1291
1292         while (handled) {
1293                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1294                 if (ret != 8) {
1295                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1296                         return;
1297                 }
1298
1299                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1300                 if (!handled)
1301                         break;
1302
1303                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1304         }
1305 }
1306
1307 void
1308 nv50_mstm_remove(struct nv50_mstm *mstm)
1309 {
1310         if (mstm)
1311                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1312 }
1313
1314 static int
1315 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1316 {
1317         struct nouveau_encoder *outp = mstm->outp;
1318         struct {
1319                 struct nv50_disp_mthd_v1 base;
1320                 struct nv50_disp_sor_dp_mst_link_v0 mst;
1321         } args = {
1322                 .base.version = 1,
1323                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1324                 .base.hasht = outp->dcb->hasht,
1325                 .base.hashm = outp->dcb->hashm,
1326                 .mst.state = state,
1327         };
1328         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1329         struct nvif_object *disp = &drm->display->disp.object;
1330         int ret;
1331
1332         if (dpcd >= 0x12) {
1333                 /* Even if we're enabling MST, start with disabling the
1334                  * branching unit to clear any sink-side MST topology state
1335                  * that wasn't set by us
1336                  */
1337                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1338                 if (ret < 0)
1339                         return ret;
1340
1341                 if (state) {
1342                         /* Now, start initializing */
1343                         ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1344                                                  DP_MST_EN);
1345                         if (ret < 0)
1346                                 return ret;
1347                 }
1348         }
1349
1350         return nvif_mthd(disp, 0, &args, sizeof(args));
1351 }
1352
1353 int
1354 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1355 {
1356         struct drm_dp_aux *aux;
1357         int ret;
1358         bool old_state, new_state;
1359         u8 mstm_ctrl;
1360
1361         if (!mstm)
1362                 return 0;
1363
1364         mutex_lock(&mstm->mgr.lock);
1365
1366         old_state = mstm->mgr.mst_state;
1367         new_state = old_state;
1368         aux = mstm->mgr.aux;
1369
1370         if (old_state) {
1371                 /* Just check that the MST hub is still as we expect it */
1372                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1373                 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1374                         DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1375                         new_state = false;
1376                 }
1377         } else if (dpcd[0] >= 0x12) {
1378                 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1379                 if (ret < 0)
1380                         goto probe_error;
1381
1382                 if (!(dpcd[1] & DP_MST_CAP))
1383                         dpcd[0] = 0x11;
1384                 else
1385                         new_state = allow;
1386         }
1387
1388         if (new_state == old_state) {
1389                 mutex_unlock(&mstm->mgr.lock);
1390                 return new_state;
1391         }
1392
1393         ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1394         if (ret)
1395                 goto probe_error;
1396
1397         mutex_unlock(&mstm->mgr.lock);
1398
1399         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1400         if (ret)
1401                 return nv50_mstm_enable(mstm, dpcd[0], 0);
1402
1403         return new_state;
1404
1405 probe_error:
1406         mutex_unlock(&mstm->mgr.lock);
1407         return ret;
1408 }
1409
1410 static void
1411 nv50_mstm_fini(struct nv50_mstm *mstm)
1412 {
1413         if (mstm && mstm->mgr.mst_state)
1414                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1415 }
1416
1417 static void
1418 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime)
1419 {
1420         int ret;
1421
1422         if (!mstm || !mstm->mgr.mst_state)
1423                 return;
1424
1425         ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1426         if (ret == -1) {
1427                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1428                 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1429         }
1430 }
1431
1432 static void
1433 nv50_mstm_del(struct nv50_mstm **pmstm)
1434 {
1435         struct nv50_mstm *mstm = *pmstm;
1436         if (mstm) {
1437                 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1438                 kfree(*pmstm);
1439                 *pmstm = NULL;
1440         }
1441 }
1442
1443 static int
1444 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1445               int conn_base_id, struct nv50_mstm **pmstm)
1446 {
1447         const int max_payloads = hweight8(outp->dcb->heads);
1448         struct drm_device *dev = outp->base.base.dev;
1449         struct nv50_mstm *mstm;
1450         int ret;
1451         u8 dpcd;
1452
1453         /* This is a workaround for some monitors not functioning
1454          * correctly in MST mode on initial module load.  I think
1455          * some bad interaction with the VBIOS may be responsible.
1456          *
1457          * A good ol' off and on again seems to work here ;)
1458          */
1459         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1460         if (ret >= 0 && dpcd >= 0x12)
1461                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1462
1463         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1464                 return -ENOMEM;
1465         mstm->outp = outp;
1466         mstm->mgr.cbs = &nv50_mstm;
1467
1468         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1469                                            max_payloads, conn_base_id);
1470         if (ret)
1471                 return ret;
1472
1473         return 0;
1474 }
1475
1476 /******************************************************************************
1477  * SOR
1478  *****************************************************************************/
1479 static void
1480 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1481                 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1482 {
1483         struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1484         struct nv50_core *core = disp->core;
1485
1486         if (!asyh) {
1487                 nv_encoder->ctrl &= ~BIT(head);
1488                 if (!(nv_encoder->ctrl & 0x0000000f))
1489                         nv_encoder->ctrl = 0;
1490         } else {
1491                 nv_encoder->ctrl |= proto << 8;
1492                 nv_encoder->ctrl |= BIT(head);
1493                 asyh->or.depth = depth;
1494         }
1495
1496         core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1497 }
1498
1499 static void
1500 nv50_sor_disable(struct drm_encoder *encoder)
1501 {
1502         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1503         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1504
1505         nv_encoder->crtc = NULL;
1506
1507         if (nv_crtc) {
1508                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1509                 u8 pwr;
1510
1511                 if (aux) {
1512                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1513                         if (ret == 0) {
1514                                 pwr &= ~DP_SET_POWER_MASK;
1515                                 pwr |=  DP_SET_POWER_D3;
1516                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1517                         }
1518                 }
1519
1520                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1521                 nv50_audio_disable(encoder, nv_crtc);
1522                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1523                 nv50_outp_release(nv_encoder);
1524         }
1525 }
1526
1527 static void
1528 nv50_sor_enable(struct drm_encoder *encoder)
1529 {
1530         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1531         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1532         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1533         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1534         struct {
1535                 struct nv50_disp_mthd_v1 base;
1536                 struct nv50_disp_sor_lvds_script_v0 lvds;
1537         } lvds = {
1538                 .base.version = 1,
1539                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1540                 .base.hasht   = nv_encoder->dcb->hasht,
1541                 .base.hashm   = nv_encoder->dcb->hashm,
1542         };
1543         struct nv50_disp *disp = nv50_disp(encoder->dev);
1544         struct drm_device *dev = encoder->dev;
1545         struct nouveau_drm *drm = nouveau_drm(dev);
1546         struct nouveau_connector *nv_connector;
1547         struct nvbios *bios = &drm->vbios;
1548         bool hda = false;
1549         u8 proto = 0xf;
1550         u8 depth = 0x0;
1551
1552         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1553         nv_encoder->crtc = encoder->crtc;
1554
1555         if ((disp->disp->object.oclass == GT214_DISP ||
1556              disp->disp->object.oclass >= GF110_DISP) &&
1557             drm_detect_monitor_audio(nv_connector->edid))
1558                 hda = true;
1559         nv50_outp_acquire(nv_encoder, hda);
1560
1561         switch (nv_encoder->dcb->type) {
1562         case DCB_OUTPUT_TMDS:
1563                 if (nv_encoder->link & 1) {
1564                         proto = 0x1;
1565                         /* Only enable dual-link if:
1566                          *  - Need to (i.e. rate > 165MHz)
1567                          *  - DCB says we can
1568                          *  - Not an HDMI monitor, since there's no dual-link
1569                          *    on HDMI.
1570                          */
1571                         if (mode->clock >= 165000 &&
1572                             nv_encoder->dcb->duallink_possible &&
1573                             !drm_detect_hdmi_monitor(nv_connector->edid))
1574                                 proto |= 0x4;
1575                 } else {
1576                         proto = 0x2;
1577                 }
1578
1579                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1580                 break;
1581         case DCB_OUTPUT_LVDS:
1582                 proto = 0x0;
1583
1584                 if (bios->fp_no_ddc) {
1585                         if (bios->fp.dual_link)
1586                                 lvds.lvds.script |= 0x0100;
1587                         if (bios->fp.if_is_24bit)
1588                                 lvds.lvds.script |= 0x0200;
1589                 } else {
1590                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1591                                 if (((u8 *)nv_connector->edid)[121] == 2)
1592                                         lvds.lvds.script |= 0x0100;
1593                         } else
1594                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1595                                 lvds.lvds.script |= 0x0100;
1596                         }
1597
1598                         if (lvds.lvds.script & 0x0100) {
1599                                 if (bios->fp.strapless_is_24bit & 2)
1600                                         lvds.lvds.script |= 0x0200;
1601                         } else {
1602                                 if (bios->fp.strapless_is_24bit & 1)
1603                                         lvds.lvds.script |= 0x0200;
1604                         }
1605
1606                         if (asyh->or.bpc == 8)
1607                                 lvds.lvds.script |= 0x0200;
1608                 }
1609
1610                 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1611                 break;
1612         case DCB_OUTPUT_DP:
1613                 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1614
1615                 if (nv_encoder->link & 1)
1616                         proto = 0x8;
1617                 else
1618                         proto = 0x9;
1619
1620                 nv50_audio_enable(encoder, mode);
1621                 break;
1622         default:
1623                 BUG();
1624                 break;
1625         }
1626
1627         nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1628 }
1629
1630 static const struct drm_encoder_helper_funcs
1631 nv50_sor_help = {
1632         .atomic_check = nv50_outp_atomic_check,
1633         .enable = nv50_sor_enable,
1634         .disable = nv50_sor_disable,
1635 };
1636
1637 static void
1638 nv50_sor_destroy(struct drm_encoder *encoder)
1639 {
1640         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1641         nv50_mstm_del(&nv_encoder->dp.mstm);
1642         drm_encoder_cleanup(encoder);
1643         kfree(encoder);
1644 }
1645
1646 static const struct drm_encoder_funcs
1647 nv50_sor_func = {
1648         .destroy = nv50_sor_destroy,
1649 };
1650
1651 static bool nv50_has_mst(struct nouveau_drm *drm)
1652 {
1653         struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1654         u32 data;
1655         u8 ver, hdr, cnt, len;
1656
1657         data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len);
1658         return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04);
1659 }
1660
1661 static int
1662 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1663 {
1664         struct nouveau_connector *nv_connector = nouveau_connector(connector);
1665         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1666         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1667         struct nouveau_encoder *nv_encoder;
1668         struct drm_encoder *encoder;
1669         struct nv50_disp *disp = nv50_disp(connector->dev);
1670         int type, ret;
1671
1672         switch (dcbe->type) {
1673         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1674         case DCB_OUTPUT_TMDS:
1675         case DCB_OUTPUT_DP:
1676         default:
1677                 type = DRM_MODE_ENCODER_TMDS;
1678                 break;
1679         }
1680
1681         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1682         if (!nv_encoder)
1683                 return -ENOMEM;
1684         nv_encoder->dcb = dcbe;
1685         nv_encoder->update = nv50_sor_update;
1686
1687         encoder = to_drm_encoder(nv_encoder);
1688         encoder->possible_crtcs = dcbe->heads;
1689         encoder->possible_clones = 0;
1690         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1691                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1692         drm_encoder_helper_add(encoder, &nv50_sor_help);
1693
1694         drm_connector_attach_encoder(connector, encoder);
1695
1696         disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1697
1698         if (dcbe->type == DCB_OUTPUT_DP) {
1699                 struct nvkm_i2c_aux *aux =
1700                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1701
1702                 if (aux) {
1703                         if (disp->disp->object.oclass < GF110_DISP) {
1704                                 /* HW has no support for address-only
1705                                  * transactions, so we're required to
1706                                  * use custom I2C-over-AUX code.
1707                                  */
1708                                 nv_encoder->i2c = &aux->i2c;
1709                         } else {
1710                                 nv_encoder->i2c = &nv_connector->aux.ddc;
1711                         }
1712                         nv_encoder->aux = aux;
1713                 }
1714
1715                 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1716                     nv50_has_mst(drm)) {
1717                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1718                                             16, nv_connector->base.base.id,
1719                                             &nv_encoder->dp.mstm);
1720                         if (ret)
1721                                 return ret;
1722                 }
1723         } else {
1724                 struct nvkm_i2c_bus *bus =
1725                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1726                 if (bus)
1727                         nv_encoder->i2c = &bus->i2c;
1728         }
1729
1730         return 0;
1731 }
1732
1733 /******************************************************************************
1734  * PIOR
1735  *****************************************************************************/
1736 static int
1737 nv50_pior_atomic_check(struct drm_encoder *encoder,
1738                        struct drm_crtc_state *crtc_state,
1739                        struct drm_connector_state *conn_state)
1740 {
1741         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1742         if (ret)
1743                 return ret;
1744         crtc_state->adjusted_mode.clock *= 2;
1745         return 0;
1746 }
1747
1748 static void
1749 nv50_pior_disable(struct drm_encoder *encoder)
1750 {
1751         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1752         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1753         if (nv_encoder->crtc)
1754                 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1755         nv_encoder->crtc = NULL;
1756         nv50_outp_release(nv_encoder);
1757 }
1758
1759 static void
1760 nv50_pior_enable(struct drm_encoder *encoder)
1761 {
1762         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1763         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1764         struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1765         struct nv50_core *core = nv50_disp(encoder->dev)->core;
1766         u8 owner = 1 << nv_crtc->index;
1767         u8 proto;
1768
1769         nv50_outp_acquire(nv_encoder, false);
1770
1771         switch (asyh->or.bpc) {
1772         case 10: asyh->or.depth = 0x6; break;
1773         case  8: asyh->or.depth = 0x5; break;
1774         case  6: asyh->or.depth = 0x2; break;
1775         default: asyh->or.depth = 0x0; break;
1776         }
1777
1778         switch (nv_encoder->dcb->type) {
1779         case DCB_OUTPUT_TMDS:
1780         case DCB_OUTPUT_DP:
1781                 proto = 0x0;
1782                 break;
1783         default:
1784                 BUG();
1785                 break;
1786         }
1787
1788         core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1789         nv_encoder->crtc = encoder->crtc;
1790 }
1791
1792 static const struct drm_encoder_helper_funcs
1793 nv50_pior_help = {
1794         .atomic_check = nv50_pior_atomic_check,
1795         .enable = nv50_pior_enable,
1796         .disable = nv50_pior_disable,
1797 };
1798
1799 static void
1800 nv50_pior_destroy(struct drm_encoder *encoder)
1801 {
1802         drm_encoder_cleanup(encoder);
1803         kfree(encoder);
1804 }
1805
1806 static const struct drm_encoder_funcs
1807 nv50_pior_func = {
1808         .destroy = nv50_pior_destroy,
1809 };
1810
1811 static int
1812 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1813 {
1814         struct drm_device *dev = connector->dev;
1815         struct nouveau_drm *drm = nouveau_drm(dev);
1816         struct nv50_disp *disp = nv50_disp(dev);
1817         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1818         struct nvkm_i2c_bus *bus = NULL;
1819         struct nvkm_i2c_aux *aux = NULL;
1820         struct i2c_adapter *ddc;
1821         struct nouveau_encoder *nv_encoder;
1822         struct drm_encoder *encoder;
1823         int type;
1824
1825         switch (dcbe->type) {
1826         case DCB_OUTPUT_TMDS:
1827                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1828                 ddc  = bus ? &bus->i2c : NULL;
1829                 type = DRM_MODE_ENCODER_TMDS;
1830                 break;
1831         case DCB_OUTPUT_DP:
1832                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1833                 ddc  = aux ? &aux->i2c : NULL;
1834                 type = DRM_MODE_ENCODER_TMDS;
1835                 break;
1836         default:
1837                 return -ENODEV;
1838         }
1839
1840         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1841         if (!nv_encoder)
1842                 return -ENOMEM;
1843         nv_encoder->dcb = dcbe;
1844         nv_encoder->i2c = ddc;
1845         nv_encoder->aux = aux;
1846
1847         encoder = to_drm_encoder(nv_encoder);
1848         encoder->possible_crtcs = dcbe->heads;
1849         encoder->possible_clones = 0;
1850         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1851                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1852         drm_encoder_helper_add(encoder, &nv50_pior_help);
1853
1854         drm_connector_attach_encoder(connector, encoder);
1855
1856         disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1857
1858         return 0;
1859 }
1860
1861 /******************************************************************************
1862  * Atomic
1863  *****************************************************************************/
1864
1865 static void
1866 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1867 {
1868         struct nouveau_drm *drm = nouveau_drm(state->dev);
1869         struct nv50_disp *disp = nv50_disp(drm->dev);
1870         struct nv50_core *core = disp->core;
1871         struct nv50_mstm *mstm;
1872         struct drm_encoder *encoder;
1873
1874         NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1875
1876         drm_for_each_encoder(encoder, drm->dev) {
1877                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1878                         mstm = nouveau_encoder(encoder)->dp.mstm;
1879                         if (mstm && mstm->modified)
1880                                 nv50_mstm_prepare(mstm);
1881                 }
1882         }
1883
1884         core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1885         core->func->update(core, interlock, true);
1886         if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1887                                        disp->core->chan.base.device))
1888                 NV_ERROR(drm, "core notifier timeout\n");
1889
1890         drm_for_each_encoder(encoder, drm->dev) {
1891                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1892                         mstm = nouveau_encoder(encoder)->dp.mstm;
1893                         if (mstm && mstm->modified)
1894                                 nv50_mstm_cleanup(mstm);
1895                 }
1896         }
1897 }
1898
1899 static void
1900 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1901 {
1902         struct drm_plane_state *new_plane_state;
1903         struct drm_plane *plane;
1904         int i;
1905
1906         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1907                 struct nv50_wndw *wndw = nv50_wndw(plane);
1908                 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1909                         if (wndw->func->update)
1910                                 wndw->func->update(wndw, interlock);
1911                 }
1912         }
1913 }
1914
1915 static void
1916 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1917 {
1918         struct drm_device *dev = state->dev;
1919         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1920         struct drm_crtc *crtc;
1921         struct drm_plane_state *new_plane_state;
1922         struct drm_plane *plane;
1923         struct nouveau_drm *drm = nouveau_drm(dev);
1924         struct nv50_disp *disp = nv50_disp(dev);
1925         struct nv50_atom *atom = nv50_atom(state);
1926         struct nv50_core *core = disp->core;
1927         struct nv50_outp_atom *outp, *outt;
1928         u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1929         int i;
1930
1931         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1932         drm_atomic_helper_wait_for_fences(dev, state, false);
1933         drm_atomic_helper_wait_for_dependencies(state);
1934         drm_atomic_helper_update_legacy_modeset_state(dev, state);
1935
1936         if (atom->lock_core)
1937                 mutex_lock(&disp->mutex);
1938
1939         /* Disable head(s). */
1940         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1941                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1942                 struct nv50_head *head = nv50_head(crtc);
1943
1944                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1945                           asyh->clr.mask, asyh->set.mask);
1946
1947                 if (old_crtc_state->active && !new_crtc_state->active) {
1948                         pm_runtime_put_noidle(dev->dev);
1949                         drm_crtc_vblank_off(crtc);
1950                 }
1951
1952                 if (asyh->clr.mask) {
1953                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
1954                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1955                 }
1956         }
1957
1958         /* Disable plane(s). */
1959         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1960                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1961                 struct nv50_wndw *wndw = nv50_wndw(plane);
1962
1963                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1964                           asyw->clr.mask, asyw->set.mask);
1965                 if (!asyw->clr.mask)
1966                         continue;
1967
1968                 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1969         }
1970
1971         /* Disable output path(s). */
1972         list_for_each_entry(outp, &atom->outp, head) {
1973                 const struct drm_encoder_helper_funcs *help;
1974                 struct drm_encoder *encoder;
1975
1976                 encoder = outp->encoder;
1977                 help = encoder->helper_private;
1978
1979                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1980                           outp->clr.mask, outp->set.mask);
1981
1982                 if (outp->clr.mask) {
1983                         help->disable(encoder);
1984                         interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1985                         if (outp->flush_disable) {
1986                                 nv50_disp_atomic_commit_wndw(state, interlock);
1987                                 nv50_disp_atomic_commit_core(state, interlock);
1988                                 memset(interlock, 0x00, sizeof(interlock));
1989                         }
1990                 }
1991         }
1992
1993         /* Flush disable. */
1994         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1995                 if (atom->flush_disable) {
1996                         nv50_disp_atomic_commit_wndw(state, interlock);
1997                         nv50_disp_atomic_commit_core(state, interlock);
1998                         memset(interlock, 0x00, sizeof(interlock));
1999                 }
2000         }
2001
2002         /* Update output path(s). */
2003         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2004                 const struct drm_encoder_helper_funcs *help;
2005                 struct drm_encoder *encoder;
2006
2007                 encoder = outp->encoder;
2008                 help = encoder->helper_private;
2009
2010                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2011                           outp->set.mask, outp->clr.mask);
2012
2013                 if (outp->set.mask) {
2014                         help->enable(encoder);
2015                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2016                 }
2017
2018                 list_del(&outp->head);
2019                 kfree(outp);
2020         }
2021
2022         /* Update head(s). */
2023         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2024                 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2025                 struct nv50_head *head = nv50_head(crtc);
2026
2027                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2028                           asyh->set.mask, asyh->clr.mask);
2029
2030                 if (asyh->set.mask) {
2031                         nv50_head_flush_set(head, asyh);
2032                         interlock[NV50_DISP_INTERLOCK_CORE] = 1;
2033                 }
2034
2035                 if (new_crtc_state->active) {
2036                         if (!old_crtc_state->active) {
2037                                 drm_crtc_vblank_on(crtc);
2038                                 pm_runtime_get_noresume(dev->dev);
2039                         }
2040                         if (new_crtc_state->event)
2041                                 drm_crtc_vblank_get(crtc);
2042                 }
2043         }
2044
2045         /* Update window->head assignment.
2046          *
2047          * This has to happen in an update that's not interlocked with
2048          * any window channels to avoid hitting HW error checks.
2049          *
2050          *TODO: Proper handling of window ownership (Turing apparently
2051          *      supports non-fixed mappings).
2052          */
2053         if (core->assign_windows) {
2054                 core->func->wndw.owner(core);
2055                 core->func->update(core, interlock, false);
2056                 core->assign_windows = false;
2057                 interlock[NV50_DISP_INTERLOCK_CORE] = 0;
2058         }
2059
2060         /* Update plane(s). */
2061         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2062                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2063                 struct nv50_wndw *wndw = nv50_wndw(plane);
2064
2065                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2066                           asyw->set.mask, asyw->clr.mask);
2067                 if ( !asyw->set.mask &&
2068                     (!asyw->clr.mask || atom->flush_disable))
2069                         continue;
2070
2071                 nv50_wndw_flush_set(wndw, interlock, asyw);
2072         }
2073
2074         /* Flush update. */
2075         nv50_disp_atomic_commit_wndw(state, interlock);
2076
2077         if (interlock[NV50_DISP_INTERLOCK_CORE]) {
2078                 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
2079                     interlock[NV50_DISP_INTERLOCK_OVLY] ||
2080                     interlock[NV50_DISP_INTERLOCK_WNDW] ||
2081                     !atom->state.legacy_cursor_update)
2082                         nv50_disp_atomic_commit_core(state, interlock);
2083                 else
2084                         disp->core->func->update(disp->core, interlock, false);
2085         }
2086
2087         if (atom->lock_core)
2088                 mutex_unlock(&disp->mutex);
2089
2090         /* Wait for HW to signal completion. */
2091         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2092                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2093                 struct nv50_wndw *wndw = nv50_wndw(plane);
2094                 int ret = nv50_wndw_wait_armed(wndw, asyw);
2095                 if (ret)
2096                         NV_ERROR(drm, "%s: timeout\n", plane->name);
2097         }
2098
2099         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2100                 if (new_crtc_state->event) {
2101                         unsigned long flags;
2102                         /* Get correct count/ts if racing with vblank irq */
2103                         if (new_crtc_state->active)
2104                                 drm_crtc_accurate_vblank_count(crtc);
2105                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
2106                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2107                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2108
2109                         new_crtc_state->event = NULL;
2110                         if (new_crtc_state->active)
2111                                 drm_crtc_vblank_put(crtc);
2112                 }
2113         }
2114
2115         drm_atomic_helper_commit_hw_done(state);
2116         drm_atomic_helper_cleanup_planes(dev, state);
2117         drm_atomic_helper_commit_cleanup_done(state);
2118         drm_atomic_state_put(state);
2119
2120         /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2121         pm_runtime_mark_last_busy(dev->dev);
2122         pm_runtime_put_autosuspend(dev->dev);
2123 }
2124
2125 static void
2126 nv50_disp_atomic_commit_work(struct work_struct *work)
2127 {
2128         struct drm_atomic_state *state =
2129                 container_of(work, typeof(*state), commit_work);
2130         nv50_disp_atomic_commit_tail(state);
2131 }
2132
2133 static int
2134 nv50_disp_atomic_commit(struct drm_device *dev,
2135                         struct drm_atomic_state *state, bool nonblock)
2136 {
2137         struct drm_plane_state *new_plane_state;
2138         struct drm_plane *plane;
2139         int ret, i;
2140
2141         ret = pm_runtime_get_sync(dev->dev);
2142         if (ret < 0 && ret != -EACCES)
2143                 return ret;
2144
2145         ret = drm_atomic_helper_setup_commit(state, nonblock);
2146         if (ret)
2147                 goto done;
2148
2149         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2150
2151         ret = drm_atomic_helper_prepare_planes(dev, state);
2152         if (ret)
2153                 goto done;
2154
2155         if (!nonblock) {
2156                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2157                 if (ret)
2158                         goto err_cleanup;
2159         }
2160
2161         ret = drm_atomic_helper_swap_state(state, true);
2162         if (ret)
2163                 goto err_cleanup;
2164
2165         for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2166                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2167                 struct nv50_wndw *wndw = nv50_wndw(plane);
2168
2169                 if (asyw->set.image)
2170                         nv50_wndw_ntfy_enable(wndw, asyw);
2171         }
2172
2173         drm_atomic_state_get(state);
2174
2175         /*
2176          * Grab another RPM ref for the commit tail, which will release the
2177          * ref when it's finished
2178          */
2179         pm_runtime_get_noresume(dev->dev);
2180
2181         if (nonblock)
2182                 queue_work(system_unbound_wq, &state->commit_work);
2183         else
2184                 nv50_disp_atomic_commit_tail(state);
2185
2186 err_cleanup:
2187         if (ret)
2188                 drm_atomic_helper_cleanup_planes(dev, state);
2189 done:
2190         pm_runtime_put_autosuspend(dev->dev);
2191         return ret;
2192 }
2193
2194 static struct nv50_outp_atom *
2195 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2196 {
2197         struct nv50_outp_atom *outp;
2198
2199         list_for_each_entry(outp, &atom->outp, head) {
2200                 if (outp->encoder == encoder)
2201                         return outp;
2202         }
2203
2204         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2205         if (!outp)
2206                 return ERR_PTR(-ENOMEM);
2207
2208         list_add(&outp->head, &atom->outp);
2209         outp->encoder = encoder;
2210         return outp;
2211 }
2212
2213 static int
2214 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2215                                 struct drm_connector_state *old_connector_state)
2216 {
2217         struct drm_encoder *encoder = old_connector_state->best_encoder;
2218         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2219         struct drm_crtc *crtc;
2220         struct nv50_outp_atom *outp;
2221
2222         if (!(crtc = old_connector_state->crtc))
2223                 return 0;
2224
2225         old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2226         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2227         if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2228                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2229                 if (IS_ERR(outp))
2230                         return PTR_ERR(outp);
2231
2232                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2233                         outp->flush_disable = true;
2234                         atom->flush_disable = true;
2235                 }
2236                 outp->clr.ctrl = true;
2237                 atom->lock_core = true;
2238         }
2239
2240         return 0;
2241 }
2242
2243 static int
2244 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2245                                 struct drm_connector_state *connector_state)
2246 {
2247         struct drm_encoder *encoder = connector_state->best_encoder;
2248         struct drm_crtc_state *new_crtc_state;
2249         struct drm_crtc *crtc;
2250         struct nv50_outp_atom *outp;
2251
2252         if (!(crtc = connector_state->crtc))
2253                 return 0;
2254
2255         new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2256         if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2257                 outp = nv50_disp_outp_atomic_add(atom, encoder);
2258                 if (IS_ERR(outp))
2259                         return PTR_ERR(outp);
2260
2261                 outp->set.ctrl = true;
2262                 atom->lock_core = true;
2263         }
2264
2265         return 0;
2266 }
2267
2268 static int
2269 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2270 {
2271         struct nv50_atom *atom = nv50_atom(state);
2272         struct nv50_core *core = nv50_disp(dev)->core;
2273         struct drm_connector_state *old_connector_state, *new_connector_state;
2274         struct drm_connector *connector;
2275         struct drm_crtc_state *new_crtc_state;
2276         struct drm_crtc *crtc;
2277         struct nv50_head *head;
2278         struct nv50_head_atom *asyh;
2279         int ret, i;
2280
2281         if (core->assign_windows && core->func->head->static_wndw_map) {
2282                 drm_for_each_crtc(crtc, dev) {
2283                         new_crtc_state = drm_atomic_get_crtc_state(state,
2284                                                                    crtc);
2285                         if (IS_ERR(new_crtc_state))
2286                                 return PTR_ERR(new_crtc_state);
2287
2288                         head = nv50_head(crtc);
2289                         asyh = nv50_head_atom(new_crtc_state);
2290                         core->func->head->static_wndw_map(head, asyh);
2291                 }
2292         }
2293
2294         /* We need to handle colour management on a per-plane basis. */
2295         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2296                 if (new_crtc_state->color_mgmt_changed) {
2297                         ret = drm_atomic_add_affected_planes(state, crtc);
2298                         if (ret)
2299                                 return ret;
2300                 }
2301         }
2302
2303         ret = drm_atomic_helper_check(dev, state);
2304         if (ret)
2305                 return ret;
2306
2307         for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2308                 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2309                 if (ret)
2310                         return ret;
2311
2312                 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2313                 if (ret)
2314                         return ret;
2315         }
2316
2317         ret = drm_dp_mst_atomic_check(state);
2318         if (ret)
2319                 return ret;
2320
2321         return 0;
2322 }
2323
2324 static void
2325 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2326 {
2327         struct nv50_atom *atom = nv50_atom(state);
2328         struct nv50_outp_atom *outp, *outt;
2329
2330         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2331                 list_del(&outp->head);
2332                 kfree(outp);
2333         }
2334
2335         drm_atomic_state_default_clear(state);
2336 }
2337
2338 static void
2339 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2340 {
2341         struct nv50_atom *atom = nv50_atom(state);
2342         drm_atomic_state_default_release(&atom->state);
2343         kfree(atom);
2344 }
2345
2346 static struct drm_atomic_state *
2347 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2348 {
2349         struct nv50_atom *atom;
2350         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2351             drm_atomic_state_init(dev, &atom->state) < 0) {
2352                 kfree(atom);
2353                 return NULL;
2354         }
2355         INIT_LIST_HEAD(&atom->outp);
2356         return &atom->state;
2357 }
2358
2359 static const struct drm_mode_config_funcs
2360 nv50_disp_func = {
2361         .fb_create = nouveau_user_framebuffer_create,
2362         .output_poll_changed = nouveau_fbcon_output_poll_changed,
2363         .atomic_check = nv50_disp_atomic_check,
2364         .atomic_commit = nv50_disp_atomic_commit,
2365         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2366         .atomic_state_clear = nv50_disp_atomic_state_clear,
2367         .atomic_state_free = nv50_disp_atomic_state_free,
2368 };
2369
2370 /******************************************************************************
2371  * Init
2372  *****************************************************************************/
2373
2374 static void
2375 nv50_display_fini(struct drm_device *dev, bool suspend)
2376 {
2377         struct nouveau_encoder *nv_encoder;
2378         struct drm_encoder *encoder;
2379         struct drm_plane *plane;
2380
2381         drm_for_each_plane(plane, dev) {
2382                 struct nv50_wndw *wndw = nv50_wndw(plane);
2383                 if (plane->funcs != &nv50_wndw)
2384                         continue;
2385                 nv50_wndw_fini(wndw);
2386         }
2387
2388         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2389                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2390                         nv_encoder = nouveau_encoder(encoder);
2391                         nv50_mstm_fini(nv_encoder->dp.mstm);
2392                 }
2393         }
2394 }
2395
2396 static int
2397 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2398 {
2399         struct nv50_core *core = nv50_disp(dev)->core;
2400         struct drm_encoder *encoder;
2401         struct drm_plane *plane;
2402
2403         if (resume || runtime)
2404                 core->func->init(core);
2405
2406         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2407                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2408                         struct nouveau_encoder *nv_encoder =
2409                                 nouveau_encoder(encoder);
2410                         nv50_mstm_init(nv_encoder->dp.mstm, runtime);
2411                 }
2412         }
2413
2414         drm_for_each_plane(plane, dev) {
2415                 struct nv50_wndw *wndw = nv50_wndw(plane);
2416                 if (plane->funcs != &nv50_wndw)
2417                         continue;
2418                 nv50_wndw_init(wndw);
2419         }
2420
2421         return 0;
2422 }
2423
2424 static void
2425 nv50_display_destroy(struct drm_device *dev)
2426 {
2427         struct nv50_disp *disp = nv50_disp(dev);
2428
2429         nv50_audio_component_fini(nouveau_drm(dev));
2430
2431         nvif_object_unmap(&disp->caps);
2432         nvif_object_fini(&disp->caps);
2433         nv50_core_del(&disp->core);
2434
2435         nouveau_bo_unmap(disp->sync);
2436         if (disp->sync)
2437                 nouveau_bo_unpin(disp->sync);
2438         nouveau_bo_ref(NULL, &disp->sync);
2439
2440         nouveau_display(dev)->priv = NULL;
2441         kfree(disp);
2442 }
2443
2444 int
2445 nv50_display_create(struct drm_device *dev)
2446 {
2447         struct nvif_device *device = &nouveau_drm(dev)->client.device;
2448         struct nouveau_drm *drm = nouveau_drm(dev);
2449         struct dcb_table *dcb = &drm->vbios.dcb;
2450         struct drm_connector *connector, *tmp;
2451         struct nv50_disp *disp;
2452         struct dcb_output *dcbe;
2453         int crtcs, ret, i;
2454         bool has_mst = nv50_has_mst(drm);
2455
2456         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2457         if (!disp)
2458                 return -ENOMEM;
2459
2460         mutex_init(&disp->mutex);
2461
2462         nouveau_display(dev)->priv = disp;
2463         nouveau_display(dev)->dtor = nv50_display_destroy;
2464         nouveau_display(dev)->init = nv50_display_init;
2465         nouveau_display(dev)->fini = nv50_display_fini;
2466         disp->disp = &nouveau_display(dev)->disp;
2467         dev->mode_config.funcs = &nv50_disp_func;
2468         dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2469         dev->mode_config.normalize_zpos = true;
2470
2471         /* small shared memory area we use for notifiers and semaphores */
2472         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2473                              0, 0x0000, NULL, NULL, &disp->sync);
2474         if (!ret) {
2475                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2476                 if (!ret) {
2477                         ret = nouveau_bo_map(disp->sync);
2478                         if (ret)
2479                                 nouveau_bo_unpin(disp->sync);
2480                 }
2481                 if (ret)
2482                         nouveau_bo_ref(NULL, &disp->sync);
2483         }
2484
2485         if (ret)
2486                 goto out;
2487
2488         /* allocate master evo channel */
2489         ret = nv50_core_new(drm, &disp->core);
2490         if (ret)
2491                 goto out;
2492
2493         disp->core->func->init(disp->core);
2494         if (disp->core->func->caps_init) {
2495                 ret = disp->core->func->caps_init(drm, disp);
2496                 if (ret)
2497                         goto out;
2498         }
2499
2500         /* Assign the correct format modifiers */
2501         if (disp->disp->object.oclass >= TU102_DISP)
2502                 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2503         else
2504         if (disp->disp->object.oclass >= GF110_DISP)
2505                 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2506         else
2507                 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2508
2509         /* create crtc objects to represent the hw heads */
2510         if (disp->disp->object.oclass >= GV100_DISP)
2511                 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2512         else
2513         if (disp->disp->object.oclass >= GF110_DISP)
2514                 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2515         else
2516                 crtcs = 0x3;
2517
2518         for (i = 0; i < fls(crtcs); i++) {
2519                 struct nv50_head *head;
2520
2521                 if (!(crtcs & (1 << i)))
2522                         continue;
2523
2524                 head = nv50_head_create(dev, i);
2525                 if (IS_ERR(head)) {
2526                         ret = PTR_ERR(head);
2527                         goto out;
2528                 }
2529
2530                 if (has_mst) {
2531                         head->msto = nv50_msto_new(dev, head, i);
2532                         if (IS_ERR(head->msto)) {
2533                                 ret = PTR_ERR(head->msto);
2534                                 head->msto = NULL;
2535                                 goto out;
2536                         }
2537
2538                         /*
2539                          * FIXME: This is a hack to workaround the following
2540                          * issues:
2541                          *
2542                          * https://gitlab.gnome.org/GNOME/mutter/issues/759
2543                          * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
2544                          *
2545                          * Once these issues are closed, this should be
2546                          * removed
2547                          */
2548                         head->msto->encoder.possible_crtcs = crtcs;
2549                 }
2550         }
2551
2552         /* create encoder/connector objects based on VBIOS DCB table */
2553         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2554                 connector = nouveau_connector_create(dev, dcbe);
2555                 if (IS_ERR(connector))
2556                         continue;
2557
2558                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2559                         switch (dcbe->type) {
2560                         case DCB_OUTPUT_TMDS:
2561                         case DCB_OUTPUT_LVDS:
2562                         case DCB_OUTPUT_DP:
2563                                 ret = nv50_sor_create(connector, dcbe);
2564                                 break;
2565                         case DCB_OUTPUT_ANALOG:
2566                                 ret = nv50_dac_create(connector, dcbe);
2567                                 break;
2568                         default:
2569                                 ret = -ENODEV;
2570                                 break;
2571                         }
2572                 } else {
2573                         ret = nv50_pior_create(connector, dcbe);
2574                 }
2575
2576                 if (ret) {
2577                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2578                                      dcbe->location, dcbe->type,
2579                                      ffs(dcbe->or) - 1, ret);
2580                         ret = 0;
2581                 }
2582         }
2583
2584         /* cull any connectors we created that don't have an encoder */
2585         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2586                 if (connector->possible_encoders)
2587                         continue;
2588
2589                 NV_WARN(drm, "%s has no encoders, removing\n",
2590                         connector->name);
2591                 connector->funcs->destroy(connector);
2592         }
2593
2594         /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2595         dev->vblank_disable_immediate = true;
2596
2597         nv50_audio_component_init(drm);
2598
2599 out:
2600         if (ret)
2601                 nv50_display_destroy(dev);
2602         return ret;
2603 }
2604
2605 /******************************************************************************
2606  * Format modifiers
2607  *****************************************************************************/
2608
2609 /****************************************************************
2610  *            Log2(block height) ----------------------------+  *
2611  *            Page Kind ----------------------------------+  |  *
2612  *            Gob Height/Page Kind Generation ------+     |  |  *
2613  *                          Sector layout -------+  |     |  |  *
2614  *                          Compression ------+  |  |     |  |  */
2615 const u64 disp50xx_modifiers[] = { /*         |  |  |     |  |  */
2616         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0),
2617         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1),
2618         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2),
2619         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3),
2620         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4),
2621         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5),
2622         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0),
2623         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1),
2624         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2),
2625         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3),
2626         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4),
2627         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5),
2628         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0),
2629         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1),
2630         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2),
2631         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3),
2632         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4),
2633         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5),
2634         DRM_FORMAT_MOD_LINEAR,
2635         DRM_FORMAT_MOD_INVALID
2636 };
2637
2638 /****************************************************************
2639  *            Log2(block height) ----------------------------+  *
2640  *            Page Kind ----------------------------------+  |  *
2641  *            Gob Height/Page Kind Generation ------+     |  |  *
2642  *                          Sector layout -------+  |     |  |  *
2643  *                          Compression ------+  |  |     |  |  */
2644 const u64 disp90xx_modifiers[] = { /*         |  |  |     |  |  */
2645         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0),
2646         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1),
2647         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2),
2648         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3),
2649         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4),
2650         DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5),
2651         DRM_FORMAT_MOD_LINEAR,
2652         DRM_FORMAT_MOD_INVALID
2653 };