2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/option.h>
27 #include <subdev/clock.h>
28 #include <subdev/therm.h>
29 #include <subdev/volt.h>
30 #include <subdev/fb.h>
32 #include <subdev/bios.h>
33 #include <subdev/bios/boost.h>
34 #include <subdev/bios/cstep.h>
35 #include <subdev/bios/perf.h>
37 /******************************************************************************
39 *****************************************************************************/
41 nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
42 u8 pstate, u8 domain, u32 input)
44 struct nouveau_bios *bios = nouveau_bios(clk);
45 struct nvbios_boostE boostE;
46 u8 ver, hdr, cnt, len;
49 data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
51 struct nvbios_boostS boostS;
52 u8 idx = 0, sver, shdr;
55 input = max(boostE.min, input);
56 input = min(boostE.max, input);
60 subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
62 if (subd && boostS.domain == domain) {
64 input = input * boostS.percent / 100;
65 input = max(boostS.min, input);
66 input = min(boostS.max, input);
75 /******************************************************************************
77 *****************************************************************************/
79 nouveau_cstate_prog(struct nouveau_clock *clk,
80 struct nouveau_pstate *pstate, int cstatei)
82 struct nouveau_therm *ptherm = nouveau_therm(clk);
83 struct nouveau_volt *volt = nouveau_volt(clk);
84 struct nouveau_cstate *cstate;
87 if (!list_empty(&pstate->list)) {
88 cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
90 cstate = &pstate->base;
94 ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
95 if (ret && ret != -ENODEV) {
96 nv_error(clk, "failed to raise fan speed: %d\n", ret);
102 ret = volt->set_id(volt, cstate->voltage, +1);
103 if (ret && ret != -ENODEV) {
104 nv_error(clk, "failed to raise voltage: %d\n", ret);
109 ret = clk->calc(clk, cstate);
111 ret = clk->prog(clk);
116 ret = volt->set_id(volt, cstate->voltage, -1);
117 if (ret && ret != -ENODEV)
118 nv_error(clk, "failed to lower voltage: %d\n", ret);
122 ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
123 if (ret && ret != -ENODEV)
124 nv_error(clk, "failed to lower fan speed: %d\n", ret);
131 nouveau_cstate_del(struct nouveau_cstate *cstate)
133 list_del(&cstate->head);
138 nouveau_cstate_new(struct nouveau_clock *clk, int idx,
139 struct nouveau_pstate *pstate)
141 struct nouveau_bios *bios = nouveau_bios(clk);
142 struct nouveau_clocks *domain = clk->domains;
143 struct nouveau_cstate *cstate = NULL;
144 struct nvbios_cstepX cstepX;
148 data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
152 cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
156 *cstate = pstate->base;
157 cstate->voltage = cstepX.voltage;
159 while (domain && domain->name != nv_clk_src_max) {
160 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
161 u32 freq = nouveau_clock_adjust(clk, true,
165 cstate->domain[domain->name] = freq;
170 list_add(&cstate->head, &pstate->list);
174 /******************************************************************************
176 *****************************************************************************/
178 nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
180 struct nouveau_fb *pfb = nouveau_fb(clk);
181 struct nouveau_pstate *pstate;
184 list_for_each_entry(pstate, &clk->states, head) {
185 if (idx++ == pstatei)
189 nv_debug(clk, "setting performance state %d\n", pstatei);
190 clk->pstate = pstatei;
192 if (pfb->ram->calc) {
193 int khz = pstate->base.domain[nv_clk_src_mem];
195 ret = pfb->ram->calc(pfb, khz);
197 ret = pfb->ram->prog(pfb);
202 return nouveau_cstate_prog(clk, pstate, 0);
206 nouveau_pstate_work(struct work_struct *work)
208 struct nouveau_clock *clk = container_of(work, typeof(*clk), work);
211 if (!atomic_xchg(&clk->waiting, 0))
213 clk->pwrsrc = power_supply_is_system_supplied();
215 nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
216 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
217 clk->astate, clk->tstate, clk->dstate);
219 pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
220 if (clk->state_nr && pstate != -1) {
221 pstate = (pstate < 0) ? clk->astate : pstate;
222 pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
223 pstate = max(pstate, clk->dstate);
225 pstate = clk->pstate = -1;
228 nv_trace(clk, "-> %d\n", pstate);
229 if (pstate != clk->pstate) {
230 int ret = nouveau_pstate_prog(clk, pstate);
232 nv_error(clk, "error setting pstate %d: %d\n",
237 wake_up_all(&clk->wait);
238 nouveau_event_get(clk->pwrsrc_ntfy);
242 nouveau_pstate_calc(struct nouveau_clock *clk, bool wait)
244 atomic_set(&clk->waiting, 1);
245 schedule_work(&clk->work);
247 wait_event(clk->wait, !atomic_read(&clk->waiting));
252 nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
254 struct nouveau_clocks *clock = clk->domains - 1;
255 struct nouveau_cstate *cstate;
256 char info[3][32] = { "", "", "" };
260 if (pstate->pstate != 0xff)
261 snprintf(name, sizeof(name), "%02x", pstate->pstate);
263 while ((++clock)->name != nv_clk_src_max) {
264 u32 lo = pstate->base.domain[clock->name];
269 nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
270 list_for_each_entry(cstate, &pstate->list, head) {
271 u32 freq = cstate->domain[clock->name];
274 nv_debug(clk, "%10d KHz\n", freq);
277 if (clock->mname && ++i < ARRAY_SIZE(info)) {
281 snprintf(info[i], sizeof(info[i]), "%s %d MHz",
284 snprintf(info[i], sizeof(info[i]),
285 "%s %d-%d MHz", clock->mname, lo, hi);
290 nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
294 nouveau_pstate_del(struct nouveau_pstate *pstate)
296 struct nouveau_cstate *cstate, *temp;
298 list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
299 nouveau_cstate_del(cstate);
302 list_del(&pstate->head);
307 nouveau_pstate_new(struct nouveau_clock *clk, int idx)
309 struct nouveau_bios *bios = nouveau_bios(clk);
310 struct nouveau_clocks *domain = clk->domains - 1;
311 struct nouveau_pstate *pstate;
312 struct nouveau_cstate *cstate;
313 struct nvbios_cstepE cstepE;
314 struct nvbios_perfE perfE;
315 u8 ver, hdr, cnt, len;
318 data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
321 if (perfE.pstate == 0xff)
324 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
325 cstate = &pstate->base;
329 INIT_LIST_HEAD(&pstate->list);
331 pstate->pstate = perfE.pstate;
332 pstate->fanspeed = perfE.fanspeed;
333 cstate->voltage = perfE.voltage;
334 cstate->domain[nv_clk_src_core] = perfE.core;
335 cstate->domain[nv_clk_src_shader] = perfE.shader;
336 cstate->domain[nv_clk_src_mem] = perfE.memory;
337 cstate->domain[nv_clk_src_vdec] = perfE.vdec;
338 cstate->domain[nv_clk_src_dom6] = perfE.disp;
340 while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
341 struct nvbios_perfS perfS;
342 u8 sver = ver, shdr = hdr;
343 u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
344 &sver, &shdr, cnt, len, &perfS);
345 if (perfSe == 0 || sver != 0x40)
348 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
349 perfS.v40.freq = nouveau_clock_adjust(clk, false,
355 cstate->domain[domain->name] = perfS.v40.freq;
358 data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
360 int idx = cstepE.index;
362 nouveau_cstate_new(clk, idx, pstate);
366 nouveau_pstate_info(clk, pstate);
367 list_add_tail(&pstate->head, &clk->states);
372 /******************************************************************************
373 * Adjustment triggers
374 *****************************************************************************/
376 nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
378 struct nouveau_pstate *pstate;
381 if (!clk->allow_reclock)
384 if (req != -1 && req != -2) {
385 list_for_each_entry(pstate, &clk->states, head) {
386 if (pstate->pstate == req)
391 if (pstate->pstate != req)
400 nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
404 if (strncasecmpz(mode, "disabled", arglen)) {
405 char save = mode[arglen];
408 ((char *)mode)[arglen] = '\0';
409 if (!kstrtol(mode, 0, &v)) {
410 ret = nouveau_clock_ustate_update(clk, v);
414 ((char *)mode)[arglen] = save;
421 nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
423 int ret = nouveau_clock_ustate_update(clk, req);
425 if (ret -= 2, pwr) clk->ustate_ac = ret;
426 else clk->ustate_dc = ret;
427 return nouveau_pstate_calc(clk, true);
433 nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
435 if (!rel) clk->astate = req;
436 if ( rel) clk->astate += rel;
437 clk->astate = min(clk->astate, clk->state_nr - 1);
438 clk->astate = max(clk->astate, 0);
439 return nouveau_pstate_calc(clk, true);
443 nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
445 if (!rel) clk->tstate = req;
446 if ( rel) clk->tstate += rel;
447 clk->tstate = min(clk->tstate, 0);
448 clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
449 return nouveau_pstate_calc(clk, true);
453 nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
455 if (!rel) clk->dstate = req;
456 if ( rel) clk->dstate += rel;
457 clk->dstate = min(clk->dstate, clk->state_nr - 1);
458 clk->dstate = max(clk->dstate, 0);
459 return nouveau_pstate_calc(clk, true);
463 nouveau_clock_pwrsrc(void *data, u32 mask, int type)
465 struct nouveau_clock *clk = data;
466 nouveau_pstate_calc(clk, false);
467 return NVKM_EVENT_DROP;
470 /******************************************************************************
471 * subdev base class implementation
472 *****************************************************************************/
475 _nouveau_clock_fini(struct nouveau_object *object, bool suspend)
477 struct nouveau_clock *clk = (void *)object;
478 nouveau_event_put(clk->pwrsrc_ntfy);
479 return nouveau_subdev_fini(&clk->base, suspend);
483 _nouveau_clock_init(struct nouveau_object *object)
485 struct nouveau_clock *clk = (void *)object;
486 struct nouveau_clocks *clock = clk->domains;
489 ret = nouveau_subdev_init(&clk->base);
493 memset(&clk->bstate, 0x00, sizeof(clk->bstate));
494 INIT_LIST_HEAD(&clk->bstate.list);
495 clk->bstate.pstate = 0xff;
497 while (clock->name != nv_clk_src_max) {
498 ret = clk->read(clk, clock->name);
500 nv_error(clk, "%02x freq unknown\n", clock->name);
503 clk->bstate.base.domain[clock->name] = ret;
507 nouveau_pstate_info(clk, &clk->bstate);
509 clk->astate = clk->state_nr - 1;
513 nouveau_pstate_calc(clk, true);
518 _nouveau_clock_dtor(struct nouveau_object *object)
520 struct nouveau_clock *clk = (void *)object;
521 struct nouveau_pstate *pstate, *temp;
523 nouveau_event_ref(NULL, &clk->pwrsrc_ntfy);
525 list_for_each_entry_safe(pstate, temp, &clk->states, head) {
526 nouveau_pstate_del(pstate);
529 nouveau_subdev_destroy(&clk->base);
533 nouveau_clock_create_(struct nouveau_object *parent,
534 struct nouveau_object *engine,
535 struct nouveau_oclass *oclass,
536 struct nouveau_clocks *clocks,
537 struct nouveau_pstate *pstates, int nb_pstates,
539 int length, void **object)
541 struct nouveau_device *device = nv_device(parent);
542 struct nouveau_clock *clk;
543 int ret, idx, arglen;
546 ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
547 "clock", length, object);
552 INIT_LIST_HEAD(&clk->states);
553 clk->domains = clocks;
557 INIT_WORK(&clk->work, nouveau_pstate_work);
558 init_waitqueue_head(&clk->wait);
559 atomic_set(&clk->waiting, 0);
561 /* If no pstates are provided, try and fetch them from the BIOS */
565 ret = nouveau_pstate_new(clk, idx++);
568 for (idx = 0; idx < nb_pstates; idx++)
569 list_add_tail(&pstates[idx].head, &clk->states);
570 clk->state_nr = nb_pstates;
573 clk->allow_reclock = allow_reclock;
575 ret = nouveau_event_new(device->ntfy, 1, NVKM_DEVICE_NTFY_POWER,
576 nouveau_clock_pwrsrc, clk,
581 mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
583 clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
584 clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
587 mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
589 clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
591 mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
593 clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);