1 #include <core/engine.h>
2 #include <core/device.h>
4 #include <subdev/bios.h>
5 #include <subdev/bios/bmp.h>
6 #include <subdev/bios/bit.h>
7 #include <subdev/bios/conn.h>
8 #include <subdev/bios/dcb.h>
9 #include <subdev/bios/dp.h>
10 #include <subdev/bios/gpio.h>
11 #include <subdev/bios/init.h>
12 #include <subdev/devinit.h>
13 #include <subdev/clock.h>
14 #include <subdev/i2c.h>
15 #include <subdev/vga.h>
16 #include <subdev/gpio.h>
18 #define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
22 #define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
26 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
30 /******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
35 init_exec(struct nvbios_init *init)
37 return (init->execute == 1) || ((init->execute & 5) == 5);
41 init_exec_set(struct nvbios_init *init, bool exec)
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
48 init_exec_inv(struct nvbios_init *init)
50 init->execute ^= 0x02;
54 init_exec_force(struct nvbios_init *init, bool exec)
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
60 /******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
65 init_or(struct nvbios_init *init)
67 if (init_exec(init)) {
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
76 init_link(struct nvbios_init *init)
78 if (init_exec(init)) {
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
87 init_crtc(struct nvbios_init *init)
89 if (init_exec(init)) {
92 error("script needs crtc\n");
98 init_conn(struct nvbios_init *init)
100 struct nouveau_bios *bios = init->bios;
104 if (init_exec(init)) {
106 conn = init->outp->connector;
107 conn = dcb_conn(bios, conn, &ver, &len);
109 return nv_ro08(bios, conn);
112 error("script needs connector type\n");
119 init_nvreg(struct nvbios_init *init, u32 reg)
121 /* C51 (at least) sometimes has the lower bits set which the VBIOS
122 * interprets to mean that access needs to go through certain IO
123 * ports instead. The NVIDIA binary driver has been seen to access
124 * these through the NV register address, so lets assume we can
129 /* GF8+ display scripts need register addresses mangled a bit to
130 * select a specific CRTC/OR
132 if (nv_device(init->bios)->card_type >= NV_50) {
133 if (reg & 0x80000000) {
134 reg += init_crtc(init) * 0x800;
138 if (reg & 0x40000000) {
139 reg += init_or(init) * 0x800;
141 if (reg & 0x20000000) {
142 reg += init_link(init) * 0x80;
148 if (reg & ~0x00fffffc)
149 warn("unknown bits in register 0x%08x\n", reg);
154 init_rd32(struct nvbios_init *init, u32 reg)
156 reg = init_nvreg(init, reg);
158 return nv_rd32(init->subdev, reg);
163 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
165 reg = init_nvreg(init, reg);
167 nv_wr32(init->subdev, reg, val);
171 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
173 reg = init_nvreg(init, reg);
174 if (init_exec(init)) {
175 u32 tmp = nv_rd32(init->subdev, reg);
176 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
183 init_rdport(struct nvbios_init *init, u16 port)
186 return nv_rdport(init->subdev, init->crtc, port);
191 init_wrport(struct nvbios_init *init, u16 port, u8 value)
194 nv_wrport(init->subdev, init->crtc, port, value);
198 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
200 struct nouveau_subdev *subdev = init->subdev;
201 if (init_exec(init)) {
202 int head = init->crtc < 0 ? 0 : init->crtc;
203 return nv_rdvgai(subdev, head, port, index);
209 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
211 /* force head 0 for updates to cr44, it only exists on first head */
212 if (nv_device(init->subdev)->card_type < NV_50) {
213 if (port == 0x03d4 && index == 0x44)
217 if (init_exec(init)) {
218 int head = init->crtc < 0 ? 0 : init->crtc;
219 nv_wrvgai(init->subdev, head, port, index, value);
222 /* select head 1 if cr44 write selected it */
223 if (nv_device(init->subdev)->card_type < NV_50) {
224 if (port == 0x03d4 && index == 0x44 && value == 3)
229 static struct nouveau_i2c_port *
230 init_i2c(struct nvbios_init *init, int index)
232 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
235 index = NV_I2C_DEFAULT(0);
236 if (init->outp && init->outp->i2c_upper_default)
237 index = NV_I2C_DEFAULT(1);
242 error("script needs output for i2c\n");
246 if (index == -2 && init->outp->location) {
247 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
248 return i2c->find_type(i2c, index);
251 index = init->outp->i2c_index;
254 return i2c->find(i2c, index);
258 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
260 struct nouveau_i2c_port *port = init_i2c(init, index);
261 if (port && init_exec(init))
262 return nv_rdi2cr(port, addr, reg);
267 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
269 struct nouveau_i2c_port *port = init_i2c(init, index);
270 if (port && init_exec(init))
271 return nv_wri2cr(port, addr, reg, val);
276 init_rdauxr(struct nvbios_init *init, u32 addr)
278 struct nouveau_i2c_port *port = init_i2c(init, -2);
281 if (port && init_exec(init)) {
282 int ret = nv_rdaux(port, addr, &data, 1);
292 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
294 struct nouveau_i2c_port *port = init_i2c(init, -2);
295 if (port && init_exec(init))
296 return nv_wraux(port, addr, &data, 1);
301 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
303 struct nouveau_clock *clk = nouveau_clock(init->bios);
304 if (clk && clk->pll_set && init_exec(init)) {
305 int ret = clk->pll_set(clk, id, freq);
307 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
311 /******************************************************************************
312 * parsing of bios structures that are required to execute init tables
313 *****************************************************************************/
316 init_table(struct nouveau_bios *bios, u16 *len)
318 struct bit_entry bit_I;
320 if (!bit_entry(bios, 'I', &bit_I)) {
325 if (bmp_version(bios) >= 0x0510) {
327 return bios->bmp_offset + 75;
334 init_table_(struct nvbios_init *init, u16 offset, const char *name)
336 struct nouveau_bios *bios = init->bios;
337 u16 len, data = init_table(bios, &len);
339 if (len >= offset + 2) {
340 data = nv_ro16(bios, data + offset);
344 warn("%s pointer invalid\n", name);
348 warn("init data too short for %s pointer", name);
352 warn("init data not found\n");
356 #define init_script_table(b) init_table_((b), 0x00, "script table")
357 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
358 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
359 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
360 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
361 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
362 #define init_function_table(b) init_table_((b), 0x0c, "function table")
363 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
366 init_script(struct nouveau_bios *bios, int index)
368 struct nvbios_init init = { .bios = bios };
371 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
375 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
376 return nv_ro16(bios, data + (index * 2));
379 data = init_script_table(&init);
381 return nv_ro16(bios, data + (index * 2));
387 init_unknown_script(struct nouveau_bios *bios)
389 u16 len, data = init_table(bios, &len);
390 if (data && len >= 16)
391 return nv_ro16(bios, data + 14);
396 init_ram_restrict_table(struct nvbios_init *init)
398 struct nouveau_bios *bios = init->bios;
399 struct bit_entry bit_M;
402 if (!bit_entry(bios, 'M', &bit_M)) {
403 if (bit_M.version == 1 && bit_M.length >= 5)
404 data = nv_ro16(bios, bit_M.offset + 3);
405 if (bit_M.version == 2 && bit_M.length >= 3)
406 data = nv_ro16(bios, bit_M.offset + 1);
410 warn("ram restrict table not found\n");
415 init_ram_restrict_group_count(struct nvbios_init *init)
417 struct nouveau_bios *bios = init->bios;
418 struct bit_entry bit_M;
420 if (!bit_entry(bios, 'M', &bit_M)) {
421 if (bit_M.version == 1 && bit_M.length >= 5)
422 return nv_ro08(bios, bit_M.offset + 2);
423 if (bit_M.version == 2 && bit_M.length >= 3)
424 return nv_ro08(bios, bit_M.offset + 0);
431 init_ram_restrict_strap(struct nvbios_init *init)
433 /* This appears to be the behaviour of the VBIOS parser, and *is*
434 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
435 * avoid fucking up the memory controller (somehow) by reading it
436 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
438 * Preserving the non-caching behaviour on earlier chipsets just
439 * in case *not* re-reading the strap causes similar breakage.
441 if (!init->ramcfg || init->bios->version.major < 0x70)
442 init->ramcfg = init_rd32(init, 0x101000);
443 return (init->ramcfg & 0x00000003c) >> 2;
447 init_ram_restrict(struct nvbios_init *init)
449 u8 strap = init_ram_restrict_strap(init);
450 u16 table = init_ram_restrict_table(init);
452 return nv_ro08(init->bios, table + strap);
457 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_xlat_table(init);
462 u16 data = nv_ro16(bios, table + (index * 2));
464 return nv_ro08(bios, data + offset);
465 warn("xlat table pointer %d invalid\n", index);
470 /******************************************************************************
471 * utility functions used by various init opcode handlers
472 *****************************************************************************/
475 init_condition_met(struct nvbios_init *init, u8 cond)
477 struct nouveau_bios *bios = init->bios;
478 u16 table = init_condition_table(init);
480 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
481 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
482 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
483 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
484 cond, reg, msk, val);
485 return (init_rd32(init, reg) & msk) == val;
491 init_io_condition_met(struct nvbios_init *init, u8 cond)
493 struct nouveau_bios *bios = init->bios;
494 u16 table = init_io_condition_table(init);
496 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
497 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
498 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
499 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
500 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
501 cond, port, index, mask, value);
502 return (init_rdvgai(init, port, index) & mask) == value;
508 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
510 struct nouveau_bios *bios = init->bios;
511 u16 table = init_io_flag_condition_table(init);
513 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
514 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
515 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
516 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
517 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
518 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
519 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
520 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
521 return (nv_ro08(bios, data + ioval) & dmask) == value;
527 init_shift(u32 data, u8 shift)
530 return data >> shift;
531 return data << (0x100 - shift);
535 init_tmds_reg(struct nvbios_init *init, u8 tmds)
537 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
538 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
539 * CR58 for CR57 = 0 to index a table of offsets to the basic
541 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
542 * CR58 for CR57 = 0 to index a table of offsets to the basic
543 * 0x6808b0 address, and then flip the offset by 8.
546 const int pramdac_offset[13] = {
547 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
548 const u32 pramdac_table[4] = {
549 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
553 u32 dacoffset = pramdac_offset[init->outp->or];
556 return 0x6808b0 + dacoffset;
560 error("tmds opcodes need dcb\n");
562 if (tmds < ARRAY_SIZE(pramdac_table))
563 return pramdac_table[tmds];
565 error("tmds selector 0x%02x unknown\n", tmds);
571 /******************************************************************************
572 * init opcode handlers
573 *****************************************************************************/
576 * init_reserved - stub for various unknown/unused single-byte opcodes
580 init_reserved(struct nvbios_init *init)
582 u8 opcode = nv_ro08(init->bios, init->offset);
583 trace("RESERVED\t0x%02x\n", opcode);
588 * INIT_DONE - opcode 0x71
592 init_done(struct nvbios_init *init)
595 init->offset = 0x0000;
599 * INIT_IO_RESTRICT_PROG - opcode 0x32
603 init_io_restrict_prog(struct nvbios_init *init)
605 struct nouveau_bios *bios = init->bios;
606 u16 port = nv_ro16(bios, init->offset + 1);
607 u8 index = nv_ro08(bios, init->offset + 3);
608 u8 mask = nv_ro08(bios, init->offset + 4);
609 u8 shift = nv_ro08(bios, init->offset + 5);
610 u8 count = nv_ro08(bios, init->offset + 6);
611 u32 reg = nv_ro32(bios, init->offset + 7);
614 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
615 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
616 reg, port, index, mask, shift);
619 conf = (init_rdvgai(init, port, index) & mask) >> shift;
620 for (i = 0; i < count; i++) {
621 u32 data = nv_ro32(bios, init->offset);
624 trace("\t0x%08x *\n", data);
625 init_wr32(init, reg, data);
627 trace("\t0x%08x\n", data);
636 * INIT_REPEAT - opcode 0x33
640 init_repeat(struct nvbios_init *init)
642 struct nouveau_bios *bios = init->bios;
643 u8 count = nv_ro08(bios, init->offset + 1);
644 u16 repeat = init->repeat;
646 trace("REPEAT\t0x%02x\n", count);
649 init->repeat = init->offset;
650 init->repend = init->offset;
652 init->offset = init->repeat;
655 trace("REPEAT\t0x%02x\n", count);
657 init->offset = init->repend;
658 init->repeat = repeat;
662 * INIT_IO_RESTRICT_PLL - opcode 0x34
666 init_io_restrict_pll(struct nvbios_init *init)
668 struct nouveau_bios *bios = init->bios;
669 u16 port = nv_ro16(bios, init->offset + 1);
670 u8 index = nv_ro08(bios, init->offset + 3);
671 u8 mask = nv_ro08(bios, init->offset + 4);
672 u8 shift = nv_ro08(bios, init->offset + 5);
673 s8 iofc = nv_ro08(bios, init->offset + 6);
674 u8 count = nv_ro08(bios, init->offset + 7);
675 u32 reg = nv_ro32(bios, init->offset + 8);
678 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
679 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
680 reg, port, index, mask, shift, iofc);
683 conf = (init_rdvgai(init, port, index) & mask) >> shift;
684 for (i = 0; i < count; i++) {
685 u32 freq = nv_ro16(bios, init->offset) * 10;
688 trace("\t%dkHz *\n", freq);
689 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
691 init_prog_pll(init, reg, freq);
693 trace("\t%dkHz\n", freq);
702 * INIT_END_REPEAT - opcode 0x36
706 init_end_repeat(struct nvbios_init *init)
708 trace("END_REPEAT\n");
712 init->repend = init->offset;
718 * INIT_COPY - opcode 0x37
722 init_copy(struct nvbios_init *init)
724 struct nouveau_bios *bios = init->bios;
725 u32 reg = nv_ro32(bios, init->offset + 1);
726 u8 shift = nv_ro08(bios, init->offset + 5);
727 u8 smask = nv_ro08(bios, init->offset + 6);
728 u16 port = nv_ro16(bios, init->offset + 7);
729 u8 index = nv_ro08(bios, init->offset + 9);
730 u8 mask = nv_ro08(bios, init->offset + 10);
733 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
734 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
735 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
736 (shift & 0x80) ? (0x100 - shift) : shift, smask);
739 data = init_rdvgai(init, port, index) & mask;
740 data |= init_shift(init_rd32(init, reg), shift) & smask;
741 init_wrvgai(init, port, index, data);
745 * INIT_NOT - opcode 0x38
749 init_not(struct nvbios_init *init)
757 * INIT_IO_FLAG_CONDITION - opcode 0x39
761 init_io_flag_condition(struct nvbios_init *init)
763 struct nouveau_bios *bios = init->bios;
764 u8 cond = nv_ro08(bios, init->offset + 1);
766 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
769 if (!init_io_flag_condition_met(init, cond))
770 init_exec_set(init, false);
774 * INIT_DP_CONDITION - opcode 0x3a
778 init_dp_condition(struct nvbios_init *init)
780 struct nouveau_bios *bios = init->bios;
781 struct nvbios_dpout info;
782 u8 cond = nv_ro08(bios, init->offset + 1);
783 u8 unkn = nv_ro08(bios, init->offset + 2);
784 u8 ver, hdr, cnt, len;
787 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
792 if (init_conn(init) != DCB_CONNECTOR_eDP)
793 init_exec_set(init, false);
798 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
799 (init->outp->or << 0) |
800 (init->outp->sorconf.link << 6),
801 &ver, &hdr, &cnt, &len, &info)))
803 if (!(info.flags & cond))
804 init_exec_set(init, false);
809 warn("script needs dp output table data\n");
812 if (!(init_rdauxr(init, 0x0d) & 1))
813 init_exec_set(init, false);
816 warn("unknown dp condition 0x%02x\n", cond);
822 * INIT_IO_MASK_OR - opcode 0x3b
826 init_io_mask_or(struct nvbios_init *init)
828 struct nouveau_bios *bios = init->bios;
829 u8 index = nv_ro08(bios, init->offset + 1);
830 u8 or = init_or(init);
833 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
836 data = init_rdvgai(init, 0x03d4, index);
837 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
841 * INIT_IO_OR - opcode 0x3c
845 init_io_or(struct nvbios_init *init)
847 struct nouveau_bios *bios = init->bios;
848 u8 index = nv_ro08(bios, init->offset + 1);
849 u8 or = init_or(init);
852 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
855 data = init_rdvgai(init, 0x03d4, index);
856 init_wrvgai(init, 0x03d4, index, data | (1 << or));
860 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
864 init_idx_addr_latched(struct nvbios_init *init)
866 struct nouveau_bios *bios = init->bios;
867 u32 creg = nv_ro32(bios, init->offset + 1);
868 u32 dreg = nv_ro32(bios, init->offset + 5);
869 u32 mask = nv_ro32(bios, init->offset + 9);
870 u32 data = nv_ro32(bios, init->offset + 13);
871 u8 count = nv_ro08(bios, init->offset + 17);
873 trace("INDEX_ADDRESS_LATCHED\t"
874 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
875 creg, dreg, mask, data);
879 u8 iaddr = nv_ro08(bios, init->offset + 0);
880 u8 idata = nv_ro08(bios, init->offset + 1);
882 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
885 init_wr32(init, dreg, idata);
886 init_mask(init, creg, ~mask, data | iaddr);
891 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
895 init_io_restrict_pll2(struct nvbios_init *init)
897 struct nouveau_bios *bios = init->bios;
898 u16 port = nv_ro16(bios, init->offset + 1);
899 u8 index = nv_ro08(bios, init->offset + 3);
900 u8 mask = nv_ro08(bios, init->offset + 4);
901 u8 shift = nv_ro08(bios, init->offset + 5);
902 u8 count = nv_ro08(bios, init->offset + 6);
903 u32 reg = nv_ro32(bios, init->offset + 7);
906 trace("IO_RESTRICT_PLL2\t"
907 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
908 reg, port, index, mask, shift);
911 conf = (init_rdvgai(init, port, index) & mask) >> shift;
912 for (i = 0; i < count; i++) {
913 u32 freq = nv_ro32(bios, init->offset);
915 trace("\t%dkHz *\n", freq);
916 init_prog_pll(init, reg, freq);
918 trace("\t%dkHz\n", freq);
926 * INIT_PLL2 - opcode 0x4b
930 init_pll2(struct nvbios_init *init)
932 struct nouveau_bios *bios = init->bios;
933 u32 reg = nv_ro32(bios, init->offset + 1);
934 u32 freq = nv_ro32(bios, init->offset + 5);
936 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
939 init_prog_pll(init, reg, freq);
943 * INIT_I2C_BYTE - opcode 0x4c
947 init_i2c_byte(struct nvbios_init *init)
949 struct nouveau_bios *bios = init->bios;
950 u8 index = nv_ro08(bios, init->offset + 1);
951 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
952 u8 count = nv_ro08(bios, init->offset + 3);
954 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
958 u8 reg = nv_ro08(bios, init->offset + 0);
959 u8 mask = nv_ro08(bios, init->offset + 1);
960 u8 data = nv_ro08(bios, init->offset + 2);
963 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
966 val = init_rdi2cr(init, index, addr, reg);
969 init_wri2cr(init, index, addr, reg, (val & mask) | data);
974 * INIT_ZM_I2C_BYTE - opcode 0x4d
978 init_zm_i2c_byte(struct nvbios_init *init)
980 struct nouveau_bios *bios = init->bios;
981 u8 index = nv_ro08(bios, init->offset + 1);
982 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
983 u8 count = nv_ro08(bios, init->offset + 3);
985 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
989 u8 reg = nv_ro08(bios, init->offset + 0);
990 u8 data = nv_ro08(bios, init->offset + 1);
992 trace("\t[0x%02x] = 0x%02x\n", reg, data);
995 init_wri2cr(init, index, addr, reg, data);
1001 * INIT_ZM_I2C - opcode 0x4e
1005 init_zm_i2c(struct nvbios_init *init)
1007 struct nouveau_bios *bios = init->bios;
1008 u8 index = nv_ro08(bios, init->offset + 1);
1009 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1010 u8 count = nv_ro08(bios, init->offset + 3);
1013 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1016 for (i = 0; i < count; i++) {
1017 data[i] = nv_ro08(bios, init->offset);
1018 trace("\t0x%02x\n", data[i]);
1022 if (init_exec(init)) {
1023 struct nouveau_i2c_port *port = init_i2c(init, index);
1024 struct i2c_msg msg = {
1025 .addr = addr, .flags = 0, .len = count, .buf = data,
1029 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1030 warn("i2c wr failed, %d\n", ret);
1035 * INIT_TMDS - opcode 0x4f
1039 init_tmds(struct nvbios_init *init)
1041 struct nouveau_bios *bios = init->bios;
1042 u8 tmds = nv_ro08(bios, init->offset + 1);
1043 u8 addr = nv_ro08(bios, init->offset + 2);
1044 u8 mask = nv_ro08(bios, init->offset + 3);
1045 u8 data = nv_ro08(bios, init->offset + 4);
1046 u32 reg = init_tmds_reg(init, tmds);
1048 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1049 tmds, addr, mask, data);
1055 init_wr32(init, reg + 0, addr | 0x00010000);
1056 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1057 init_wr32(init, reg + 0, addr);
1061 * INIT_ZM_TMDS_GROUP - opcode 0x50
1065 init_zm_tmds_group(struct nvbios_init *init)
1067 struct nouveau_bios *bios = init->bios;
1068 u8 tmds = nv_ro08(bios, init->offset + 1);
1069 u8 count = nv_ro08(bios, init->offset + 2);
1070 u32 reg = init_tmds_reg(init, tmds);
1072 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1076 u8 addr = nv_ro08(bios, init->offset + 0);
1077 u8 data = nv_ro08(bios, init->offset + 1);
1079 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1082 init_wr32(init, reg + 4, data);
1083 init_wr32(init, reg + 0, addr);
1088 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1092 init_cr_idx_adr_latch(struct nvbios_init *init)
1094 struct nouveau_bios *bios = init->bios;
1095 u8 addr0 = nv_ro08(bios, init->offset + 1);
1096 u8 addr1 = nv_ro08(bios, init->offset + 2);
1097 u8 base = nv_ro08(bios, init->offset + 3);
1098 u8 count = nv_ro08(bios, init->offset + 4);
1101 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1104 save0 = init_rdvgai(init, 0x03d4, addr0);
1106 u8 data = nv_ro08(bios, init->offset);
1108 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1111 init_wrvgai(init, 0x03d4, addr0, base++);
1112 init_wrvgai(init, 0x03d4, addr1, data);
1114 init_wrvgai(init, 0x03d4, addr0, save0);
1118 * INIT_CR - opcode 0x52
1122 init_cr(struct nvbios_init *init)
1124 struct nouveau_bios *bios = init->bios;
1125 u8 addr = nv_ro08(bios, init->offset + 1);
1126 u8 mask = nv_ro08(bios, init->offset + 2);
1127 u8 data = nv_ro08(bios, init->offset + 3);
1130 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1133 val = init_rdvgai(init, 0x03d4, addr) & mask;
1134 init_wrvgai(init, 0x03d4, addr, val | data);
1138 * INIT_ZM_CR - opcode 0x53
1142 init_zm_cr(struct nvbios_init *init)
1144 struct nouveau_bios *bios = init->bios;
1145 u8 addr = nv_ro08(bios, init->offset + 1);
1146 u8 data = nv_ro08(bios, init->offset + 2);
1148 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1151 init_wrvgai(init, 0x03d4, addr, data);
1155 * INIT_ZM_CR_GROUP - opcode 0x54
1159 init_zm_cr_group(struct nvbios_init *init)
1161 struct nouveau_bios *bios = init->bios;
1162 u8 count = nv_ro08(bios, init->offset + 1);
1164 trace("ZM_CR_GROUP\n");
1168 u8 addr = nv_ro08(bios, init->offset + 0);
1169 u8 data = nv_ro08(bios, init->offset + 1);
1171 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1174 init_wrvgai(init, 0x03d4, addr, data);
1179 * INIT_CONDITION_TIME - opcode 0x56
1183 init_condition_time(struct nvbios_init *init)
1185 struct nouveau_bios *bios = init->bios;
1186 u8 cond = nv_ro08(bios, init->offset + 1);
1187 u8 retry = nv_ro08(bios, init->offset + 2);
1188 u8 wait = min((u16)retry * 50, 100);
1190 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1193 if (!init_exec(init))
1197 if (init_condition_met(init, cond))
1202 init_exec_set(init, false);
1206 * INIT_LTIME - opcode 0x57
1210 init_ltime(struct nvbios_init *init)
1212 struct nouveau_bios *bios = init->bios;
1213 u16 msec = nv_ro16(bios, init->offset + 1);
1215 trace("LTIME\t0x%04x\n", msec);
1218 if (init_exec(init))
1223 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1227 init_zm_reg_sequence(struct nvbios_init *init)
1229 struct nouveau_bios *bios = init->bios;
1230 u32 base = nv_ro32(bios, init->offset + 1);
1231 u8 count = nv_ro08(bios, init->offset + 5);
1233 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1237 u32 data = nv_ro32(bios, init->offset);
1239 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1242 init_wr32(init, base, data);
1248 * INIT_SUB_DIRECT - opcode 0x5b
1252 init_sub_direct(struct nvbios_init *init)
1254 struct nouveau_bios *bios = init->bios;
1255 u16 addr = nv_ro16(bios, init->offset + 1);
1258 trace("SUB_DIRECT\t0x%04x\n", addr);
1260 if (init_exec(init)) {
1261 save = init->offset;
1262 init->offset = addr;
1263 if (nvbios_exec(init)) {
1264 error("error parsing sub-table\n");
1267 init->offset = save;
1274 * INIT_JUMP - opcode 0x5c
1278 init_jump(struct nvbios_init *init)
1280 struct nouveau_bios *bios = init->bios;
1281 u16 offset = nv_ro16(bios, init->offset + 1);
1283 trace("JUMP\t0x%04x\n", offset);
1284 init->offset = offset;
1288 * INIT_I2C_IF - opcode 0x5e
1292 init_i2c_if(struct nvbios_init *init)
1294 struct nouveau_bios *bios = init->bios;
1295 u8 index = nv_ro08(bios, init->offset + 1);
1296 u8 addr = nv_ro08(bios, init->offset + 2);
1297 u8 reg = nv_ro08(bios, init->offset + 3);
1298 u8 mask = nv_ro08(bios, init->offset + 4);
1299 u8 data = nv_ro08(bios, init->offset + 5);
1302 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1303 index, addr, reg, mask, data);
1305 init_exec_force(init, true);
1307 value = init_rdi2cr(init, index, addr, reg);
1308 if ((value & mask) != data)
1309 init_exec_set(init, false);
1311 init_exec_force(init, false);
1315 * INIT_COPY_NV_REG - opcode 0x5f
1319 init_copy_nv_reg(struct nvbios_init *init)
1321 struct nouveau_bios *bios = init->bios;
1322 u32 sreg = nv_ro32(bios, init->offset + 1);
1323 u8 shift = nv_ro08(bios, init->offset + 5);
1324 u32 smask = nv_ro32(bios, init->offset + 6);
1325 u32 sxor = nv_ro32(bios, init->offset + 10);
1326 u32 dreg = nv_ro32(bios, init->offset + 14);
1327 u32 dmask = nv_ro32(bios, init->offset + 18);
1330 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1331 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1332 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1333 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1336 data = init_shift(init_rd32(init, sreg), shift);
1337 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1341 * INIT_ZM_INDEX_IO - opcode 0x62
1345 init_zm_index_io(struct nvbios_init *init)
1347 struct nouveau_bios *bios = init->bios;
1348 u16 port = nv_ro16(bios, init->offset + 1);
1349 u8 index = nv_ro08(bios, init->offset + 3);
1350 u8 data = nv_ro08(bios, init->offset + 4);
1352 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1355 init_wrvgai(init, port, index, data);
1359 * INIT_COMPUTE_MEM - opcode 0x63
1363 init_compute_mem(struct nvbios_init *init)
1365 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1367 trace("COMPUTE_MEM\n");
1370 init_exec_force(init, true);
1371 if (init_exec(init) && devinit->meminit)
1372 devinit->meminit(devinit);
1373 init_exec_force(init, false);
1377 * INIT_RESET - opcode 0x65
1381 init_reset(struct nvbios_init *init)
1383 struct nouveau_bios *bios = init->bios;
1384 u32 reg = nv_ro32(bios, init->offset + 1);
1385 u32 data1 = nv_ro32(bios, init->offset + 5);
1386 u32 data2 = nv_ro32(bios, init->offset + 9);
1389 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1391 init_exec_force(init, true);
1393 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1394 init_wr32(init, reg, data1);
1396 init_wr32(init, reg, data2);
1397 init_wr32(init, 0x00184c, savepci19);
1398 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1400 init_exec_force(init, false);
1404 * INIT_CONFIGURE_MEM - opcode 0x66
1408 init_configure_mem_clk(struct nvbios_init *init)
1410 u16 mdata = bmp_mem_init_table(init->bios);
1412 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1417 init_configure_mem(struct nvbios_init *init)
1419 struct nouveau_bios *bios = init->bios;
1423 trace("CONFIGURE_MEM\n");
1426 if (bios->version.major > 2) {
1430 init_exec_force(init, true);
1432 mdata = init_configure_mem_clk(init);
1433 sdata = bmp_sdr_seq_table(bios);
1434 if (nv_ro08(bios, mdata) & 0x01)
1435 sdata = bmp_ddr_seq_table(bios);
1436 mdata += 6; /* skip to data */
1438 data = init_rdvgai(init, 0x03c4, 0x01);
1439 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1441 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1443 case 0x10021c: /* CKE_NORMAL */
1444 case 0x1002d0: /* CMD_REFRESH */
1445 case 0x1002d4: /* CMD_PRECHARGE */
1449 data = nv_ro32(bios, mdata);
1451 if (data == 0xffffffff)
1456 init_wr32(init, addr, data);
1459 init_exec_force(init, false);
1463 * INIT_CONFIGURE_CLK - opcode 0x67
1467 init_configure_clk(struct nvbios_init *init)
1469 struct nouveau_bios *bios = init->bios;
1472 trace("CONFIGURE_CLK\n");
1475 if (bios->version.major > 2) {
1479 init_exec_force(init, true);
1481 mdata = init_configure_mem_clk(init);
1484 clock = nv_ro16(bios, mdata + 4) * 10;
1485 init_prog_pll(init, 0x680500, clock);
1488 clock = nv_ro16(bios, mdata + 2) * 10;
1489 if (nv_ro08(bios, mdata) & 0x01)
1491 init_prog_pll(init, 0x680504, clock);
1493 init_exec_force(init, false);
1497 * INIT_CONFIGURE_PREINIT - opcode 0x68
1501 init_configure_preinit(struct nvbios_init *init)
1503 struct nouveau_bios *bios = init->bios;
1506 trace("CONFIGURE_PREINIT\n");
1509 if (bios->version.major > 2) {
1513 init_exec_force(init, true);
1515 strap = init_rd32(init, 0x101000);
1516 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1517 init_wrvgai(init, 0x03d4, 0x3c, strap);
1519 init_exec_force(init, false);
1523 * INIT_IO - opcode 0x69
1527 init_io(struct nvbios_init *init)
1529 struct nouveau_bios *bios = init->bios;
1530 u16 port = nv_ro16(bios, init->offset + 1);
1531 u8 mask = nv_ro16(bios, init->offset + 3);
1532 u8 data = nv_ro16(bios, init->offset + 4);
1535 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1538 /* ummm.. yes.. should really figure out wtf this is and why it's
1539 * needed some day.. it's almost certainly wrong, but, it also
1540 * somehow makes things work...
1542 if (nv_device(init->bios)->card_type >= NV_50 &&
1543 port == 0x03c3 && data == 0x01) {
1544 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1545 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1546 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1547 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1549 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1550 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1551 init_wr32(init, 0x614100, 0x00800018);
1552 init_wr32(init, 0x614900, 0x00800018);
1554 init_wr32(init, 0x614100, 0x10000018);
1555 init_wr32(init, 0x614900, 0x10000018);
1558 value = init_rdport(init, port) & mask;
1559 init_wrport(init, port, data | value);
1563 * INIT_SUB - opcode 0x6b
1567 init_sub(struct nvbios_init *init)
1569 struct nouveau_bios *bios = init->bios;
1570 u8 index = nv_ro08(bios, init->offset + 1);
1573 trace("SUB\t0x%02x\n", index);
1575 addr = init_script(bios, index);
1576 if (addr && init_exec(init)) {
1577 save = init->offset;
1578 init->offset = addr;
1579 if (nvbios_exec(init)) {
1580 error("error parsing sub-table\n");
1583 init->offset = save;
1590 * INIT_RAM_CONDITION - opcode 0x6d
1594 init_ram_condition(struct nvbios_init *init)
1596 struct nouveau_bios *bios = init->bios;
1597 u8 mask = nv_ro08(bios, init->offset + 1);
1598 u8 value = nv_ro08(bios, init->offset + 2);
1600 trace("RAM_CONDITION\t"
1601 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1604 if ((init_rd32(init, 0x100000) & mask) != value)
1605 init_exec_set(init, false);
1609 * INIT_NV_REG - opcode 0x6e
1613 init_nv_reg(struct nvbios_init *init)
1615 struct nouveau_bios *bios = init->bios;
1616 u32 reg = nv_ro32(bios, init->offset + 1);
1617 u32 mask = nv_ro32(bios, init->offset + 5);
1618 u32 data = nv_ro32(bios, init->offset + 9);
1620 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1623 init_mask(init, reg, ~mask, data);
1627 * INIT_MACRO - opcode 0x6f
1631 init_macro(struct nvbios_init *init)
1633 struct nouveau_bios *bios = init->bios;
1634 u8 macro = nv_ro08(bios, init->offset + 1);
1637 trace("MACRO\t0x%02x\n", macro);
1639 table = init_macro_table(init);
1641 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1642 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1643 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1644 init_wr32(init, addr, data);
1651 * INIT_RESUME - opcode 0x72
1655 init_resume(struct nvbios_init *init)
1659 init_exec_set(init, true);
1663 * INIT_TIME - opcode 0x74
1667 init_time(struct nvbios_init *init)
1669 struct nouveau_bios *bios = init->bios;
1670 u16 usec = nv_ro16(bios, init->offset + 1);
1672 trace("TIME\t0x%04x\n", usec);
1675 if (init_exec(init)) {
1679 mdelay((usec + 900) / 1000);
1684 * INIT_CONDITION - opcode 0x75
1688 init_condition(struct nvbios_init *init)
1690 struct nouveau_bios *bios = init->bios;
1691 u8 cond = nv_ro08(bios, init->offset + 1);
1693 trace("CONDITION\t0x%02x\n", cond);
1696 if (!init_condition_met(init, cond))
1697 init_exec_set(init, false);
1701 * INIT_IO_CONDITION - opcode 0x76
1705 init_io_condition(struct nvbios_init *init)
1707 struct nouveau_bios *bios = init->bios;
1708 u8 cond = nv_ro08(bios, init->offset + 1);
1710 trace("IO_CONDITION\t0x%02x\n", cond);
1713 if (!init_io_condition_met(init, cond))
1714 init_exec_set(init, false);
1718 * INIT_INDEX_IO - opcode 0x78
1722 init_index_io(struct nvbios_init *init)
1724 struct nouveau_bios *bios = init->bios;
1725 u16 port = nv_ro16(bios, init->offset + 1);
1726 u8 index = nv_ro16(bios, init->offset + 3);
1727 u8 mask = nv_ro08(bios, init->offset + 4);
1728 u8 data = nv_ro08(bios, init->offset + 5);
1731 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1732 port, index, mask, data);
1735 value = init_rdvgai(init, port, index) & mask;
1736 init_wrvgai(init, port, index, data | value);
1740 * INIT_PLL - opcode 0x79
1744 init_pll(struct nvbios_init *init)
1746 struct nouveau_bios *bios = init->bios;
1747 u32 reg = nv_ro32(bios, init->offset + 1);
1748 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1750 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1753 init_prog_pll(init, reg, freq);
1757 * INIT_ZM_REG - opcode 0x7a
1761 init_zm_reg(struct nvbios_init *init)
1763 struct nouveau_bios *bios = init->bios;
1764 u32 addr = nv_ro32(bios, init->offset + 1);
1765 u32 data = nv_ro32(bios, init->offset + 5);
1767 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1770 if (addr == 0x000200)
1773 init_wr32(init, addr, data);
1777 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1781 init_ram_restrict_pll(struct nvbios_init *init)
1783 struct nouveau_bios *bios = init->bios;
1784 u8 type = nv_ro08(bios, init->offset + 1);
1785 u8 count = init_ram_restrict_group_count(init);
1786 u8 strap = init_ram_restrict(init);
1789 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1792 for (cconf = 0; cconf < count; cconf++) {
1793 u32 freq = nv_ro32(bios, init->offset);
1795 if (cconf == strap) {
1796 trace("%dkHz *\n", freq);
1797 init_prog_pll(init, type, freq);
1799 trace("%dkHz\n", freq);
1807 * INIT_GPIO - opcode 0x8e
1811 init_gpio(struct nvbios_init *init)
1813 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1818 if (init_exec(init) && gpio && gpio->reset)
1819 gpio->reset(gpio, DCB_GPIO_UNUSED);
1823 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1827 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1829 struct nouveau_bios *bios = init->bios;
1830 u32 addr = nv_ro32(bios, init->offset + 1);
1831 u8 incr = nv_ro08(bios, init->offset + 5);
1832 u8 num = nv_ro08(bios, init->offset + 6);
1833 u8 count = init_ram_restrict_group_count(init);
1834 u8 index = init_ram_restrict(init);
1837 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1838 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1841 for (i = 0; i < num; i++) {
1842 trace("\tR[0x%06x] = {\n", addr);
1843 for (j = 0; j < count; j++) {
1844 u32 data = nv_ro32(bios, init->offset);
1847 trace("\t\t0x%08x *\n", data);
1848 init_wr32(init, addr, data);
1850 trace("\t\t0x%08x\n", data);
1861 * INIT_COPY_ZM_REG - opcode 0x90
1865 init_copy_zm_reg(struct nvbios_init *init)
1867 struct nouveau_bios *bios = init->bios;
1868 u32 sreg = nv_ro32(bios, init->offset + 1);
1869 u32 dreg = nv_ro32(bios, init->offset + 5);
1871 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1874 init_wr32(init, dreg, init_rd32(init, sreg));
1878 * INIT_ZM_REG_GROUP - opcode 0x91
1882 init_zm_reg_group(struct nvbios_init *init)
1884 struct nouveau_bios *bios = init->bios;
1885 u32 addr = nv_ro32(bios, init->offset + 1);
1886 u8 count = nv_ro08(bios, init->offset + 5);
1888 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1892 u32 data = nv_ro32(bios, init->offset);
1893 trace("\t0x%08x\n", data);
1894 init_wr32(init, addr, data);
1900 * INIT_XLAT - opcode 0x96
1904 init_xlat(struct nvbios_init *init)
1906 struct nouveau_bios *bios = init->bios;
1907 u32 saddr = nv_ro32(bios, init->offset + 1);
1908 u8 sshift = nv_ro08(bios, init->offset + 5);
1909 u8 smask = nv_ro08(bios, init->offset + 6);
1910 u8 index = nv_ro08(bios, init->offset + 7);
1911 u32 daddr = nv_ro32(bios, init->offset + 8);
1912 u32 dmask = nv_ro32(bios, init->offset + 12);
1913 u8 shift = nv_ro08(bios, init->offset + 16);
1916 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1917 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1918 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1919 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1922 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1923 data = init_xlat_(init, index, data) << shift;
1924 init_mask(init, daddr, ~dmask, data);
1928 * INIT_ZM_MASK_ADD - opcode 0x97
1932 init_zm_mask_add(struct nvbios_init *init)
1934 struct nouveau_bios *bios = init->bios;
1935 u32 addr = nv_ro32(bios, init->offset + 1);
1936 u32 mask = nv_ro32(bios, init->offset + 5);
1937 u32 add = nv_ro32(bios, init->offset + 9);
1940 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1943 data = init_rd32(init, addr) & mask;
1944 data |= ((data + add) & ~mask);
1945 init_wr32(init, addr, data);
1949 * INIT_AUXCH - opcode 0x98
1953 init_auxch(struct nvbios_init *init)
1955 struct nouveau_bios *bios = init->bios;
1956 u32 addr = nv_ro32(bios, init->offset + 1);
1957 u8 count = nv_ro08(bios, init->offset + 5);
1959 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1963 u8 mask = nv_ro08(bios, init->offset + 0);
1964 u8 data = nv_ro08(bios, init->offset + 1);
1965 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1966 mask = init_rdauxr(init, addr) & mask;
1967 init_wrauxr(init, addr, mask | data);
1973 * INIT_AUXCH - opcode 0x99
1977 init_zm_auxch(struct nvbios_init *init)
1979 struct nouveau_bios *bios = init->bios;
1980 u32 addr = nv_ro32(bios, init->offset + 1);
1981 u8 count = nv_ro08(bios, init->offset + 5);
1983 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1987 u8 data = nv_ro08(bios, init->offset + 0);
1988 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1989 init_wrauxr(init, addr, data);
1995 * INIT_I2C_LONG_IF - opcode 0x9a
1999 init_i2c_long_if(struct nvbios_init *init)
2001 struct nouveau_bios *bios = init->bios;
2002 u8 index = nv_ro08(bios, init->offset + 1);
2003 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2004 u8 reglo = nv_ro08(bios, init->offset + 3);
2005 u8 reghi = nv_ro08(bios, init->offset + 4);
2006 u8 mask = nv_ro08(bios, init->offset + 5);
2007 u8 data = nv_ro08(bios, init->offset + 6);
2008 struct nouveau_i2c_port *port;
2010 trace("I2C_LONG_IF\t"
2011 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2012 index, addr, reglo, reghi, mask, data);
2015 port = init_i2c(init, index);
2017 u8 i[2] = { reghi, reglo };
2019 struct i2c_msg msg[] = {
2020 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2021 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2025 ret = i2c_transfer(&port->adapter, msg, 2);
2026 if (ret == 2 && ((o[0] & mask) == data))
2030 init_exec_set(init, false);
2034 * INIT_GPIO_NE - opcode 0xa9
2038 init_gpio_ne(struct nvbios_init *init)
2040 struct nouveau_bios *bios = init->bios;
2041 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2042 struct dcb_gpio_func func;
2043 u8 count = nv_ro08(bios, init->offset + 1);
2044 u8 idx = 0, ver, len;
2050 for (i = init->offset; i < init->offset + count; i++)
2051 cont("0x%02x ", nv_ro08(bios, i));
2054 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2055 if (func.func != DCB_GPIO_UNUSED) {
2056 for (i = init->offset; i < init->offset + count; i++) {
2057 if (func.func == nv_ro08(bios, i))
2061 trace("\tFUNC[0x%02x]", func.func);
2062 if (i == (init->offset + count)) {
2064 if (init_exec(init) && gpio && gpio->reset)
2065 gpio->reset(gpio, func.func);
2071 init->offset += count;
2074 static struct nvbios_init_opcode {
2075 void (*exec)(struct nvbios_init *);
2077 [0x32] = { init_io_restrict_prog },
2078 [0x33] = { init_repeat },
2079 [0x34] = { init_io_restrict_pll },
2080 [0x36] = { init_end_repeat },
2081 [0x37] = { init_copy },
2082 [0x38] = { init_not },
2083 [0x39] = { init_io_flag_condition },
2084 [0x3a] = { init_dp_condition },
2085 [0x3b] = { init_io_mask_or },
2086 [0x3c] = { init_io_or },
2087 [0x49] = { init_idx_addr_latched },
2088 [0x4a] = { init_io_restrict_pll2 },
2089 [0x4b] = { init_pll2 },
2090 [0x4c] = { init_i2c_byte },
2091 [0x4d] = { init_zm_i2c_byte },
2092 [0x4e] = { init_zm_i2c },
2093 [0x4f] = { init_tmds },
2094 [0x50] = { init_zm_tmds_group },
2095 [0x51] = { init_cr_idx_adr_latch },
2096 [0x52] = { init_cr },
2097 [0x53] = { init_zm_cr },
2098 [0x54] = { init_zm_cr_group },
2099 [0x56] = { init_condition_time },
2100 [0x57] = { init_ltime },
2101 [0x58] = { init_zm_reg_sequence },
2102 [0x5b] = { init_sub_direct },
2103 [0x5c] = { init_jump },
2104 [0x5e] = { init_i2c_if },
2105 [0x5f] = { init_copy_nv_reg },
2106 [0x62] = { init_zm_index_io },
2107 [0x63] = { init_compute_mem },
2108 [0x65] = { init_reset },
2109 [0x66] = { init_configure_mem },
2110 [0x67] = { init_configure_clk },
2111 [0x68] = { init_configure_preinit },
2112 [0x69] = { init_io },
2113 [0x6b] = { init_sub },
2114 [0x6d] = { init_ram_condition },
2115 [0x6e] = { init_nv_reg },
2116 [0x6f] = { init_macro },
2117 [0x71] = { init_done },
2118 [0x72] = { init_resume },
2119 [0x74] = { init_time },
2120 [0x75] = { init_condition },
2121 [0x76] = { init_io_condition },
2122 [0x78] = { init_index_io },
2123 [0x79] = { init_pll },
2124 [0x7a] = { init_zm_reg },
2125 [0x87] = { init_ram_restrict_pll },
2126 [0x8c] = { init_reserved },
2127 [0x8d] = { init_reserved },
2128 [0x8e] = { init_gpio },
2129 [0x8f] = { init_ram_restrict_zm_reg_group },
2130 [0x90] = { init_copy_zm_reg },
2131 [0x91] = { init_zm_reg_group },
2132 [0x92] = { init_reserved },
2133 [0x96] = { init_xlat },
2134 [0x97] = { init_zm_mask_add },
2135 [0x98] = { init_auxch },
2136 [0x99] = { init_zm_auxch },
2137 [0x9a] = { init_i2c_long_if },
2138 [0xa9] = { init_gpio_ne },
2141 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2144 nvbios_exec(struct nvbios_init *init)
2147 while (init->offset) {
2148 u8 opcode = nv_ro08(init->bios, init->offset);
2149 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2150 error("unknown opcode 0x%02x\n", opcode);
2154 init_opcode[opcode].exec(init);
2161 nvbios_init(struct nouveau_subdev *subdev, bool execute)
2163 struct nouveau_bios *bios = nouveau_bios(subdev);
2169 nv_info(bios, "running init tables\n");
2170 while (!ret && (data = (init_script(bios, ++i)))) {
2171 struct nvbios_init init = {
2177 .execute = execute ? 1 : 0,
2180 ret = nvbios_exec(&init);
2183 /* the vbios parser will run this right after the normal init
2184 * tables, whereas the binary driver appears to run it later.
2186 if (!ret && (data = init_unknown_script(bios))) {
2187 struct nvbios_init init = {
2193 .execute = execute ? 1 : 0,
2196 ret = nvbios_exec(&init);