2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
27 #include <subdev/timer.h>
28 #include <subdev/fb.h>
29 #include <subdev/vm.h>
33 struct nvc0_bar_priv {
34 struct nouveau_bar base;
37 struct nouveau_gpuobj *mem;
38 struct nouveau_gpuobj *pgd;
39 struct nouveau_vm *vm;
44 nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
45 u32 flags, struct nouveau_vma *vma)
47 struct nvc0_bar_priv *priv = (void *)bar;
50 ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
54 nouveau_vm_map(vma, mem);
59 nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
60 u32 flags, struct nouveau_vma *vma)
62 struct nvc0_bar_priv *priv = (void *)bar;
65 ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
66 mem->page_shift, flags, vma);
70 nouveau_vm_map(vma, mem);
75 nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
77 nouveau_vm_unmap(vma);
82 nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
83 struct nouveau_oclass *oclass, void *data, u32 size,
84 struct nouveau_object **pobject)
86 struct nouveau_device *device = nv_device(parent);
87 struct nvc0_bar_priv *priv;
88 struct nouveau_gpuobj *mem;
89 struct nouveau_vm *vm;
92 ret = nouveau_bar_create(parent, engine, oclass, &priv);
93 *pobject = nv_object(priv);
98 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
100 mem = priv->bar[0].mem;
104 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
109 ret = nouveau_vm_new(device, 0, nv_device_resource_len(device, 3), 0, &vm);
113 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
115 ret = nouveau_gpuobj_new(nv_object(priv), NULL,
116 (nv_device_resource_len(device, 3) >> 12) * 8,
117 0x1000, NVOBJ_FLAG_ZERO_ALLOC,
119 vm->pgt[0].refcount[0] = 1;
123 ret = nouveau_vm_ref(vm, &priv->bar[0].vm, priv->bar[0].pgd);
124 nouveau_vm_ref(NULL, &vm, NULL);
128 nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr));
129 nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr));
130 nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 3) - 1));
131 nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 3) - 1));
134 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
136 mem = priv->bar[1].mem;
140 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
145 ret = nouveau_vm_new(device, 0, nv_device_resource_len(device, 1), 0, &vm);
149 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
151 ret = nouveau_vm_ref(vm, &priv->bar[1].vm, priv->bar[1].pgd);
152 nouveau_vm_ref(NULL, &vm, NULL);
156 nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[1].pgd->addr));
157 nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[1].pgd->addr));
158 nv_wo32(mem, 0x0208, lower_32_bits(nv_device_resource_len(device, 1) - 1));
159 nv_wo32(mem, 0x020c, upper_32_bits(nv_device_resource_len(device, 1) - 1));
161 priv->base.alloc = nouveau_bar_alloc;
162 priv->base.kmap = nvc0_bar_kmap;
163 priv->base.umap = nvc0_bar_umap;
164 priv->base.unmap = nvc0_bar_unmap;
165 priv->base.flush = nv84_bar_flush;
166 spin_lock_init(&priv->lock);
171 nvc0_bar_dtor(struct nouveau_object *object)
173 struct nvc0_bar_priv *priv = (void *)object;
175 nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
176 nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
177 nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
179 if (priv->bar[0].vm) {
180 nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
181 nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
183 nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
184 nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
186 nouveau_bar_destroy(&priv->base);
190 nvc0_bar_init(struct nouveau_object *object)
192 struct nvc0_bar_priv *priv = (void *)object;
195 ret = nouveau_bar_init(&priv->base);
199 nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
200 nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
201 nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
203 nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
204 nv_wr32(priv, 0x001714, 0xc0000000 | priv->bar[0].mem->addr >> 12);
208 struct nouveau_oclass
210 .handle = NV_SUBDEV(BAR, 0xc0),
211 .ofuncs = &(struct nouveau_ofuncs) {
212 .ctor = nvc0_bar_ctor,
213 .dtor = nvc0_bar_dtor,
214 .init = nvc0_bar_init,
215 .fini = _nouveau_bar_fini,