2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/client.h>
26 #include <core/handle.h>
27 #include <core/namedb.h>
28 #include <core/gpuobj.h>
29 #include <core/engctx.h>
30 #include <core/event.h>
31 #include <core/class.h>
32 #include <core/math.h>
33 #include <core/enum.h>
35 #include <subdev/timer.h>
36 #include <subdev/bar.h>
37 #include <subdev/vm.h>
39 #include <engine/dmaobj.h>
40 #include <engine/fifo.h>
42 #define _(a,b) { (a), ((1ULL << (a)) | (b)) }
47 _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW)),
48 _(NVDEV_ENGINE_VP , 0),
49 _(NVDEV_ENGINE_PPP , 0),
50 _(NVDEV_ENGINE_BSP , 0),
51 _(NVDEV_ENGINE_COPY0 , 0),
52 _(NVDEV_ENGINE_COPY1 , 0),
53 _(NVDEV_ENGINE_VENC , 0),
56 #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
58 struct nve0_fifo_engn {
59 struct nouveau_gpuobj *playlist[2];
63 struct nve0_fifo_priv {
64 struct nouveau_fifo base;
65 struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
67 struct nouveau_gpuobj *mem;
68 struct nouveau_vma bar;
73 struct nve0_fifo_base {
74 struct nouveau_fifo_base base;
75 struct nouveau_gpuobj *pgd;
76 struct nouveau_vm *vm;
79 struct nve0_fifo_chan {
80 struct nouveau_fifo_chan base;
84 /*******************************************************************************
85 * FIFO channel objects
86 ******************************************************************************/
89 nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
91 struct nouveau_bar *bar = nouveau_bar(priv);
92 struct nve0_fifo_engn *engn = &priv->engine[engine];
93 struct nouveau_gpuobj *cur;
94 u32 match = (engine << 16) | 0x00000001;
97 cur = engn->playlist[engn->cur_playlist];
98 if (unlikely(cur == NULL)) {
99 int ret = nouveau_gpuobj_new(nv_object(priv), NULL,
100 0x8000, 0x1000, 0, &cur);
102 nv_error(priv, "playlist alloc failed\n");
106 engn->playlist[engn->cur_playlist] = cur;
109 engn->cur_playlist = !engn->cur_playlist;
111 for (i = 0, p = 0; i < priv->base.max; i++) {
112 u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001;
115 nv_wo32(cur, p + 0, i);
116 nv_wo32(cur, p + 4, 0x00000000);
121 nv_wr32(priv, 0x002270, cur->addr >> 12);
122 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
123 if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
124 nv_error(priv, "playlist %d update timeout\n", engine);
128 nve0_fifo_context_attach(struct nouveau_object *parent,
129 struct nouveau_object *object)
131 struct nouveau_bar *bar = nouveau_bar(parent);
132 struct nve0_fifo_base *base = (void *)parent->parent;
133 struct nouveau_engctx *ectx = (void *)object;
137 switch (nv_engidx(object->engine)) {
138 case NVDEV_ENGINE_SW : return 0;
139 case NVDEV_ENGINE_GR :
140 case NVDEV_ENGINE_COPY0:
141 case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
142 case NVDEV_ENGINE_BSP : addr = 0x0270; break;
143 case NVDEV_ENGINE_VP : addr = 0x0250; break;
144 case NVDEV_ENGINE_PPP : addr = 0x0260; break;
149 if (!ectx->vma.node) {
150 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
151 NV_MEM_ACCESS_RW, &ectx->vma);
155 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
158 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
159 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
165 nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
166 struct nouveau_object *object)
168 struct nouveau_bar *bar = nouveau_bar(parent);
169 struct nve0_fifo_priv *priv = (void *)parent->engine;
170 struct nve0_fifo_base *base = (void *)parent->parent;
171 struct nve0_fifo_chan *chan = (void *)parent;
174 switch (nv_engidx(object->engine)) {
175 case NVDEV_ENGINE_SW : return 0;
176 case NVDEV_ENGINE_GR :
177 case NVDEV_ENGINE_COPY0:
178 case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
179 case NVDEV_ENGINE_BSP : addr = 0x0270; break;
180 case NVDEV_ENGINE_VP : addr = 0x0250; break;
181 case NVDEV_ENGINE_PPP : addr = 0x0260; break;
186 nv_wr32(priv, 0x002634, chan->base.chid);
187 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
188 nv_error(priv, "channel %d [%s] kick timeout\n",
189 chan->base.chid, nouveau_client_name(chan));
194 nv_wo32(base, addr + 0x00, 0x00000000);
195 nv_wo32(base, addr + 0x04, 0x00000000);
201 nve0_fifo_chan_ctor(struct nouveau_object *parent,
202 struct nouveau_object *engine,
203 struct nouveau_oclass *oclass, void *data, u32 size,
204 struct nouveau_object **pobject)
206 struct nouveau_bar *bar = nouveau_bar(parent);
207 struct nve0_fifo_priv *priv = (void *)engine;
208 struct nve0_fifo_base *base = (void *)parent;
209 struct nve0_fifo_chan *chan;
210 struct nve0_channel_ind_class *args = data;
211 u64 usermem, ioffset, ilength;
214 if (size < sizeof(*args))
217 for (i = 0; i < FIFO_ENGINE_NR; i++) {
218 if (args->engine & (1 << i)) {
219 if (nouveau_engine(parent, fifo_engine[i].subdev)) {
220 args->engine = (1 << i);
226 if (i == FIFO_ENGINE_NR)
229 ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
230 priv->user.bar.offset, 0x200,
232 fifo_engine[i].mask, &chan);
233 *pobject = nv_object(chan);
237 nv_parent(chan)->context_attach = nve0_fifo_context_attach;
238 nv_parent(chan)->context_detach = nve0_fifo_context_detach;
241 usermem = chan->base.chid * 0x200;
242 ioffset = args->ioffset;
243 ilength = log2i(args->ilength / 8);
245 for (i = 0; i < 0x200; i += 4)
246 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
248 nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
249 nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
250 nv_wo32(base, 0x10, 0x0000face);
251 nv_wo32(base, 0x30, 0xfffff902);
252 nv_wo32(base, 0x48, lower_32_bits(ioffset));
253 nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
254 nv_wo32(base, 0x84, 0x20400000);
255 nv_wo32(base, 0x94, 0x30000001);
256 nv_wo32(base, 0x9c, 0x00000100);
257 nv_wo32(base, 0xac, 0x0000001f);
258 nv_wo32(base, 0xe8, chan->base.chid);
259 nv_wo32(base, 0xb8, 0xf8000000);
260 nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
261 nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
267 nve0_fifo_chan_init(struct nouveau_object *object)
269 struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
270 struct nve0_fifo_priv *priv = (void *)object->engine;
271 struct nve0_fifo_chan *chan = (void *)object;
272 u32 chid = chan->base.chid;
275 ret = nouveau_fifo_channel_init(&chan->base);
279 nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
280 nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
281 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
282 nve0_fifo_playlist_update(priv, chan->engine);
283 nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
288 nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
290 struct nve0_fifo_priv *priv = (void *)object->engine;
291 struct nve0_fifo_chan *chan = (void *)object;
292 u32 chid = chan->base.chid;
294 nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
295 nve0_fifo_playlist_update(priv, chan->engine);
296 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
298 return nouveau_fifo_channel_fini(&chan->base, suspend);
301 static struct nouveau_ofuncs
303 .ctor = nve0_fifo_chan_ctor,
304 .dtor = _nouveau_fifo_channel_dtor,
305 .init = nve0_fifo_chan_init,
306 .fini = nve0_fifo_chan_fini,
307 .rd32 = _nouveau_fifo_channel_rd32,
308 .wr32 = _nouveau_fifo_channel_wr32,
311 static struct nouveau_oclass
312 nve0_fifo_sclass[] = {
313 { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs },
317 /*******************************************************************************
318 * FIFO context - instmem heap and vm setup
319 ******************************************************************************/
322 nve0_fifo_context_ctor(struct nouveau_object *parent,
323 struct nouveau_object *engine,
324 struct nouveau_oclass *oclass, void *data, u32 size,
325 struct nouveau_object **pobject)
327 struct nve0_fifo_base *base;
330 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
331 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
332 *pobject = nv_object(base);
336 ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
341 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
342 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
343 nv_wo32(base, 0x0208, 0xffffffff);
344 nv_wo32(base, 0x020c, 0x000000ff);
346 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
354 nve0_fifo_context_dtor(struct nouveau_object *object)
356 struct nve0_fifo_base *base = (void *)object;
357 nouveau_vm_ref(NULL, &base->vm, base->pgd);
358 nouveau_gpuobj_ref(NULL, &base->pgd);
359 nouveau_fifo_context_destroy(&base->base);
362 static struct nouveau_oclass
364 .handle = NV_ENGCTX(FIFO, 0xe0),
365 .ofuncs = &(struct nouveau_ofuncs) {
366 .ctor = nve0_fifo_context_ctor,
367 .dtor = nve0_fifo_context_dtor,
368 .init = _nouveau_fifo_context_init,
369 .fini = _nouveau_fifo_context_fini,
370 .rd32 = _nouveau_fifo_context_rd32,
371 .wr32 = _nouveau_fifo_context_wr32,
375 /*******************************************************************************
377 ******************************************************************************/
379 static const struct nouveau_enum nve0_fifo_fault_unit[] = {
383 static const struct nouveau_enum nve0_fifo_fault_reason[] = {
384 { 0x00, "PT_NOT_PRESENT" },
385 { 0x01, "PT_TOO_SHORT" },
386 { 0x02, "PAGE_NOT_PRESENT" },
387 { 0x03, "VM_LIMIT_EXCEEDED" },
388 { 0x04, "NO_CHANNEL" },
389 { 0x05, "PAGE_SYSTEM_ONLY" },
390 { 0x06, "PAGE_READ_ONLY" },
391 { 0x0a, "COMPRESSED_SYSRAM" },
392 { 0x0c, "INVALID_STORAGE_TYPE" },
396 static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
400 static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
404 static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = {
405 { 0x00200000, "ILLEGAL_MTHD" },
406 { 0x00800000, "EMPTY_SUBC" },
411 nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
413 u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
414 u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
415 u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
416 u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
417 u32 client = (stat & 0x00001f00) >> 8;
418 const struct nouveau_enum *en;
419 struct nouveau_engine *engine;
420 struct nouveau_object *engctx = NULL;
422 nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
423 "write" : "read", (u64)vahi << 32 | valo);
424 nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
426 en = nouveau_enum_print(nve0_fifo_fault_unit, unit);
427 if (stat & 0x00000040) {
429 nouveau_enum_print(nve0_fifo_fault_hubclient, client);
431 pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
432 nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
435 if (en && en->data2) {
436 engine = nouveau_engine(priv, en->data2);
438 engctx = nouveau_engctx_get(engine, inst);
442 pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
443 nouveau_client_name(engctx));
445 nouveau_engctx_put(engctx);
449 nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
451 struct nve0_fifo_chan *chan = NULL;
452 struct nouveau_handle *bind;
456 spin_lock_irqsave(&priv->base.lock, flags);
457 if (likely(chid >= priv->base.min && chid <= priv->base.max))
458 chan = (void *)priv->base.channel[chid];
462 bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
464 if (!mthd || !nv_call(bind->object, mthd, data))
466 nouveau_namedb_put(bind);
470 spin_unlock_irqrestore(&priv->base.lock, flags);
475 nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
477 u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
478 u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
479 u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
480 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
481 u32 subc = (addr & 0x00070000) >> 16;
482 u32 mthd = (addr & 0x00003ffc);
485 if (stat & 0x00200000) {
486 if (mthd == 0x0054) {
487 if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
492 if (stat & 0x00800000) {
493 if (!nve0_fifo_swmthd(priv, chid, mthd, data))
498 nv_error(priv, "SUBFIFO%d:", unit);
499 nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
502 "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
504 nouveau_client_name_for_fifo_chid(&priv->base, chid),
508 nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
509 nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
513 nve0_fifo_intr(struct nouveau_subdev *subdev)
515 struct nve0_fifo_priv *priv = (void *)subdev;
516 u32 mask = nv_rd32(priv, 0x002140);
517 u32 stat = nv_rd32(priv, 0x002100) & mask;
519 if (stat & 0x00000100) {
520 nv_warn(priv, "unknown status 0x00000100\n");
521 nv_wr32(priv, 0x002100, 0x00000100);
525 if (stat & 0x10000000) {
526 u32 units = nv_rd32(priv, 0x00259c);
531 nve0_fifo_isr_vm_fault(priv, i);
535 nv_wr32(priv, 0x00259c, units);
539 if (stat & 0x20000000) {
540 u32 units = nv_rd32(priv, 0x0025a0);
545 nve0_fifo_isr_subfifo_intr(priv, i);
549 nv_wr32(priv, 0x0025a0, units);
553 if (stat & 0x40000000) {
554 nv_warn(priv, "unknown status 0x40000000\n");
555 nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
559 if (stat & 0x80000000) {
560 nouveau_event_trigger(priv->base.uevent, 0);
561 nv_wr32(priv, 0x002100, 0x80000000);
566 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
567 nv_wr32(priv, 0x002100, stat);
568 nv_wr32(priv, 0x002140, 0);
573 nve0_fifo_uevent_enable(struct nouveau_event *event, int index)
575 struct nve0_fifo_priv *priv = event->priv;
576 nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
580 nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
582 struct nve0_fifo_priv *priv = event->priv;
583 nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
587 nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
588 struct nouveau_oclass *oclass, void *data, u32 size,
589 struct nouveau_object **pobject)
591 struct nve0_fifo_priv *priv;
594 ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv);
595 *pobject = nv_object(priv);
599 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000,
600 NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
604 ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
609 priv->base.uevent->enable = nve0_fifo_uevent_enable;
610 priv->base.uevent->disable = nve0_fifo_uevent_disable;
611 priv->base.uevent->priv = priv;
613 nv_subdev(priv)->unit = 0x00000100;
614 nv_subdev(priv)->intr = nve0_fifo_intr;
615 nv_engine(priv)->cclass = &nve0_fifo_cclass;
616 nv_engine(priv)->sclass = nve0_fifo_sclass;
621 nve0_fifo_dtor(struct nouveau_object *object)
623 struct nve0_fifo_priv *priv = (void *)object;
626 nouveau_gpuobj_unmap(&priv->user.bar);
627 nouveau_gpuobj_ref(NULL, &priv->user.mem);
629 for (i = 0; i < ARRAY_SIZE(priv->engine); i++) {
630 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
631 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
634 nouveau_fifo_destroy(&priv->base);
638 nve0_fifo_init(struct nouveau_object *object)
640 struct nve0_fifo_priv *priv = (void *)object;
643 ret = nouveau_fifo_init(&priv->base);
647 /* enable all available PSUBFIFOs */
648 nv_wr32(priv, 0x000204, 0xffffffff);
649 priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
650 nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
653 for (i = 0; i < priv->spoon_nr; i++) {
654 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
655 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
656 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
659 nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
661 nv_wr32(priv, 0x002a00, 0xffffffff);
662 nv_wr32(priv, 0x002100, 0xffffffff);
663 nv_wr32(priv, 0x002140, 0x3fffffff);
667 struct nouveau_oclass
669 .handle = NV_ENGINE(FIFO, 0xe0),
670 .ofuncs = &(struct nouveau_ofuncs) {
671 .ctor = nve0_fifo_ctor,
672 .dtor = nve0_fifo_dtor,
673 .init = nve0_fifo_init,
674 .fini = _nouveau_fifo_fini,