2 * Copyright 2013 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/bios.h>
26 #include <subdev/bios/dcb.h>
27 #include <subdev/bios/dp.h>
28 #include <subdev/bios/init.h>
29 #include <subdev/i2c.h>
31 #include <engine/disp.h>
35 #define DBG(fmt, args...) nv_debug(dp->disp, "DP:%04x:%04x: " fmt, \
36 dp->outp->hasht, dp->outp->hashm, ##args)
37 #define ERR(fmt, args...) nv_error(dp->disp, "DP:%04x:%04x: " fmt, \
38 dp->outp->hasht, dp->outp->hashm, ##args)
40 /******************************************************************************
42 *****************************************************************************/
44 const struct nouveau_dp_func *func;
45 struct nouveau_disp *disp;
46 struct dcb_output *outp;
47 struct nvbios_dpout info;
49 struct nouveau_i2c_port *aux;
59 dp_set_link_config(struct dp_state *dp)
61 struct nouveau_disp *disp = dp->disp;
62 struct nouveau_bios *bios = nouveau_bios(disp);
63 struct nvbios_init init = {
64 .subdev = nv_subdev(dp->disp),
75 DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
77 /* set desired link configuration on the source */
78 if ((lnkcmp = dp->info.lnkcmp)) {
79 if (dp->version < 0x30) {
80 while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp))
82 init.offset = nv_ro16(bios, lnkcmp + 2);
84 while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp))
86 init.offset = nv_ro16(bios, lnkcmp + 1);
92 ret = dp->func->lnk_ctl(dp->disp, dp->outp, dp->head,
93 dp->link_nr, dp->link_bw / 27000,
95 DPCD_RC02_ENHANCED_FRAME_CAP);
97 ERR("lnk_ctl failed with %d\n", ret);
101 /* set desired link configuration on the sink */
102 sink[0] = dp->link_bw / 27000;
103 sink[1] = dp->link_nr;
104 if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
105 sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
107 return nv_wraux(dp->aux, DPCD_LC00, sink, 2);
111 dp_set_training_pattern(struct dp_state *dp, u8 pattern)
115 DBG("training pattern %d\n", pattern);
116 dp->func->pattern(dp->disp, dp->outp, dp->head, pattern);
118 nv_rdaux(dp->aux, DPCD_LC02, &sink_tp, 1);
119 sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET;
121 nv_wraux(dp->aux, DPCD_LC02, &sink_tp, 1);
125 dp_link_train_commit(struct dp_state *dp)
129 for (i = 0; i < dp->link_nr; i++) {
130 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
131 u8 lpre = (lane & 0x0c) >> 2;
132 u8 lvsw = (lane & 0x03) >> 0;
134 dp->conf[i] = (lpre << 3) | lvsw;
136 dp->conf[i] |= DPCD_LC03_MAX_SWING_REACHED;
138 dp->conf[i] |= DPCD_LC03_MAX_PRE_EMPHASIS_REACHED;
140 DBG("config lane %d %02x\n", i, dp->conf[i]);
141 dp->func->drv_ctl(dp->disp, dp->outp, dp->head, i, lvsw, lpre);
144 return nv_wraux(dp->aux, DPCD_LC03(0), dp->conf, 4);
148 dp_link_train_update(struct dp_state *dp, u32 delay)
154 ret = nv_rdaux(dp->aux, DPCD_LS02, dp->stat, 6);
158 DBG("status %6ph\n", dp->stat);
163 dp_link_train_cr(struct dp_state *dp)
165 bool cr_done = false, abort = false;
166 int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
169 dp_set_training_pattern(dp, 1);
172 if (dp_link_train_commit(dp) ||
173 dp_link_train_update(dp, 100))
177 for (i = 0; i < dp->link_nr; i++) {
178 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
179 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) {
181 if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED)
187 if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) {
188 voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET;
191 } while (!cr_done && !abort && ++tries < 5);
193 return cr_done ? 0 : -1;
197 dp_link_train_eq(struct dp_state *dp)
199 bool eq_done = false, cr_done = true;
202 dp_set_training_pattern(dp, 2);
205 if (dp_link_train_update(dp, 400))
208 eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE);
209 for (i = 0; i < dp->link_nr && eq_done; i++) {
210 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
211 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
213 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
214 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
218 if (dp_link_train_commit(dp))
220 } while (!eq_done && cr_done && ++tries <= 5);
222 return eq_done ? 0 : -1;
226 dp_link_train_init(struct dp_state *dp, bool spread)
228 struct nvbios_init init = {
229 .subdev = nv_subdev(dp->disp),
230 .bios = nouveau_bios(dp->disp),
236 /* set desired spread */
238 init.offset = dp->info.script[2];
240 init.offset = dp->info.script[3];
243 /* pre-train script */
244 init.offset = dp->info.script[0];
249 dp_link_train_fini(struct dp_state *dp)
251 struct nvbios_init init = {
252 .subdev = nv_subdev(dp->disp),
253 .bios = nouveau_bios(dp->disp),
259 /* post-train script */
260 init.offset = dp->info.script[1],
265 nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
266 struct dcb_output *outp, int head, u32 datarate)
268 struct nouveau_bios *bios = nouveau_bios(disp);
269 struct nouveau_i2c *i2c = nouveau_i2c(disp);
270 struct dp_state _dp = {
276 const u32 bw_list[] = { 540000, 270000, 162000, 0 };
277 const u32 *link_bw = bw_list;
282 /* find the bios displayport data relevant to this output */
283 data = nvbios_dpout_match(bios, outp->hasht, outp->hashm, &dp->version,
284 &hdr, &cnt, &len, &dp->info);
286 ERR("bios data not found\n");
290 /* acquire the aux channel and fetch some info about the display */
292 dp->aux = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(outp->extdev));
294 dp->aux = i2c->find(i2c, NV_I2C_TYPE_DCBI2C(outp->i2c_index));
296 ERR("no aux channel?!\n");
300 ret = nv_rdaux(dp->aux, 0x00000, dp->dpcd, sizeof(dp->dpcd));
302 /* it's possible the display has been unplugged before we
303 * get here. we still need to execute the full set of
304 * vbios scripts, and program the OR at a high enough
305 * frequency to satisfy the target mode. failure to do
306 * so results at best in an UPDATE hanging, and at worst
307 * with PDISP running away to join the circus.
309 dp->dpcd[1] = link_bw[0] / 27000;
312 ERR("failed to read DPCD\n");
315 /* bring capabilities within encoder limits */
316 if ((dp->dpcd[2] & 0x1f) > dp->outp->dpconf.link_nr) {
317 dp->dpcd[2] &= ~0x1f;
318 dp->dpcd[2] |= dp->outp->dpconf.link_nr;
320 if (dp->dpcd[1] > dp->outp->dpconf.link_bw)
321 dp->dpcd[1] = dp->outp->dpconf.link_bw;
323 /* adjust required bandwidth for 8B/10B coding overhead */
324 datarate = (datarate / 8) * 10;
326 /* enable down-spreading and execute pre-train script from vbios */
327 dp_link_train_init(dp, dp->dpcd[3] & 0x01);
329 /* start off at highest link rate supported by encoder and display */
330 while (*link_bw > (dp->dpcd[1] * 27000))
333 while ((ret = -EIO) && link_bw[0]) {
334 /* find minimum required lane count at this link rate */
335 dp->link_nr = dp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT;
336 while ((dp->link_nr >> 1) * link_bw[0] > datarate)
339 /* drop link rate to minimum with this lane count */
340 while ((link_bw[1] * dp->link_nr) > datarate)
342 dp->link_bw = link_bw[0];
344 /* program selected link configuration */
345 ret = dp_set_link_config(dp);
347 /* attempt to train the link at this configuration */
348 memset(dp->stat, 0x00, sizeof(dp->stat));
349 if (!dp_link_train_cr(dp) &&
350 !dp_link_train_eq(dp))
354 /* dp_set_link_config() handled training, or
355 * we failed to communicate with the sink.
360 /* retry at lower rate */
364 /* finish link training */
365 dp_set_training_pattern(dp, 0);
367 ERR("link training failed\n");
369 /* execute post-train script from vbios */
370 dp_link_train_fini(dp);
371 return (ret < 0) ? false : true;