drivers/gpu/drm/mxsfb/lcdif_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2022 Marek Vasut <marex@denx.de>
   4  *
   5  * This code is based on drivers/gpu/drm/mxsfb/mxsfb*
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/media-bus-format.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/spinlock.h>
  14
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_bridge.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_encoder.h>
  20 #include <drm/drm_fb_dma_helper.h>
  21 #include <drm/drm_fourcc.h>
  22 #include <drm/drm_framebuffer.h>
  23 #include <drm/drm_gem_atomic_helper.h>
  24 #include <drm/drm_gem_dma_helper.h>
  25 #include <drm/drm_plane.h>
  26 #include <drm/drm_vblank.h>
  27
  28 #include "lcdif_drv.h"
  29 #include "lcdif_regs.h"
  30
  31 /* -----------------------------------------------------------------------------
  32  * CRTC
  33  */
  34 static void lcdif_set_formats(struct lcdif_drm_private *lcdif,
  35                               const u32 bus_format)
  36 {
  37         struct drm_device *drm = lcdif->drm;
  38         const u32 format = lcdif->crtc.primary->state->fb->format->format;
  39
  40         writel(CSC0_CTRL_BYPASS, lcdif->base + LCDC_V8_CSC0_CTRL);
  41
  42         switch (bus_format) {
  43         case MEDIA_BUS_FMT_RGB565_1X16:
  44                 writel(DISP_PARA_LINE_PATTERN_RGB565,
  45                        lcdif->base + LCDC_V8_DISP_PARA);
  46                 break;
  47         case MEDIA_BUS_FMT_RGB888_1X24:
  48                 writel(DISP_PARA_LINE_PATTERN_RGB888,
  49                        lcdif->base + LCDC_V8_DISP_PARA);
  50                 break;
  51         case MEDIA_BUS_FMT_UYVY8_1X16:
  52                 writel(DISP_PARA_LINE_PATTERN_UYVY_H,
  53                        lcdif->base + LCDC_V8_DISP_PARA);
  54
  55                 /* CSC: BT.601 Full Range RGB to YCbCr coefficients. */
  56                 writel(CSC0_COEF0_A2(0x096) | CSC0_COEF0_A1(0x04c),
  57                        lcdif->base + LCDC_V8_CSC0_COEF0);
  58                 writel(CSC0_COEF1_B1(0x7d5) | CSC0_COEF1_A3(0x01d),
  59                        lcdif->base + LCDC_V8_CSC0_COEF1);
  60                 writel(CSC0_COEF2_B3(0x080) | CSC0_COEF2_B2(0x7ac),
  61                        lcdif->base + LCDC_V8_CSC0_COEF2);
  62                 writel(CSC0_COEF3_C2(0x795) | CSC0_COEF3_C1(0x080),
  63                        lcdif->base + LCDC_V8_CSC0_COEF3);
  64                 writel(CSC0_COEF4_D1(0x000) | CSC0_COEF4_C3(0x7ec),
  65                        lcdif->base + LCDC_V8_CSC0_COEF4);
  66                 writel(CSC0_COEF5_D3(0x080) | CSC0_COEF5_D2(0x080),
  67                        lcdif->base + LCDC_V8_CSC0_COEF5);
  68
  69                 writel(CSC0_CTRL_CSC_MODE_RGB2YCbCr,
  70                        lcdif->base + LCDC_V8_CSC0_CTRL);
  71
  72                 break;
  73         default:
  74                 dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format);
  75                 break;
  76         }
  77
  78         switch (format) {
  79         case DRM_FORMAT_RGB565:
  80                 writel(CTRLDESCL0_5_BPP_16_RGB565,
  81                        lcdif->base + LCDC_V8_CTRLDESCL0_5);
  82                 break;
  83         case DRM_FORMAT_RGB888:
  84                 writel(CTRLDESCL0_5_BPP_24_RGB888,
  85                        lcdif->base + LCDC_V8_CTRLDESCL0_5);
  86                 break;
  87         case DRM_FORMAT_XRGB1555:
  88                 writel(CTRLDESCL0_5_BPP_16_ARGB1555,
  89                        lcdif->base + LCDC_V8_CTRLDESCL0_5);
  90                 break;
  91         case DRM_FORMAT_XRGB4444:
  92                 writel(CTRLDESCL0_5_BPP_16_ARGB4444,
  93                        lcdif->base + LCDC_V8_CTRLDESCL0_5);
  94                 break;
  95         case DRM_FORMAT_XBGR8888:
  96                 writel(CTRLDESCL0_5_BPP_32_ABGR8888,
  97                        lcdif->base + LCDC_V8_CTRLDESCL0_5);
  98                 break;
  99         case DRM_FORMAT_XRGB8888:
 100                 writel(CTRLDESCL0_5_BPP_32_ARGB8888,
 101                        lcdif->base + LCDC_V8_CTRLDESCL0_5);
 102                 break;
 103         default:
 104                 dev_err(drm->dev, "Unknown pixel format 0x%x\n", format);
 105                 break;
 106         }
 107 }
 108
 109 static void lcdif_set_mode(struct lcdif_drm_private *lcdif, u32 bus_flags)
 110 {
 111         struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
 112         u32 ctrl = 0;
 113
 114         if (m->flags & DRM_MODE_FLAG_NHSYNC)
 115                 ctrl |= CTRL_INV_HS;
 116         if (m->flags & DRM_MODE_FLAG_NVSYNC)
 117                 ctrl |= CTRL_INV_VS;
 118         if (bus_flags & DRM_BUS_FLAG_DE_LOW)
 119                 ctrl |= CTRL_INV_DE;
 120         if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 121                 ctrl |= CTRL_INV_PXCK;
 122
 123         writel(ctrl, lcdif->base + LCDC_V8_CTRL);
 124
 125         writel(DISP_SIZE_DELTA_Y(m->vdisplay) |
 126                DISP_SIZE_DELTA_X(m->hdisplay),
 127                lcdif->base + LCDC_V8_DISP_SIZE);
 128
 129         writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) |
 130                HSYN_PARA_FP_H(m->hsync_start - m->hdisplay),
 131                lcdif->base + LCDC_V8_HSYN_PARA);
 132
 133         writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) |
 134                VSYN_PARA_FP_V(m->vsync_start - m->vdisplay),
 135                lcdif->base + LCDC_V8_VSYN_PARA);
 136
 137         writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) |
 138                VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start),
 139                lcdif->base + LCDC_V8_VSYN_HSYN_WIDTH);
 140
 141         writel(CTRLDESCL0_1_HEIGHT(m->vdisplay) |
 142                CTRLDESCL0_1_WIDTH(m->hdisplay),
 143                lcdif->base + LCDC_V8_CTRLDESCL0_1);
 144
 145         writel(CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]),
 146                lcdif->base + LCDC_V8_CTRLDESCL0_3);
 147 }
 148
 149 static void lcdif_enable_controller(struct lcdif_drm_private *lcdif)
 150 {
 151         u32 reg;
 152
 153         reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
 154         reg |= DISP_PARA_DISP_ON;
 155         writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
 156
 157         reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
 158         reg |= CTRLDESCL0_5_EN;
 159         writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
 160 }
 161
 162 static void lcdif_disable_controller(struct lcdif_drm_private *lcdif)
 163 {
 164         u32 reg;
 165         int ret;
 166
 167         reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
 168         reg &= ~CTRLDESCL0_5_EN;
 169         writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
 170
 171         ret = readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5,
 172                                  reg, !(reg & CTRLDESCL0_5_EN),
 173                                  0, 36000);     /* Wait ~2 frame times max */
 174         if (ret)
 175                 drm_err(lcdif->drm, "Failed to disable controller!\n");
 176
 177         reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
 178         reg &= ~DISP_PARA_DISP_ON;
 179         writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
 180 }
 181
 182 static void lcdif_reset_block(struct lcdif_drm_private *lcdif)
 183 {
 184         writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET);
 185         readl(lcdif->base + LCDC_V8_CTRL);
 186         writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR);
 187         readl(lcdif->base + LCDC_V8_CTRL);
 188 }
 189
 190 static void lcdif_crtc_mode_set_nofb(struct lcdif_drm_private *lcdif,
 191                                      struct drm_bridge_state *bridge_state,
 192                                      const u32 bus_format)
 193 {
 194         struct drm_device *drm = lcdif->crtc.dev;
 195         struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
 196         u32 bus_flags = 0;
 197
 198         if (lcdif->bridge && lcdif->bridge->timings)
 199                 bus_flags = lcdif->bridge->timings->input_bus_flags;
 200         else if (bridge_state)
 201                 bus_flags = bridge_state->input_bus_cfg.flags;
 202
 203         DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
 204                              m->crtc_clock,
 205                              (int)(clk_get_rate(lcdif->clk) / 1000));
 206         DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n",
 207                              bus_flags);
 208         DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags);
 209
 210         /* Mandatory eLCDIF reset as per the Reference Manual */
 211         lcdif_reset_block(lcdif);
 212
 213         lcdif_set_formats(lcdif, bus_format);
 214
 215         lcdif_set_mode(lcdif, bus_flags);
 216 }
 217
 218 static int lcdif_crtc_atomic_check(struct drm_crtc *crtc,
 219                                    struct drm_atomic_state *state)
 220 {
 221         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 222                                                                           crtc);
 223         bool has_primary = crtc_state->plane_mask &
 224                            drm_plane_mask(crtc->primary);
 225
 226         /* The primary plane has to be enabled when the CRTC is active. */
 227         if (crtc_state->active && !has_primary)
 228                 return -EINVAL;
 229
 230         return drm_atomic_add_affected_planes(state, crtc);
 231 }
 232
 233 static void lcdif_crtc_atomic_flush(struct drm_crtc *crtc,
 234                                     struct drm_atomic_state *state)
 235 {
 236         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
 237         struct drm_pending_vblank_event *event;
 238         u32 reg;
 239
 240         reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
 241         reg |= CTRLDESCL0_5_SHADOW_LOAD_EN;
 242         writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
 243
 244         event = crtc->state->event;
 245         crtc->state->event = NULL;
 246
 247         if (!event)
 248                 return;
 249
 250         spin_lock_irq(&crtc->dev->event_lock);
 251         if (drm_crtc_vblank_get(crtc) == 0)
 252                 drm_crtc_arm_vblank_event(crtc, event);
 253         else
 254                 drm_crtc_send_vblank_event(crtc, event);
 255         spin_unlock_irq(&crtc->dev->event_lock);
 256 }
 257
 258 static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc,
 259                                      struct drm_atomic_state *state)
 260 {
 261         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
 262         struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
 263                                                                             crtc->primary);
 264         struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
 265         struct drm_bridge_state *bridge_state = NULL;
 266         struct drm_device *drm = lcdif->drm;
 267         u32 bus_format = 0;
 268         dma_addr_t paddr;
 269
 270         /* If there is a bridge attached to the LCDIF, use its bus format */
 271         if (lcdif->bridge) {
 272                 bridge_state =
 273                         drm_atomic_get_new_bridge_state(state,
 274                                                         lcdif->bridge);
 275                 if (!bridge_state)
 276                         bus_format = MEDIA_BUS_FMT_FIXED;
 277                 else
 278                         bus_format = bridge_state->input_bus_cfg.format;
 279
 280                 if (bus_format == MEDIA_BUS_FMT_FIXED) {
 281                         dev_warn_once(drm->dev,
 282                                       "Bridge does not provide bus format, assuming MEDIA_BUS_FMT_RGB888_1X24.\n"
 283                                       "Please fix bridge driver by handling atomic_get_input_bus_fmts.\n");
 284                         bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 285                 }
 286         }
 287
 288         /* If all else fails, default to RGB888_1X24 */
 289         if (!bus_format)
 290                 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
 291
 292         clk_set_rate(lcdif->clk, m->crtc_clock * 1000);
 293
 294         pm_runtime_get_sync(drm->dev);
 295
 296         lcdif_crtc_mode_set_nofb(lcdif, bridge_state, bus_format);
 297
 298         /* Write cur_buf as well to avoid an initial corrupt frame */
 299         paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
 300         if (paddr) {
 301                 writel(lower_32_bits(paddr),
 302                        lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
 303                 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
 304                        lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
 305         }
 306         lcdif_enable_controller(lcdif);
 307
 308         drm_crtc_vblank_on(crtc);
 309 }
 310
 311 static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc,
 312                                       struct drm_atomic_state *state)
 313 {
 314         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
 315         struct drm_device *drm = lcdif->drm;
 316         struct drm_pending_vblank_event *event;
 317
 318         drm_crtc_vblank_off(crtc);
 319
 320         lcdif_disable_controller(lcdif);
 321
 322         spin_lock_irq(&drm->event_lock);
 323         event = crtc->state->event;
 324         if (event) {
 325                 crtc->state->event = NULL;
 326                 drm_crtc_send_vblank_event(crtc, event);
 327         }
 328         spin_unlock_irq(&drm->event_lock);
 329
 330         pm_runtime_put_sync(drm->dev);
 331 }
 332
 333 static int lcdif_crtc_enable_vblank(struct drm_crtc *crtc)
 334 {
 335         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
 336
 337         /* Clear and enable VBLANK IRQ */
 338         writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
 339         writel(INT_ENABLE_D0_VS_BLANK_EN, lcdif->base + LCDC_V8_INT_ENABLE_D0);
 340
 341         return 0;
 342 }
 343
 344 static void lcdif_crtc_disable_vblank(struct drm_crtc *crtc)
 345 {
 346         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
 347
 348         /* Disable and clear VBLANK IRQ */
 349         writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D0);
 350         writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
 351 }
 352
 353 static const struct drm_crtc_helper_funcs lcdif_crtc_helper_funcs = {
 354         .atomic_check = lcdif_crtc_atomic_check,
 355         .atomic_flush = lcdif_crtc_atomic_flush,
 356         .atomic_enable = lcdif_crtc_atomic_enable,
 357         .atomic_disable = lcdif_crtc_atomic_disable,
 358 };
 359
 360 static const struct drm_crtc_funcs lcdif_crtc_funcs = {
 361         .reset = drm_atomic_helper_crtc_reset,
 362         .destroy = drm_crtc_cleanup,
 363         .set_config = drm_atomic_helper_set_config,
 364         .page_flip = drm_atomic_helper_page_flip,
 365         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 366         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 367         .enable_vblank = lcdif_crtc_enable_vblank,
 368         .disable_vblank = lcdif_crtc_disable_vblank,
 369 };
 370
 371 /* -----------------------------------------------------------------------------
 372  * Encoder
 373  */
 374
 375 static const struct drm_encoder_funcs lcdif_encoder_funcs = {
 376         .destroy = drm_encoder_cleanup,
 377 };
 378
 379 /* -----------------------------------------------------------------------------
 380  * Planes
 381  */
 382
 383 static int lcdif_plane_atomic_check(struct drm_plane *plane,
 384                                     struct drm_atomic_state *state)
 385 {
 386         struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
 387                                                                              plane);
 388         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev);
 389         struct drm_crtc_state *crtc_state;
 390
 391         crtc_state = drm_atomic_get_new_crtc_state(state,
 392                                                    &lcdif->crtc);
 393
 394         return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
 395                                                    DRM_PLANE_NO_SCALING,
 396                                                    DRM_PLANE_NO_SCALING,
 397                                                    false, true);
 398 }
 399
 400 static void lcdif_plane_primary_atomic_update(struct drm_plane *plane,
 401                                               struct drm_atomic_state *state)
 402 {
 403         struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev);
 404         struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
 405                                                                             plane);
 406         dma_addr_t paddr;
 407
 408         paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0);
 409         if (paddr) {
 410                 writel(lower_32_bits(paddr),
 411                        lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
 412                 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
 413                        lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
 414         }
 415 }
 416
 417 static bool lcdif_format_mod_supported(struct drm_plane *plane,
 418                                        uint32_t format,
 419                                        uint64_t modifier)
 420 {
 421         return modifier == DRM_FORMAT_MOD_LINEAR;
 422 }
 423
 424 static const struct drm_plane_helper_funcs lcdif_plane_primary_helper_funcs = {
 425         .atomic_check = lcdif_plane_atomic_check,
 426         .atomic_update = lcdif_plane_primary_atomic_update,
 427 };
 428
 429 static const struct drm_plane_funcs lcdif_plane_funcs = {
 430         .format_mod_supported   = lcdif_format_mod_supported,
 431         .update_plane           = drm_atomic_helper_update_plane,
 432         .disable_plane          = drm_atomic_helper_disable_plane,
 433         .destroy                = drm_plane_cleanup,
 434         .reset                  = drm_atomic_helper_plane_reset,
 435         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 436         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 437 };
 438
 439 static const u32 lcdif_primary_plane_formats[] = {
 440         DRM_FORMAT_RGB565,
 441         DRM_FORMAT_RGB888,
 442         DRM_FORMAT_XBGR8888,
 443         DRM_FORMAT_XRGB1555,
 444         DRM_FORMAT_XRGB4444,
 445         DRM_FORMAT_XRGB8888,
 446 };
 447
 448 static const u64 lcdif_modifiers[] = {
 449         DRM_FORMAT_MOD_LINEAR,
 450         DRM_FORMAT_MOD_INVALID
 451 };
 452
 453 /* -----------------------------------------------------------------------------
 454  * Initialization
 455  */
 456
 457 int lcdif_kms_init(struct lcdif_drm_private *lcdif)
 458 {
 459         struct drm_encoder *encoder = &lcdif->encoder;
 460         struct drm_crtc *crtc = &lcdif->crtc;
 461         int ret;
 462
 463         drm_plane_helper_add(&lcdif->planes.primary,
 464                              &lcdif_plane_primary_helper_funcs);
 465         ret = drm_universal_plane_init(lcdif->drm, &lcdif->planes.primary, 1,
 466                                        &lcdif_plane_funcs,
 467                                        lcdif_primary_plane_formats,
 468                                        ARRAY_SIZE(lcdif_primary_plane_formats),
 469                                        lcdif_modifiers, DRM_PLANE_TYPE_PRIMARY,
 470                                        NULL);
 471         if (ret)
 472                 return ret;
 473
 474         drm_crtc_helper_add(crtc, &lcdif_crtc_helper_funcs);
 475         ret = drm_crtc_init_with_planes(lcdif->drm, crtc,
 476                                         &lcdif->planes.primary, NULL,
 477                                         &lcdif_crtc_funcs, NULL);
 478         if (ret)
 479                 return ret;
 480
 481         encoder->possible_crtcs = drm_crtc_mask(crtc);
 482         return drm_encoder_init(lcdif->drm, encoder, &lcdif_encoder_funcs,
 483                                 DRM_MODE_ENCODER_NONE, NULL);
 484 }