1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/kthread.h>
9 #include <uapi/linux/sched/types.h>
10 #include <drm/drm_of.h>
13 #include "msm_debugfs.h"
14 #include "msm_fence.h"
18 #include "adreno/adreno_gpu.h"
23 * - 1.0.0 - initial interface
24 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
25 * - 1.2.0 - adds explicit fence support for submit ioctl
26 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
27 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
29 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
30 * GEM object's debug name
31 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
33 #define MSM_VERSION_MAJOR 1
34 #define MSM_VERSION_MINOR 5
35 #define MSM_VERSION_PATCHLEVEL 0
37 static const struct drm_mode_config_funcs mode_config_funcs = {
38 .fb_create = msm_framebuffer_create,
39 .output_poll_changed = drm_fb_helper_output_poll_changed,
40 .atomic_check = drm_atomic_helper_check,
41 .atomic_commit = drm_atomic_helper_commit,
44 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
45 .atomic_commit_tail = msm_atomic_commit_tail,
48 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
49 static bool reglog = false;
50 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
51 module_param(reglog, bool, 0600);
56 #ifdef CONFIG_DRM_FBDEV_EMULATION
57 static bool fbdev = true;
58 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
59 module_param(fbdev, bool, 0600);
62 static char *vram = "16m";
63 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
64 module_param(vram, charp, 0);
66 bool dumpstate = false;
67 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
68 module_param(dumpstate, bool, 0600);
70 static bool modeset = true;
71 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
72 module_param(modeset, bool, 0600);
78 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
80 struct property *prop;
82 struct clk_bulk_data *local;
83 int i = 0, ret, count;
85 count = of_property_count_strings(dev->of_node, "clock-names");
89 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
94 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
95 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
97 devm_kfree(dev, local);
104 ret = devm_clk_bulk_get(dev, count, local);
107 for (i = 0; i < count; i++)
108 devm_kfree(dev, (void *) local[i].id);
109 devm_kfree(dev, local);
118 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
124 snprintf(n, sizeof(n), "%s_clk", name);
126 for (i = 0; bulk && i < count; i++) {
127 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
135 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
140 clk = devm_clk_get(&pdev->dev, name);
141 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
144 snprintf(name2, sizeof(name2), "%s_clk", name);
146 clk = devm_clk_get(&pdev->dev, name2);
148 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
149 "\"%s\" instead of \"%s\"\n", name, name2);
154 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
157 struct resource *res;
162 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
167 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
168 return ERR_PTR(-EINVAL);
171 size = resource_size(res);
173 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
175 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
176 return ERR_PTR(-ENOMEM);
180 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
185 void msm_writel(u32 data, void __iomem *addr)
188 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
192 u32 msm_readl(const void __iomem *addr)
194 u32 val = readl(addr);
196 pr_err("IO:R %p %08x\n", addr, val);
200 struct msm_vblank_work {
201 struct work_struct work;
204 struct msm_drm_private *priv;
207 static void vblank_ctrl_worker(struct work_struct *work)
209 struct msm_vblank_work *vbl_work = container_of(work,
210 struct msm_vblank_work, work);
211 struct msm_drm_private *priv = vbl_work->priv;
212 struct msm_kms *kms = priv->kms;
214 if (vbl_work->enable)
215 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
217 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
222 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
223 int crtc_id, bool enable)
225 struct msm_vblank_work *vbl_work;
227 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
231 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
233 vbl_work->crtc_id = crtc_id;
234 vbl_work->enable = enable;
235 vbl_work->priv = priv;
237 queue_work(priv->wq, &vbl_work->work);
242 static int msm_drm_uninit(struct device *dev)
244 struct platform_device *pdev = to_platform_device(dev);
245 struct drm_device *ddev = platform_get_drvdata(pdev);
246 struct msm_drm_private *priv = ddev->dev_private;
247 struct msm_kms *kms = priv->kms;
248 struct msm_mdss *mdss = priv->mdss;
251 /* We must cancel and cleanup any pending vblank enable/disable
252 * work before drm_irq_uninstall() to avoid work re-enabling an
253 * irq after uninstall has disabled it.
256 flush_workqueue(priv->wq);
257 destroy_workqueue(priv->wq);
259 /* clean up event worker threads */
260 for (i = 0; i < priv->num_crtcs; i++) {
261 if (priv->event_thread[i].thread) {
262 kthread_destroy_worker(&priv->event_thread[i].worker);
263 priv->event_thread[i].thread = NULL;
267 msm_gem_shrinker_cleanup(ddev);
269 drm_kms_helper_poll_fini(ddev);
271 drm_dev_unregister(ddev);
273 msm_perf_debugfs_cleanup(priv);
274 msm_rd_debugfs_cleanup(priv);
276 #ifdef CONFIG_DRM_FBDEV_EMULATION
277 if (fbdev && priv->fbdev)
278 msm_fbdev_free(ddev);
280 drm_atomic_helper_shutdown(ddev);
281 drm_mode_config_cleanup(ddev);
283 pm_runtime_get_sync(dev);
284 drm_irq_uninstall(ddev);
285 pm_runtime_put_sync(dev);
287 if (kms && kms->funcs)
288 kms->funcs->destroy(kms);
290 if (priv->vram.paddr) {
291 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
292 drm_mm_takedown(&priv->vram.mm);
293 dma_free_attrs(dev, priv->vram.size, NULL,
294 priv->vram.paddr, attrs);
297 component_unbind_all(dev, ddev);
299 if (mdss && mdss->funcs)
300 mdss->funcs->destroy(ddev);
302 ddev->dev_private = NULL;
314 static int get_mdp_ver(struct platform_device *pdev)
316 struct device *dev = &pdev->dev;
318 return (int) (unsigned long) of_device_get_match_data(dev);
321 #include <linux/of_address.h>
323 bool msm_use_mmu(struct drm_device *dev)
325 struct msm_drm_private *priv = dev->dev_private;
327 /* a2xx comes with its own MMU */
328 return priv->is_a2xx || iommu_present(&platform_bus_type);
331 static int msm_init_vram(struct drm_device *dev)
333 struct msm_drm_private *priv = dev->dev_private;
334 struct device_node *node;
335 unsigned long size = 0;
338 /* In the device-tree world, we could have a 'memory-region'
339 * phandle, which gives us a link to our "vram". Allocating
340 * is all nicely abstracted behind the dma api, but we need
341 * to know the entire size to allocate it all in one go. There
343 * 1) device with no IOMMU, in which case we need exclusive
344 * access to a VRAM carveout big enough for all gpu
346 * 2) device with IOMMU, but where the bootloader puts up
347 * a splash screen. In this case, the VRAM carveout
348 * need only be large enough for fbdev fb. But we need
349 * exclusive access to the buffer to avoid the kernel
350 * using those pages for other purposes (which appears
351 * as corruption on screen before we have a chance to
352 * load and do initial modeset)
355 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
358 ret = of_address_to_resource(node, 0, &r);
362 size = r.end - r.start;
363 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
365 /* if we have no IOMMU, then we need to use carveout allocator.
366 * Grab the entire CMA chunk carved out in early startup in
369 } else if (!msm_use_mmu(dev)) {
370 DRM_INFO("using %s VRAM carveout\n", vram);
371 size = memparse(vram, NULL);
375 unsigned long attrs = 0;
378 priv->vram.size = size;
380 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
381 spin_lock_init(&priv->vram.lock);
383 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
384 attrs |= DMA_ATTR_WRITE_COMBINE;
386 /* note that for no-kernel-mapping, the vaddr returned
387 * is bogus, but non-null if allocation succeeded:
389 p = dma_alloc_attrs(dev->dev, size,
390 &priv->vram.paddr, GFP_KERNEL, attrs);
392 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
393 priv->vram.paddr = 0;
397 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
398 (uint32_t)priv->vram.paddr,
399 (uint32_t)(priv->vram.paddr + size));
405 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
407 struct platform_device *pdev = to_platform_device(dev);
408 struct drm_device *ddev;
409 struct msm_drm_private *priv;
411 struct msm_mdss *mdss;
413 struct sched_param param;
415 ddev = drm_dev_alloc(drv, dev);
417 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
418 return PTR_ERR(ddev);
421 platform_set_drvdata(pdev, ddev);
423 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
426 goto err_put_drm_dev;
429 ddev->dev_private = priv;
432 switch (get_mdp_ver(pdev)) {
434 ret = mdp5_mdss_init(ddev);
437 ret = dpu_mdss_init(ddev);
448 priv->wq = alloc_ordered_workqueue("msm", 0);
450 INIT_WORK(&priv->free_work, msm_gem_free_work);
451 init_llist_head(&priv->free_list);
453 INIT_LIST_HEAD(&priv->inactive_list);
455 drm_mode_config_init(ddev);
457 /* Bind all our sub-components: */
458 ret = component_bind_all(dev, ddev);
460 goto err_destroy_mdss;
462 ret = msm_init_vram(ddev);
466 msm_gem_shrinker_init(ddev);
468 switch (get_mdp_ver(pdev)) {
470 kms = mdp4_kms_init(ddev);
474 kms = mdp5_kms_init(ddev);
477 kms = dpu_kms_init(ddev);
481 /* valid only for the dummy headless case, where of_node=NULL */
482 WARN_ON(dev->of_node);
488 DRM_DEV_ERROR(dev, "failed to load kms\n");
494 /* Enable normalization of plane zpos */
495 ddev->mode_config.normalize_zpos = true;
498 ret = kms->funcs->hw_init(kms);
500 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
505 ddev->mode_config.funcs = &mode_config_funcs;
506 ddev->mode_config.helper_private = &mode_config_helper_funcs;
509 * this priority was found during empiric testing to have appropriate
510 * realtime scheduling to process display updates and interact with
511 * other real time and normal priority task
513 param.sched_priority = 16;
514 for (i = 0; i < priv->num_crtcs; i++) {
515 /* initialize event thread */
516 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
517 kthread_init_worker(&priv->event_thread[i].worker);
518 priv->event_thread[i].dev = ddev;
519 priv->event_thread[i].thread =
520 kthread_run(kthread_worker_fn,
521 &priv->event_thread[i].worker,
522 "crtc_event:%d", priv->event_thread[i].crtc_id);
523 if (IS_ERR(priv->event_thread[i].thread)) {
524 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
525 priv->event_thread[i].thread = NULL;
529 ret = sched_setscheduler(priv->event_thread[i].thread,
532 dev_warn(dev, "event_thread set priority failed:%d\n",
536 ret = drm_vblank_init(ddev, priv->num_crtcs);
538 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
543 pm_runtime_get_sync(dev);
544 ret = drm_irq_install(ddev, kms->irq);
545 pm_runtime_put_sync(dev);
547 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
552 ret = drm_dev_register(ddev, 0);
556 drm_mode_config_reset(ddev);
558 #ifdef CONFIG_DRM_FBDEV_EMULATION
560 priv->fbdev = msm_fbdev_init(ddev);
563 ret = msm_debugfs_late_init(ddev);
567 drm_kms_helper_poll_init(ddev);
575 if (mdss && mdss->funcs)
576 mdss->funcs->destroy(ddev);
588 static void load_gpu(struct drm_device *dev)
590 static DEFINE_MUTEX(init_lock);
591 struct msm_drm_private *priv = dev->dev_private;
593 mutex_lock(&init_lock);
596 priv->gpu = adreno_load_gpu(dev);
598 mutex_unlock(&init_lock);
601 static int context_init(struct drm_device *dev, struct drm_file *file)
603 struct msm_file_private *ctx;
605 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
609 msm_submitqueue_init(dev, ctx);
611 file->driver_priv = ctx;
616 static int msm_open(struct drm_device *dev, struct drm_file *file)
618 /* For now, load gpu on open.. to avoid the requirement of having
619 * firmware in the initrd.
623 return context_init(dev, file);
626 static void context_close(struct msm_file_private *ctx)
628 msm_submitqueue_close(ctx);
632 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
634 struct msm_drm_private *priv = dev->dev_private;
635 struct msm_file_private *ctx = file->driver_priv;
637 mutex_lock(&dev->struct_mutex);
638 if (ctx == priv->lastctx)
639 priv->lastctx = NULL;
640 mutex_unlock(&dev->struct_mutex);
645 static irqreturn_t msm_irq(int irq, void *arg)
647 struct drm_device *dev = arg;
648 struct msm_drm_private *priv = dev->dev_private;
649 struct msm_kms *kms = priv->kms;
651 return kms->funcs->irq(kms);
654 static void msm_irq_preinstall(struct drm_device *dev)
656 struct msm_drm_private *priv = dev->dev_private;
657 struct msm_kms *kms = priv->kms;
659 kms->funcs->irq_preinstall(kms);
662 static int msm_irq_postinstall(struct drm_device *dev)
664 struct msm_drm_private *priv = dev->dev_private;
665 struct msm_kms *kms = priv->kms;
668 if (kms->funcs->irq_postinstall)
669 return kms->funcs->irq_postinstall(kms);
674 static void msm_irq_uninstall(struct drm_device *dev)
676 struct msm_drm_private *priv = dev->dev_private;
677 struct msm_kms *kms = priv->kms;
679 kms->funcs->irq_uninstall(kms);
682 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
684 struct msm_drm_private *priv = dev->dev_private;
685 struct msm_kms *kms = priv->kms;
688 DBG("dev=%p, crtc=%u", dev, pipe);
689 return vblank_ctrl_queue_work(priv, pipe, true);
692 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
694 struct msm_drm_private *priv = dev->dev_private;
695 struct msm_kms *kms = priv->kms;
698 DBG("dev=%p, crtc=%u", dev, pipe);
699 vblank_ctrl_queue_work(priv, pipe, false);
706 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
707 struct drm_file *file)
709 struct msm_drm_private *priv = dev->dev_private;
710 struct drm_msm_param *args = data;
713 /* for now, we just have 3d pipe.. eventually this would need to
714 * be more clever to dispatch to appropriate gpu module:
716 if (args->pipe != MSM_PIPE_3D0)
724 return gpu->funcs->get_param(gpu, args->param, &args->value);
727 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
728 struct drm_file *file)
730 struct drm_msm_gem_new *args = data;
732 if (args->flags & ~MSM_BO_FLAGS) {
733 DRM_ERROR("invalid flags: %08x\n", args->flags);
737 return msm_gem_new_handle(dev, file, args->size,
738 args->flags, &args->handle, NULL);
741 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
743 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
746 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
747 struct drm_file *file)
749 struct drm_msm_gem_cpu_prep *args = data;
750 struct drm_gem_object *obj;
751 ktime_t timeout = to_ktime(args->timeout);
754 if (args->op & ~MSM_PREP_FLAGS) {
755 DRM_ERROR("invalid op: %08x\n", args->op);
759 obj = drm_gem_object_lookup(file, args->handle);
763 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
765 drm_gem_object_put_unlocked(obj);
770 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
771 struct drm_file *file)
773 struct drm_msm_gem_cpu_fini *args = data;
774 struct drm_gem_object *obj;
777 obj = drm_gem_object_lookup(file, args->handle);
781 ret = msm_gem_cpu_fini(obj);
783 drm_gem_object_put_unlocked(obj);
788 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
789 struct drm_gem_object *obj, uint64_t *iova)
791 struct msm_drm_private *priv = dev->dev_private;
797 * Don't pin the memory here - just get an address so that userspace can
800 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
803 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
804 struct drm_file *file)
806 struct drm_msm_gem_info *args = data;
807 struct drm_gem_object *obj;
808 struct msm_gem_object *msm_obj;
814 switch (args->info) {
815 case MSM_INFO_GET_OFFSET:
816 case MSM_INFO_GET_IOVA:
817 /* value returned as immediate, not pointer, so len==0: */
821 case MSM_INFO_SET_NAME:
822 case MSM_INFO_GET_NAME:
828 obj = drm_gem_object_lookup(file, args->handle);
832 msm_obj = to_msm_bo(obj);
834 switch (args->info) {
835 case MSM_INFO_GET_OFFSET:
836 args->value = msm_gem_mmap_offset(obj);
838 case MSM_INFO_GET_IOVA:
839 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
841 case MSM_INFO_SET_NAME:
842 /* length check should leave room for terminating null: */
843 if (args->len >= sizeof(msm_obj->name)) {
847 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
849 msm_obj->name[0] = '\0';
853 msm_obj->name[args->len] = '\0';
854 for (i = 0; i < args->len; i++) {
855 if (!isprint(msm_obj->name[i])) {
856 msm_obj->name[i] = '\0';
861 case MSM_INFO_GET_NAME:
862 if (args->value && (args->len < strlen(msm_obj->name))) {
866 args->len = strlen(msm_obj->name);
868 if (copy_to_user(u64_to_user_ptr(args->value),
869 msm_obj->name, args->len))
875 drm_gem_object_put_unlocked(obj);
880 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
881 struct drm_file *file)
883 struct msm_drm_private *priv = dev->dev_private;
884 struct drm_msm_wait_fence *args = data;
885 ktime_t timeout = to_ktime(args->timeout);
886 struct msm_gpu_submitqueue *queue;
887 struct msm_gpu *gpu = priv->gpu;
891 DRM_ERROR("invalid pad: %08x\n", args->pad);
898 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
902 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
905 msm_submitqueue_put(queue);
909 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
910 struct drm_file *file)
912 struct drm_msm_gem_madvise *args = data;
913 struct drm_gem_object *obj;
916 switch (args->madv) {
917 case MSM_MADV_DONTNEED:
918 case MSM_MADV_WILLNEED:
924 ret = mutex_lock_interruptible(&dev->struct_mutex);
928 obj = drm_gem_object_lookup(file, args->handle);
934 ret = msm_gem_madvise(obj, args->madv);
936 args->retained = ret;
940 drm_gem_object_put(obj);
943 mutex_unlock(&dev->struct_mutex);
948 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
949 struct drm_file *file)
951 struct drm_msm_submitqueue *args = data;
953 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
956 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
957 args->flags, &args->id);
960 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
961 struct drm_file *file)
963 return msm_submitqueue_query(dev, file->driver_priv, data);
966 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
967 struct drm_file *file)
969 u32 id = *(u32 *) data;
971 return msm_submitqueue_remove(file->driver_priv, id);
974 static const struct drm_ioctl_desc msm_ioctls[] = {
975 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
977 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
979 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
980 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
981 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
982 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
983 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
984 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
985 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_AUTH|DRM_RENDER_ALLOW),
988 static const struct vm_operations_struct vm_ops = {
989 .fault = msm_gem_fault,
990 .open = drm_gem_vm_open,
991 .close = drm_gem_vm_close,
994 static const struct file_operations fops = {
995 .owner = THIS_MODULE,
997 .release = drm_release,
998 .unlocked_ioctl = drm_ioctl,
999 .compat_ioctl = drm_compat_ioctl,
1002 .llseek = no_llseek,
1003 .mmap = msm_gem_mmap,
1006 static struct drm_driver msm_driver = {
1007 .driver_features = DRIVER_GEM |
1013 .postclose = msm_postclose,
1014 .lastclose = drm_fb_helper_lastclose,
1015 .irq_handler = msm_irq,
1016 .irq_preinstall = msm_irq_preinstall,
1017 .irq_postinstall = msm_irq_postinstall,
1018 .irq_uninstall = msm_irq_uninstall,
1019 .enable_vblank = msm_enable_vblank,
1020 .disable_vblank = msm_disable_vblank,
1021 .gem_free_object_unlocked = msm_gem_free_object,
1022 .gem_vm_ops = &vm_ops,
1023 .dumb_create = msm_gem_dumb_create,
1024 .dumb_map_offset = msm_gem_dumb_map_offset,
1025 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1026 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1027 .gem_prime_export = drm_gem_prime_export,
1028 .gem_prime_import = drm_gem_prime_import,
1029 .gem_prime_pin = msm_gem_prime_pin,
1030 .gem_prime_unpin = msm_gem_prime_unpin,
1031 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1032 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1033 .gem_prime_vmap = msm_gem_prime_vmap,
1034 .gem_prime_vunmap = msm_gem_prime_vunmap,
1035 .gem_prime_mmap = msm_gem_prime_mmap,
1036 #ifdef CONFIG_DEBUG_FS
1037 .debugfs_init = msm_debugfs_init,
1039 .ioctls = msm_ioctls,
1040 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1043 .desc = "MSM Snapdragon DRM",
1045 .major = MSM_VERSION_MAJOR,
1046 .minor = MSM_VERSION_MINOR,
1047 .patchlevel = MSM_VERSION_PATCHLEVEL,
1050 #ifdef CONFIG_PM_SLEEP
1051 static int msm_pm_suspend(struct device *dev)
1053 struct drm_device *ddev = dev_get_drvdata(dev);
1054 struct msm_drm_private *priv = ddev->dev_private;
1056 if (WARN_ON(priv->pm_state))
1057 drm_atomic_state_put(priv->pm_state);
1059 priv->pm_state = drm_atomic_helper_suspend(ddev);
1060 if (IS_ERR(priv->pm_state)) {
1061 int ret = PTR_ERR(priv->pm_state);
1062 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1069 static int msm_pm_resume(struct device *dev)
1071 struct drm_device *ddev = dev_get_drvdata(dev);
1072 struct msm_drm_private *priv = ddev->dev_private;
1075 if (WARN_ON(!priv->pm_state))
1078 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1080 priv->pm_state = NULL;
1087 static int msm_runtime_suspend(struct device *dev)
1089 struct drm_device *ddev = dev_get_drvdata(dev);
1090 struct msm_drm_private *priv = ddev->dev_private;
1091 struct msm_mdss *mdss = priv->mdss;
1095 if (mdss && mdss->funcs)
1096 return mdss->funcs->disable(mdss);
1101 static int msm_runtime_resume(struct device *dev)
1103 struct drm_device *ddev = dev_get_drvdata(dev);
1104 struct msm_drm_private *priv = ddev->dev_private;
1105 struct msm_mdss *mdss = priv->mdss;
1109 if (mdss && mdss->funcs)
1110 return mdss->funcs->enable(mdss);
1116 static const struct dev_pm_ops msm_pm_ops = {
1117 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1118 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1122 * Componentized driver support:
1126 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1127 * so probably some room for some helpers
1129 static int compare_of(struct device *dev, void *data)
1131 return dev->of_node == data;
1135 * Identify what components need to be added by parsing what remote-endpoints
1136 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1137 * is no external component that we need to add since LVDS is within MDP4
1140 static int add_components_mdp(struct device *mdp_dev,
1141 struct component_match **matchptr)
1143 struct device_node *np = mdp_dev->of_node;
1144 struct device_node *ep_node;
1145 struct device *master_dev;
1148 * on MDP4 based platforms, the MDP platform device is the component
1149 * master that adds other display interface components to itself.
1151 * on MDP5 based platforms, the MDSS platform device is the component
1152 * master that adds MDP5 and other display interface components to
1155 if (of_device_is_compatible(np, "qcom,mdp4"))
1156 master_dev = mdp_dev;
1158 master_dev = mdp_dev->parent;
1160 for_each_endpoint_of_node(np, ep_node) {
1161 struct device_node *intf;
1162 struct of_endpoint ep;
1165 ret = of_graph_parse_endpoint(ep_node, &ep);
1167 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1168 of_node_put(ep_node);
1173 * The LCDC/LVDS port on MDP4 is a speacial case where the
1174 * remote-endpoint isn't a component that we need to add
1176 if (of_device_is_compatible(np, "qcom,mdp4") &&
1181 * It's okay if some of the ports don't have a remote endpoint
1182 * specified. It just means that the port isn't connected to
1183 * any external interface.
1185 intf = of_graph_get_remote_port_parent(ep_node);
1189 if (of_device_is_available(intf))
1190 drm_of_component_match_add(master_dev, matchptr,
1199 static int compare_name_mdp(struct device *dev, void *data)
1201 return (strstr(dev_name(dev), "mdp") != NULL);
1204 static int add_display_components(struct device *dev,
1205 struct component_match **matchptr)
1207 struct device *mdp_dev;
1211 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1212 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1213 * Populate the children devices, find the MDP5/DPU node, and then add
1214 * the interfaces to our components list.
1216 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1217 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1218 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1220 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1224 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1226 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1227 of_platform_depopulate(dev);
1231 put_device(mdp_dev);
1233 /* add the MDP component itself */
1234 drm_of_component_match_add(dev, matchptr, compare_of,
1241 ret = add_components_mdp(mdp_dev, matchptr);
1243 of_platform_depopulate(dev);
1249 * We don't know what's the best binding to link the gpu with the drm device.
1250 * Fow now, we just hunt for all the possible gpus that we support, and add them
1253 static const struct of_device_id msm_gpu_match[] = {
1254 { .compatible = "qcom,adreno" },
1255 { .compatible = "qcom,adreno-3xx" },
1256 { .compatible = "amd,imageon" },
1257 { .compatible = "qcom,kgsl-3d0" },
1261 static int add_gpu_components(struct device *dev,
1262 struct component_match **matchptr)
1264 struct device_node *np;
1266 np = of_find_matching_node(NULL, msm_gpu_match);
1270 drm_of_component_match_add(dev, matchptr, compare_of, np);
1277 static int msm_drm_bind(struct device *dev)
1279 return msm_drm_init(dev, &msm_driver);
1282 static void msm_drm_unbind(struct device *dev)
1284 msm_drm_uninit(dev);
1287 static const struct component_master_ops msm_drm_ops = {
1288 .bind = msm_drm_bind,
1289 .unbind = msm_drm_unbind,
1296 static int msm_pdev_probe(struct platform_device *pdev)
1298 struct component_match *match = NULL;
1301 if (get_mdp_ver(pdev)) {
1302 ret = add_display_components(&pdev->dev, &match);
1307 ret = add_gpu_components(&pdev->dev, &match);
1311 /* on all devices that I am aware of, iommu's which can map
1312 * any address the cpu can see are used:
1314 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1318 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1321 static int msm_pdev_remove(struct platform_device *pdev)
1323 component_master_del(&pdev->dev, &msm_drm_ops);
1324 of_platform_depopulate(&pdev->dev);
1329 static const struct of_device_id dt_match[] = {
1330 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1331 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1332 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1335 MODULE_DEVICE_TABLE(of, dt_match);
1337 static struct platform_driver msm_platform_driver = {
1338 .probe = msm_pdev_probe,
1339 .remove = msm_pdev_remove,
1342 .of_match_table = dt_match,
1347 static int __init msm_drm_register(void)
1357 msm_hdmi_register();
1359 return platform_driver_register(&msm_platform_driver);
1362 static void __exit msm_drm_unregister(void)
1365 platform_driver_unregister(&msm_platform_driver);
1366 msm_hdmi_unregister();
1367 adreno_unregister();
1368 msm_edp_unregister();
1369 msm_dsi_unregister();
1370 msm_mdp_unregister();
1371 msm_dpu_unregister();
1374 module_init(msm_drm_register);
1375 module_exit(msm_drm_unregister);
1377 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1378 MODULE_DESCRIPTION("MSM DRM Driver");
1379 MODULE_LICENSE("GPL");