2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
29 #include "adreno/adreno_gpu.h"
34 * - 1.0.0 - initial interface
35 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
36 * - 1.2.0 - adds explicit fence support for submit ioctl
37 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
38 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
40 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
41 * GEM object's debug name
42 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
44 #define MSM_VERSION_MAJOR 1
45 #define MSM_VERSION_MINOR 5
46 #define MSM_VERSION_PATCHLEVEL 0
48 static const struct drm_mode_config_funcs mode_config_funcs = {
49 .fb_create = msm_framebuffer_create,
50 .output_poll_changed = drm_fb_helper_output_poll_changed,
51 .atomic_check = drm_atomic_helper_check,
52 .atomic_commit = drm_atomic_helper_commit,
55 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
56 .atomic_commit_tail = msm_atomic_commit_tail,
59 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
60 static bool reglog = false;
61 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
62 module_param(reglog, bool, 0600);
67 #ifdef CONFIG_DRM_FBDEV_EMULATION
68 static bool fbdev = true;
69 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
70 module_param(fbdev, bool, 0600);
73 static char *vram = "16m";
74 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
75 module_param(vram, charp, 0);
77 bool dumpstate = false;
78 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
79 module_param(dumpstate, bool, 0600);
81 static bool modeset = true;
82 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
83 module_param(modeset, bool, 0600);
89 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
91 struct property *prop;
93 struct clk_bulk_data *local;
94 int i = 0, ret, count;
96 count = of_property_count_strings(dev->of_node, "clock-names");
100 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
105 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
106 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
108 devm_kfree(dev, local);
115 ret = devm_clk_bulk_get(dev, count, local);
118 for (i = 0; i < count; i++)
119 devm_kfree(dev, (void *) local[i].id);
120 devm_kfree(dev, local);
129 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
135 snprintf(n, sizeof(n), "%s_clk", name);
137 for (i = 0; bulk && i < count; i++) {
138 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
146 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
151 clk = devm_clk_get(&pdev->dev, name);
152 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
155 snprintf(name2, sizeof(name2), "%s_clk", name);
157 clk = devm_clk_get(&pdev->dev, name2);
159 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
160 "\"%s\" instead of \"%s\"\n", name, name2);
165 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
168 struct resource *res;
173 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
178 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
179 return ERR_PTR(-EINVAL);
182 size = resource_size(res);
184 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
186 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
187 return ERR_PTR(-ENOMEM);
191 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
196 void msm_writel(u32 data, void __iomem *addr)
199 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
203 u32 msm_readl(const void __iomem *addr)
205 u32 val = readl(addr);
207 pr_err("IO:R %p %08x\n", addr, val);
211 struct msm_vblank_work {
212 struct work_struct work;
215 struct msm_drm_private *priv;
218 static void vblank_ctrl_worker(struct work_struct *work)
220 struct msm_vblank_work *vbl_work = container_of(work,
221 struct msm_vblank_work, work);
222 struct msm_drm_private *priv = vbl_work->priv;
223 struct msm_kms *kms = priv->kms;
225 if (vbl_work->enable)
226 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
228 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
233 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
234 int crtc_id, bool enable)
236 struct msm_vblank_work *vbl_work;
238 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
242 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
244 vbl_work->crtc_id = crtc_id;
245 vbl_work->enable = enable;
246 vbl_work->priv = priv;
248 queue_work(priv->wq, &vbl_work->work);
253 static int msm_drm_uninit(struct device *dev)
255 struct platform_device *pdev = to_platform_device(dev);
256 struct drm_device *ddev = platform_get_drvdata(pdev);
257 struct msm_drm_private *priv = ddev->dev_private;
258 struct msm_kms *kms = priv->kms;
259 struct msm_mdss *mdss = priv->mdss;
262 /* We must cancel and cleanup any pending vblank enable/disable
263 * work before drm_irq_uninstall() to avoid work re-enabling an
264 * irq after uninstall has disabled it.
267 flush_workqueue(priv->wq);
268 destroy_workqueue(priv->wq);
270 /* clean up event worker threads */
271 for (i = 0; i < priv->num_crtcs; i++) {
272 if (priv->event_thread[i].thread) {
273 kthread_destroy_worker(&priv->event_thread[i].worker);
274 priv->event_thread[i].thread = NULL;
278 msm_gem_shrinker_cleanup(ddev);
280 drm_kms_helper_poll_fini(ddev);
282 drm_dev_unregister(ddev);
284 msm_perf_debugfs_cleanup(priv);
285 msm_rd_debugfs_cleanup(priv);
287 #ifdef CONFIG_DRM_FBDEV_EMULATION
288 if (fbdev && priv->fbdev)
289 msm_fbdev_free(ddev);
291 drm_atomic_helper_shutdown(ddev);
292 drm_mode_config_cleanup(ddev);
294 pm_runtime_get_sync(dev);
295 drm_irq_uninstall(ddev);
296 pm_runtime_put_sync(dev);
298 if (kms && kms->funcs)
299 kms->funcs->destroy(kms);
301 if (priv->vram.paddr) {
302 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
303 drm_mm_takedown(&priv->vram.mm);
304 dma_free_attrs(dev, priv->vram.size, NULL,
305 priv->vram.paddr, attrs);
308 component_unbind_all(dev, ddev);
310 if (mdss && mdss->funcs)
311 mdss->funcs->destroy(ddev);
313 ddev->dev_private = NULL;
325 static int get_mdp_ver(struct platform_device *pdev)
327 struct device *dev = &pdev->dev;
329 return (int) (unsigned long) of_device_get_match_data(dev);
332 #include <linux/of_address.h>
334 bool msm_use_mmu(struct drm_device *dev)
336 struct msm_drm_private *priv = dev->dev_private;
338 /* a2xx comes with its own MMU */
339 return priv->is_a2xx || iommu_present(&platform_bus_type);
342 static int msm_init_vram(struct drm_device *dev)
344 struct msm_drm_private *priv = dev->dev_private;
345 struct device_node *node;
346 unsigned long size = 0;
349 /* In the device-tree world, we could have a 'memory-region'
350 * phandle, which gives us a link to our "vram". Allocating
351 * is all nicely abstracted behind the dma api, but we need
352 * to know the entire size to allocate it all in one go. There
354 * 1) device with no IOMMU, in which case we need exclusive
355 * access to a VRAM carveout big enough for all gpu
357 * 2) device with IOMMU, but where the bootloader puts up
358 * a splash screen. In this case, the VRAM carveout
359 * need only be large enough for fbdev fb. But we need
360 * exclusive access to the buffer to avoid the kernel
361 * using those pages for other purposes (which appears
362 * as corruption on screen before we have a chance to
363 * load and do initial modeset)
366 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
369 ret = of_address_to_resource(node, 0, &r);
373 size = r.end - r.start;
374 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
376 /* if we have no IOMMU, then we need to use carveout allocator.
377 * Grab the entire CMA chunk carved out in early startup in
380 } else if (!msm_use_mmu(dev)) {
381 DRM_INFO("using %s VRAM carveout\n", vram);
382 size = memparse(vram, NULL);
386 unsigned long attrs = 0;
389 priv->vram.size = size;
391 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
392 spin_lock_init(&priv->vram.lock);
394 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
395 attrs |= DMA_ATTR_WRITE_COMBINE;
397 /* note that for no-kernel-mapping, the vaddr returned
398 * is bogus, but non-null if allocation succeeded:
400 p = dma_alloc_attrs(dev->dev, size,
401 &priv->vram.paddr, GFP_KERNEL, attrs);
403 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
404 priv->vram.paddr = 0;
408 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
409 (uint32_t)priv->vram.paddr,
410 (uint32_t)(priv->vram.paddr + size));
416 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
418 struct platform_device *pdev = to_platform_device(dev);
419 struct drm_device *ddev;
420 struct msm_drm_private *priv;
422 struct msm_mdss *mdss;
424 struct sched_param param;
426 ddev = drm_dev_alloc(drv, dev);
428 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
429 return PTR_ERR(ddev);
432 platform_set_drvdata(pdev, ddev);
434 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
437 goto err_put_drm_dev;
440 ddev->dev_private = priv;
443 switch (get_mdp_ver(pdev)) {
445 ret = mdp5_mdss_init(ddev);
448 ret = dpu_mdss_init(ddev);
459 priv->wq = alloc_ordered_workqueue("msm", 0);
461 INIT_WORK(&priv->free_work, msm_gem_free_work);
462 init_llist_head(&priv->free_list);
464 INIT_LIST_HEAD(&priv->inactive_list);
466 drm_mode_config_init(ddev);
468 /* Bind all our sub-components: */
469 ret = component_bind_all(dev, ddev);
471 goto err_destroy_mdss;
473 ret = msm_init_vram(ddev);
477 msm_gem_shrinker_init(ddev);
479 switch (get_mdp_ver(pdev)) {
481 kms = mdp4_kms_init(ddev);
485 kms = mdp5_kms_init(ddev);
488 kms = dpu_kms_init(ddev);
492 /* valid only for the dummy headless case, where of_node=NULL */
493 WARN_ON(dev->of_node);
499 DRM_DEV_ERROR(dev, "failed to load kms\n");
505 /* Enable normalization of plane zpos */
506 ddev->mode_config.normalize_zpos = true;
509 ret = kms->funcs->hw_init(kms);
511 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
516 ddev->mode_config.funcs = &mode_config_funcs;
517 ddev->mode_config.helper_private = &mode_config_helper_funcs;
520 * this priority was found during empiric testing to have appropriate
521 * realtime scheduling to process display updates and interact with
522 * other real time and normal priority task
524 param.sched_priority = 16;
525 for (i = 0; i < priv->num_crtcs; i++) {
526 /* initialize event thread */
527 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
528 kthread_init_worker(&priv->event_thread[i].worker);
529 priv->event_thread[i].dev = ddev;
530 priv->event_thread[i].thread =
531 kthread_run(kthread_worker_fn,
532 &priv->event_thread[i].worker,
533 "crtc_event:%d", priv->event_thread[i].crtc_id);
534 if (IS_ERR(priv->event_thread[i].thread)) {
535 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
536 priv->event_thread[i].thread = NULL;
540 ret = sched_setscheduler(priv->event_thread[i].thread,
543 dev_warn(dev, "event_thread set priority failed:%d\n",
547 ret = drm_vblank_init(ddev, priv->num_crtcs);
549 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
554 pm_runtime_get_sync(dev);
555 ret = drm_irq_install(ddev, kms->irq);
556 pm_runtime_put_sync(dev);
558 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
563 ret = drm_dev_register(ddev, 0);
567 drm_mode_config_reset(ddev);
569 #ifdef CONFIG_DRM_FBDEV_EMULATION
571 priv->fbdev = msm_fbdev_init(ddev);
574 ret = msm_debugfs_late_init(ddev);
578 drm_kms_helper_poll_init(ddev);
586 if (mdss && mdss->funcs)
587 mdss->funcs->destroy(ddev);
599 static void load_gpu(struct drm_device *dev)
601 static DEFINE_MUTEX(init_lock);
602 struct msm_drm_private *priv = dev->dev_private;
604 mutex_lock(&init_lock);
607 priv->gpu = adreno_load_gpu(dev);
609 mutex_unlock(&init_lock);
612 static int context_init(struct drm_device *dev, struct drm_file *file)
614 struct msm_file_private *ctx;
616 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
620 msm_submitqueue_init(dev, ctx);
622 file->driver_priv = ctx;
627 static int msm_open(struct drm_device *dev, struct drm_file *file)
629 /* For now, load gpu on open.. to avoid the requirement of having
630 * firmware in the initrd.
634 return context_init(dev, file);
637 static void context_close(struct msm_file_private *ctx)
639 msm_submitqueue_close(ctx);
643 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_file_private *ctx = file->driver_priv;
648 mutex_lock(&dev->struct_mutex);
649 if (ctx == priv->lastctx)
650 priv->lastctx = NULL;
651 mutex_unlock(&dev->struct_mutex);
656 static irqreturn_t msm_irq(int irq, void *arg)
658 struct drm_device *dev = arg;
659 struct msm_drm_private *priv = dev->dev_private;
660 struct msm_kms *kms = priv->kms;
662 return kms->funcs->irq(kms);
665 static void msm_irq_preinstall(struct drm_device *dev)
667 struct msm_drm_private *priv = dev->dev_private;
668 struct msm_kms *kms = priv->kms;
670 kms->funcs->irq_preinstall(kms);
673 static int msm_irq_postinstall(struct drm_device *dev)
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
679 if (kms->funcs->irq_postinstall)
680 return kms->funcs->irq_postinstall(kms);
685 static void msm_irq_uninstall(struct drm_device *dev)
687 struct msm_drm_private *priv = dev->dev_private;
688 struct msm_kms *kms = priv->kms;
690 kms->funcs->irq_uninstall(kms);
693 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
695 struct msm_drm_private *priv = dev->dev_private;
696 struct msm_kms *kms = priv->kms;
699 DBG("dev=%p, crtc=%u", dev, pipe);
700 return vblank_ctrl_queue_work(priv, pipe, true);
703 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
705 struct msm_drm_private *priv = dev->dev_private;
706 struct msm_kms *kms = priv->kms;
709 DBG("dev=%p, crtc=%u", dev, pipe);
710 vblank_ctrl_queue_work(priv, pipe, false);
717 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
718 struct drm_file *file)
720 struct msm_drm_private *priv = dev->dev_private;
721 struct drm_msm_param *args = data;
724 /* for now, we just have 3d pipe.. eventually this would need to
725 * be more clever to dispatch to appropriate gpu module:
727 if (args->pipe != MSM_PIPE_3D0)
735 return gpu->funcs->get_param(gpu, args->param, &args->value);
738 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
739 struct drm_file *file)
741 struct drm_msm_gem_new *args = data;
743 if (args->flags & ~MSM_BO_FLAGS) {
744 DRM_ERROR("invalid flags: %08x\n", args->flags);
748 return msm_gem_new_handle(dev, file, args->size,
749 args->flags, &args->handle, NULL);
752 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
754 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
757 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
758 struct drm_file *file)
760 struct drm_msm_gem_cpu_prep *args = data;
761 struct drm_gem_object *obj;
762 ktime_t timeout = to_ktime(args->timeout);
765 if (args->op & ~MSM_PREP_FLAGS) {
766 DRM_ERROR("invalid op: %08x\n", args->op);
770 obj = drm_gem_object_lookup(file, args->handle);
774 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
776 drm_gem_object_put_unlocked(obj);
781 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
782 struct drm_file *file)
784 struct drm_msm_gem_cpu_fini *args = data;
785 struct drm_gem_object *obj;
788 obj = drm_gem_object_lookup(file, args->handle);
792 ret = msm_gem_cpu_fini(obj);
794 drm_gem_object_put_unlocked(obj);
799 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
800 struct drm_gem_object *obj, uint64_t *iova)
802 struct msm_drm_private *priv = dev->dev_private;
808 * Don't pin the memory here - just get an address so that userspace can
811 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
814 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
815 struct drm_file *file)
817 struct drm_msm_gem_info *args = data;
818 struct drm_gem_object *obj;
819 struct msm_gem_object *msm_obj;
825 switch (args->info) {
826 case MSM_INFO_GET_OFFSET:
827 case MSM_INFO_GET_IOVA:
828 /* value returned as immediate, not pointer, so len==0: */
832 case MSM_INFO_SET_NAME:
833 case MSM_INFO_GET_NAME:
839 obj = drm_gem_object_lookup(file, args->handle);
843 msm_obj = to_msm_bo(obj);
845 switch (args->info) {
846 case MSM_INFO_GET_OFFSET:
847 args->value = msm_gem_mmap_offset(obj);
849 case MSM_INFO_GET_IOVA:
850 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
852 case MSM_INFO_SET_NAME:
853 /* length check should leave room for terminating null: */
854 if (args->len >= sizeof(msm_obj->name)) {
858 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
860 msm_obj->name[0] = '\0';
864 msm_obj->name[args->len] = '\0';
865 for (i = 0; i < args->len; i++) {
866 if (!isprint(msm_obj->name[i])) {
867 msm_obj->name[i] = '\0';
872 case MSM_INFO_GET_NAME:
873 if (args->value && (args->len < strlen(msm_obj->name))) {
877 args->len = strlen(msm_obj->name);
879 if (copy_to_user(u64_to_user_ptr(args->value),
880 msm_obj->name, args->len))
886 drm_gem_object_put_unlocked(obj);
891 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
892 struct drm_file *file)
894 struct msm_drm_private *priv = dev->dev_private;
895 struct drm_msm_wait_fence *args = data;
896 ktime_t timeout = to_ktime(args->timeout);
897 struct msm_gpu_submitqueue *queue;
898 struct msm_gpu *gpu = priv->gpu;
902 DRM_ERROR("invalid pad: %08x\n", args->pad);
909 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
913 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
916 msm_submitqueue_put(queue);
920 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
921 struct drm_file *file)
923 struct drm_msm_gem_madvise *args = data;
924 struct drm_gem_object *obj;
927 switch (args->madv) {
928 case MSM_MADV_DONTNEED:
929 case MSM_MADV_WILLNEED:
935 ret = mutex_lock_interruptible(&dev->struct_mutex);
939 obj = drm_gem_object_lookup(file, args->handle);
945 ret = msm_gem_madvise(obj, args->madv);
947 args->retained = ret;
951 drm_gem_object_put(obj);
954 mutex_unlock(&dev->struct_mutex);
959 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
960 struct drm_file *file)
962 struct drm_msm_submitqueue *args = data;
964 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
967 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
968 args->flags, &args->id);
971 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
972 struct drm_file *file)
974 return msm_submitqueue_query(dev, file->driver_priv, data);
977 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
978 struct drm_file *file)
980 u32 id = *(u32 *) data;
982 return msm_submitqueue_remove(file->driver_priv, id);
985 static const struct drm_ioctl_desc msm_ioctls[] = {
986 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
987 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
988 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
989 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
990 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
991 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
992 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
993 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
995 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_AUTH|DRM_RENDER_ALLOW),
999 static const struct vm_operations_struct vm_ops = {
1000 .fault = msm_gem_fault,
1001 .open = drm_gem_vm_open,
1002 .close = drm_gem_vm_close,
1005 static const struct file_operations fops = {
1006 .owner = THIS_MODULE,
1008 .release = drm_release,
1009 .unlocked_ioctl = drm_ioctl,
1010 .compat_ioctl = drm_compat_ioctl,
1013 .llseek = no_llseek,
1014 .mmap = msm_gem_mmap,
1017 static struct drm_driver msm_driver = {
1018 .driver_features = DRIVER_GEM |
1024 .postclose = msm_postclose,
1025 .lastclose = drm_fb_helper_lastclose,
1026 .irq_handler = msm_irq,
1027 .irq_preinstall = msm_irq_preinstall,
1028 .irq_postinstall = msm_irq_postinstall,
1029 .irq_uninstall = msm_irq_uninstall,
1030 .enable_vblank = msm_enable_vblank,
1031 .disable_vblank = msm_disable_vblank,
1032 .gem_free_object_unlocked = msm_gem_free_object,
1033 .gem_vm_ops = &vm_ops,
1034 .dumb_create = msm_gem_dumb_create,
1035 .dumb_map_offset = msm_gem_dumb_map_offset,
1036 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1037 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1038 .gem_prime_export = drm_gem_prime_export,
1039 .gem_prime_import = drm_gem_prime_import,
1040 .gem_prime_pin = msm_gem_prime_pin,
1041 .gem_prime_unpin = msm_gem_prime_unpin,
1042 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1043 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1044 .gem_prime_vmap = msm_gem_prime_vmap,
1045 .gem_prime_vunmap = msm_gem_prime_vunmap,
1046 .gem_prime_mmap = msm_gem_prime_mmap,
1047 #ifdef CONFIG_DEBUG_FS
1048 .debugfs_init = msm_debugfs_init,
1050 .ioctls = msm_ioctls,
1051 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1054 .desc = "MSM Snapdragon DRM",
1056 .major = MSM_VERSION_MAJOR,
1057 .minor = MSM_VERSION_MINOR,
1058 .patchlevel = MSM_VERSION_PATCHLEVEL,
1061 #ifdef CONFIG_PM_SLEEP
1062 static int msm_pm_suspend(struct device *dev)
1064 struct drm_device *ddev = dev_get_drvdata(dev);
1065 struct msm_drm_private *priv = ddev->dev_private;
1067 if (WARN_ON(priv->pm_state))
1068 drm_atomic_state_put(priv->pm_state);
1070 priv->pm_state = drm_atomic_helper_suspend(ddev);
1071 if (IS_ERR(priv->pm_state)) {
1072 int ret = PTR_ERR(priv->pm_state);
1073 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1080 static int msm_pm_resume(struct device *dev)
1082 struct drm_device *ddev = dev_get_drvdata(dev);
1083 struct msm_drm_private *priv = ddev->dev_private;
1086 if (WARN_ON(!priv->pm_state))
1089 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1091 priv->pm_state = NULL;
1098 static int msm_runtime_suspend(struct device *dev)
1100 struct drm_device *ddev = dev_get_drvdata(dev);
1101 struct msm_drm_private *priv = ddev->dev_private;
1102 struct msm_mdss *mdss = priv->mdss;
1106 if (mdss && mdss->funcs)
1107 return mdss->funcs->disable(mdss);
1112 static int msm_runtime_resume(struct device *dev)
1114 struct drm_device *ddev = dev_get_drvdata(dev);
1115 struct msm_drm_private *priv = ddev->dev_private;
1116 struct msm_mdss *mdss = priv->mdss;
1120 if (mdss && mdss->funcs)
1121 return mdss->funcs->enable(mdss);
1127 static const struct dev_pm_ops msm_pm_ops = {
1128 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1129 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1133 * Componentized driver support:
1137 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1138 * so probably some room for some helpers
1140 static int compare_of(struct device *dev, void *data)
1142 return dev->of_node == data;
1146 * Identify what components need to be added by parsing what remote-endpoints
1147 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1148 * is no external component that we need to add since LVDS is within MDP4
1151 static int add_components_mdp(struct device *mdp_dev,
1152 struct component_match **matchptr)
1154 struct device_node *np = mdp_dev->of_node;
1155 struct device_node *ep_node;
1156 struct device *master_dev;
1159 * on MDP4 based platforms, the MDP platform device is the component
1160 * master that adds other display interface components to itself.
1162 * on MDP5 based platforms, the MDSS platform device is the component
1163 * master that adds MDP5 and other display interface components to
1166 if (of_device_is_compatible(np, "qcom,mdp4"))
1167 master_dev = mdp_dev;
1169 master_dev = mdp_dev->parent;
1171 for_each_endpoint_of_node(np, ep_node) {
1172 struct device_node *intf;
1173 struct of_endpoint ep;
1176 ret = of_graph_parse_endpoint(ep_node, &ep);
1178 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1179 of_node_put(ep_node);
1184 * The LCDC/LVDS port on MDP4 is a speacial case where the
1185 * remote-endpoint isn't a component that we need to add
1187 if (of_device_is_compatible(np, "qcom,mdp4") &&
1192 * It's okay if some of the ports don't have a remote endpoint
1193 * specified. It just means that the port isn't connected to
1194 * any external interface.
1196 intf = of_graph_get_remote_port_parent(ep_node);
1200 if (of_device_is_available(intf))
1201 drm_of_component_match_add(master_dev, matchptr,
1210 static int compare_name_mdp(struct device *dev, void *data)
1212 return (strstr(dev_name(dev), "mdp") != NULL);
1215 static int add_display_components(struct device *dev,
1216 struct component_match **matchptr)
1218 struct device *mdp_dev;
1222 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1223 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1224 * Populate the children devices, find the MDP5/DPU node, and then add
1225 * the interfaces to our components list.
1227 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1228 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1229 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1231 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1235 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1237 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1238 of_platform_depopulate(dev);
1242 put_device(mdp_dev);
1244 /* add the MDP component itself */
1245 drm_of_component_match_add(dev, matchptr, compare_of,
1252 ret = add_components_mdp(mdp_dev, matchptr);
1254 of_platform_depopulate(dev);
1260 * We don't know what's the best binding to link the gpu with the drm device.
1261 * Fow now, we just hunt for all the possible gpus that we support, and add them
1264 static const struct of_device_id msm_gpu_match[] = {
1265 { .compatible = "qcom,adreno" },
1266 { .compatible = "qcom,adreno-3xx" },
1267 { .compatible = "amd,imageon" },
1268 { .compatible = "qcom,kgsl-3d0" },
1272 static int add_gpu_components(struct device *dev,
1273 struct component_match **matchptr)
1275 struct device_node *np;
1277 np = of_find_matching_node(NULL, msm_gpu_match);
1281 drm_of_component_match_add(dev, matchptr, compare_of, np);
1288 static int msm_drm_bind(struct device *dev)
1290 return msm_drm_init(dev, &msm_driver);
1293 static void msm_drm_unbind(struct device *dev)
1295 msm_drm_uninit(dev);
1298 static const struct component_master_ops msm_drm_ops = {
1299 .bind = msm_drm_bind,
1300 .unbind = msm_drm_unbind,
1307 static int msm_pdev_probe(struct platform_device *pdev)
1309 struct component_match *match = NULL;
1312 if (get_mdp_ver(pdev)) {
1313 ret = add_display_components(&pdev->dev, &match);
1318 ret = add_gpu_components(&pdev->dev, &match);
1322 /* on all devices that I am aware of, iommu's which can map
1323 * any address the cpu can see are used:
1325 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1329 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1332 static int msm_pdev_remove(struct platform_device *pdev)
1334 component_master_del(&pdev->dev, &msm_drm_ops);
1335 of_platform_depopulate(&pdev->dev);
1340 static const struct of_device_id dt_match[] = {
1341 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1342 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1343 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1346 MODULE_DEVICE_TABLE(of, dt_match);
1348 static struct platform_driver msm_platform_driver = {
1349 .probe = msm_pdev_probe,
1350 .remove = msm_pdev_remove,
1353 .of_match_table = dt_match,
1358 static int __init msm_drm_register(void)
1368 msm_hdmi_register();
1370 return platform_driver_register(&msm_platform_driver);
1373 static void __exit msm_drm_unregister(void)
1376 platform_driver_unregister(&msm_platform_driver);
1377 msm_hdmi_unregister();
1378 adreno_unregister();
1379 msm_edp_unregister();
1380 msm_dsi_unregister();
1381 msm_mdp_unregister();
1382 msm_dpu_unregister();
1385 module_init(msm_drm_register);
1386 module_exit(msm_drm_unregister);
1388 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1389 MODULE_DESCRIPTION("MSM DRM Driver");
1390 MODULE_LICENSE("GPL");