1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/sched/mm.h>
11 #include <linux/uaccess.h>
12 #include <uapi/linux/sched/types.h>
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_irq.h>
18 #include <drm/drm_prime.h>
19 #include <drm/drm_of.h>
20 #include <drm/drm_vblank.h>
22 #include "disp/msm_disp_snapshot.h"
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
29 #include "adreno/adreno_gpu.h"
33 * - 1.0.0 - initial interface
34 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
35 * - 1.2.0 - adds explicit fence support for submit ioctl
36 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
37 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
39 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
40 * GEM object's debug name
41 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
42 * - 1.6.0 - Syncobj support
43 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
44 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
46 #define MSM_VERSION_MAJOR 1
47 #define MSM_VERSION_MINOR 8
48 #define MSM_VERSION_PATCHLEVEL 0
50 static const struct drm_mode_config_funcs mode_config_funcs = {
51 .fb_create = msm_framebuffer_create,
52 .output_poll_changed = drm_fb_helper_output_poll_changed,
53 .atomic_check = drm_atomic_helper_check,
54 .atomic_commit = drm_atomic_helper_commit,
57 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
58 .atomic_commit_tail = msm_atomic_commit_tail,
61 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
62 static bool reglog = false;
63 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
64 module_param(reglog, bool, 0600);
69 #ifdef CONFIG_DRM_FBDEV_EMULATION
70 static bool fbdev = true;
71 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
72 module_param(fbdev, bool, 0600);
75 static char *vram = "16m";
76 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
77 module_param(vram, charp, 0);
79 bool dumpstate = false;
80 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
81 module_param(dumpstate, bool, 0600);
83 static bool modeset = true;
84 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
85 module_param(modeset, bool, 0600);
91 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
97 snprintf(n, sizeof(n), "%s_clk", name);
99 for (i = 0; bulk && i < count; i++) {
100 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
108 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
113 clk = devm_clk_get(&pdev->dev, name);
114 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
117 snprintf(name2, sizeof(name2), "%s_clk", name);
119 clk = devm_clk_get(&pdev->dev, name2);
121 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
122 "\"%s\" instead of \"%s\"\n", name, name2);
127 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
128 const char *dbgname, bool quiet, phys_addr_t *psize)
130 struct resource *res;
135 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
141 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
142 return ERR_PTR(-EINVAL);
145 size = resource_size(res);
147 ptr = devm_ioremap(&pdev->dev, res->start, size);
150 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
151 return ERR_PTR(-ENOMEM);
155 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
163 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
166 return _msm_ioremap(pdev, name, dbgname, false, NULL);
169 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
172 return _msm_ioremap(pdev, name, dbgname, true, NULL);
175 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
176 const char *dbgname, phys_addr_t *psize)
178 return _msm_ioremap(pdev, name, dbgname, false, psize);
181 void msm_writel(u32 data, void __iomem *addr)
184 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
188 u32 msm_readl(const void __iomem *addr)
190 u32 val = readl(addr);
192 pr_err("IO:R %p %08x\n", addr, val);
196 void msm_rmw(void __iomem *addr, u32 mask, u32 or)
198 u32 val = msm_readl(addr);
201 msm_writel(val | or, addr);
204 struct msm_vblank_work {
205 struct work_struct work;
208 struct msm_drm_private *priv;
211 static void vblank_ctrl_worker(struct work_struct *work)
213 struct msm_vblank_work *vbl_work = container_of(work,
214 struct msm_vblank_work, work);
215 struct msm_drm_private *priv = vbl_work->priv;
216 struct msm_kms *kms = priv->kms;
218 if (vbl_work->enable)
219 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
221 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
226 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
227 int crtc_id, bool enable)
229 struct msm_vblank_work *vbl_work;
231 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
235 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
237 vbl_work->crtc_id = crtc_id;
238 vbl_work->enable = enable;
239 vbl_work->priv = priv;
241 queue_work(priv->wq, &vbl_work->work);
246 static int msm_drm_uninit(struct device *dev)
248 struct platform_device *pdev = to_platform_device(dev);
249 struct drm_device *ddev = platform_get_drvdata(pdev);
250 struct msm_drm_private *priv = ddev->dev_private;
251 struct msm_kms *kms = priv->kms;
252 struct msm_mdss *mdss = priv->mdss;
256 * Shutdown the hw if we're far enough along where things might be on.
257 * If we run this too early, we'll end up panicking in any variety of
258 * places. Since we don't register the drm device until late in
259 * msm_drm_init, drm_dev->registered is used as an indicator that the
260 * shutdown will be successful.
262 if (ddev->registered) {
263 drm_dev_unregister(ddev);
264 drm_atomic_helper_shutdown(ddev);
267 /* We must cancel and cleanup any pending vblank enable/disable
268 * work before drm_irq_uninstall() to avoid work re-enabling an
269 * irq after uninstall has disabled it.
272 flush_workqueue(priv->wq);
274 /* clean up event worker threads */
275 for (i = 0; i < priv->num_crtcs; i++) {
276 if (priv->event_thread[i].worker)
277 kthread_destroy_worker(priv->event_thread[i].worker);
280 msm_gem_shrinker_cleanup(ddev);
282 drm_kms_helper_poll_fini(ddev);
284 msm_perf_debugfs_cleanup(priv);
285 msm_rd_debugfs_cleanup(priv);
287 #ifdef CONFIG_DRM_FBDEV_EMULATION
288 if (fbdev && priv->fbdev)
289 msm_fbdev_free(ddev);
292 msm_disp_snapshot_destroy(ddev);
294 drm_mode_config_cleanup(ddev);
296 pm_runtime_get_sync(dev);
297 drm_irq_uninstall(ddev);
298 pm_runtime_put_sync(dev);
300 if (kms && kms->funcs)
301 kms->funcs->destroy(kms);
303 if (priv->vram.paddr) {
304 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
305 drm_mm_takedown(&priv->vram.mm);
306 dma_free_attrs(dev, priv->vram.size, NULL,
307 priv->vram.paddr, attrs);
310 component_unbind_all(dev, ddev);
312 if (mdss && mdss->funcs)
313 mdss->funcs->destroy(ddev);
315 ddev->dev_private = NULL;
318 destroy_workqueue(priv->wq);
328 static int get_mdp_ver(struct platform_device *pdev)
330 struct device *dev = &pdev->dev;
332 return (int) (unsigned long) of_device_get_match_data(dev);
335 #include <linux/of_address.h>
337 bool msm_use_mmu(struct drm_device *dev)
339 struct msm_drm_private *priv = dev->dev_private;
341 /* a2xx comes with its own MMU */
342 return priv->is_a2xx || iommu_present(&platform_bus_type);
345 static int msm_init_vram(struct drm_device *dev)
347 struct msm_drm_private *priv = dev->dev_private;
348 struct device_node *node;
349 unsigned long size = 0;
352 /* In the device-tree world, we could have a 'memory-region'
353 * phandle, which gives us a link to our "vram". Allocating
354 * is all nicely abstracted behind the dma api, but we need
355 * to know the entire size to allocate it all in one go. There
357 * 1) device with no IOMMU, in which case we need exclusive
358 * access to a VRAM carveout big enough for all gpu
360 * 2) device with IOMMU, but where the bootloader puts up
361 * a splash screen. In this case, the VRAM carveout
362 * need only be large enough for fbdev fb. But we need
363 * exclusive access to the buffer to avoid the kernel
364 * using those pages for other purposes (which appears
365 * as corruption on screen before we have a chance to
366 * load and do initial modeset)
369 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
372 ret = of_address_to_resource(node, 0, &r);
376 size = r.end - r.start;
377 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
379 /* if we have no IOMMU, then we need to use carveout allocator.
380 * Grab the entire CMA chunk carved out in early startup in
383 } else if (!msm_use_mmu(dev)) {
384 DRM_INFO("using %s VRAM carveout\n", vram);
385 size = memparse(vram, NULL);
389 unsigned long attrs = 0;
392 priv->vram.size = size;
394 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
395 spin_lock_init(&priv->vram.lock);
397 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
398 attrs |= DMA_ATTR_WRITE_COMBINE;
400 /* note that for no-kernel-mapping, the vaddr returned
401 * is bogus, but non-null if allocation succeeded:
403 p = dma_alloc_attrs(dev->dev, size,
404 &priv->vram.paddr, GFP_KERNEL, attrs);
406 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
407 priv->vram.paddr = 0;
411 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
412 (uint32_t)priv->vram.paddr,
413 (uint32_t)(priv->vram.paddr + size));
419 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
421 struct platform_device *pdev = to_platform_device(dev);
422 struct drm_device *ddev;
423 struct msm_drm_private *priv;
425 struct msm_mdss *mdss;
428 ddev = drm_dev_alloc(drv, dev);
430 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
431 return PTR_ERR(ddev);
434 platform_set_drvdata(pdev, ddev);
436 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
439 goto err_put_drm_dev;
442 ddev->dev_private = priv;
445 switch (get_mdp_ver(pdev)) {
447 ret = mdp5_mdss_init(ddev);
450 ret = dpu_mdss_init(ddev);
461 priv->wq = alloc_ordered_workqueue("msm", 0);
463 INIT_LIST_HEAD(&priv->objects);
464 mutex_init(&priv->obj_lock);
466 INIT_LIST_HEAD(&priv->inactive_willneed);
467 INIT_LIST_HEAD(&priv->inactive_dontneed);
468 INIT_LIST_HEAD(&priv->inactive_unpinned);
469 mutex_init(&priv->mm_lock);
471 /* Teach lockdep about lock ordering wrt. shrinker: */
472 fs_reclaim_acquire(GFP_KERNEL);
473 might_lock(&priv->mm_lock);
474 fs_reclaim_release(GFP_KERNEL);
476 drm_mode_config_init(ddev);
478 ret = msm_init_vram(ddev);
480 goto err_destroy_mdss;
482 /* Bind all our sub-components: */
483 ret = component_bind_all(dev, ddev);
485 goto err_destroy_mdss;
487 dma_set_max_seg_size(dev, UINT_MAX);
489 msm_gem_shrinker_init(ddev);
491 switch (get_mdp_ver(pdev)) {
493 kms = mdp4_kms_init(ddev);
497 kms = mdp5_kms_init(ddev);
500 kms = dpu_kms_init(ddev);
504 /* valid only for the dummy headless case, where of_node=NULL */
505 WARN_ON(dev->of_node);
511 DRM_DEV_ERROR(dev, "failed to load kms\n");
517 /* Enable normalization of plane zpos */
518 ddev->mode_config.normalize_zpos = true;
522 ret = kms->funcs->hw_init(kms);
524 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
529 ddev->mode_config.funcs = &mode_config_funcs;
530 ddev->mode_config.helper_private = &mode_config_helper_funcs;
532 for (i = 0; i < priv->num_crtcs; i++) {
533 /* initialize event thread */
534 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
535 priv->event_thread[i].dev = ddev;
536 priv->event_thread[i].worker = kthread_create_worker(0,
537 "crtc_event:%d", priv->event_thread[i].crtc_id);
538 if (IS_ERR(priv->event_thread[i].worker)) {
539 ret = PTR_ERR(priv->event_thread[i].worker);
540 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
544 sched_set_fifo(priv->event_thread[i].worker->task);
547 ret = drm_vblank_init(ddev, priv->num_crtcs);
549 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
554 pm_runtime_get_sync(dev);
555 ret = drm_irq_install(ddev, kms->irq);
556 pm_runtime_put_sync(dev);
558 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
563 ret = drm_dev_register(ddev, 0);
567 ret = msm_disp_snapshot_init(ddev);
569 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
571 drm_mode_config_reset(ddev);
573 #ifdef CONFIG_DRM_FBDEV_EMULATION
575 priv->fbdev = msm_fbdev_init(ddev);
578 ret = msm_debugfs_late_init(ddev);
582 drm_kms_helper_poll_init(ddev);
590 if (mdss && mdss->funcs)
591 mdss->funcs->destroy(ddev);
596 platform_set_drvdata(pdev, NULL);
604 static void load_gpu(struct drm_device *dev)
606 static DEFINE_MUTEX(init_lock);
607 struct msm_drm_private *priv = dev->dev_private;
609 mutex_lock(&init_lock);
612 priv->gpu = adreno_load_gpu(dev);
614 mutex_unlock(&init_lock);
617 static int context_init(struct drm_device *dev, struct drm_file *file)
619 struct msm_drm_private *priv = dev->dev_private;
620 struct msm_file_private *ctx;
622 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
626 kref_init(&ctx->ref);
627 msm_submitqueue_init(dev, ctx);
629 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
630 file->driver_priv = ctx;
635 static int msm_open(struct drm_device *dev, struct drm_file *file)
637 /* For now, load gpu on open.. to avoid the requirement of having
638 * firmware in the initrd.
642 return context_init(dev, file);
645 static void context_close(struct msm_file_private *ctx)
647 msm_submitqueue_close(ctx);
648 msm_file_private_put(ctx);
651 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
653 struct msm_drm_private *priv = dev->dev_private;
654 struct msm_file_private *ctx = file->driver_priv;
656 mutex_lock(&dev->struct_mutex);
657 if (ctx == priv->lastctx)
658 priv->lastctx = NULL;
659 mutex_unlock(&dev->struct_mutex);
664 static irqreturn_t msm_irq(int irq, void *arg)
666 struct drm_device *dev = arg;
667 struct msm_drm_private *priv = dev->dev_private;
668 struct msm_kms *kms = priv->kms;
670 return kms->funcs->irq(kms);
673 static void msm_irq_preinstall(struct drm_device *dev)
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
678 kms->funcs->irq_preinstall(kms);
681 static int msm_irq_postinstall(struct drm_device *dev)
683 struct msm_drm_private *priv = dev->dev_private;
684 struct msm_kms *kms = priv->kms;
687 if (kms->funcs->irq_postinstall)
688 return kms->funcs->irq_postinstall(kms);
693 static void msm_irq_uninstall(struct drm_device *dev)
695 struct msm_drm_private *priv = dev->dev_private;
696 struct msm_kms *kms = priv->kms;
698 kms->funcs->irq_uninstall(kms);
701 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
703 struct drm_device *dev = crtc->dev;
704 unsigned int pipe = crtc->index;
705 struct msm_drm_private *priv = dev->dev_private;
706 struct msm_kms *kms = priv->kms;
709 drm_dbg_vbl(dev, "crtc=%u", pipe);
710 return vblank_ctrl_queue_work(priv, pipe, true);
713 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
715 struct drm_device *dev = crtc->dev;
716 unsigned int pipe = crtc->index;
717 struct msm_drm_private *priv = dev->dev_private;
718 struct msm_kms *kms = priv->kms;
721 drm_dbg_vbl(dev, "crtc=%u", pipe);
722 vblank_ctrl_queue_work(priv, pipe, false);
729 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
730 struct drm_file *file)
732 struct msm_drm_private *priv = dev->dev_private;
733 struct drm_msm_param *args = data;
736 /* for now, we just have 3d pipe.. eventually this would need to
737 * be more clever to dispatch to appropriate gpu module:
739 if (args->pipe != MSM_PIPE_3D0)
747 return gpu->funcs->get_param(gpu, args->param, &args->value);
750 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
751 struct drm_file *file)
753 struct drm_msm_gem_new *args = data;
755 if (args->flags & ~MSM_BO_FLAGS) {
756 DRM_ERROR("invalid flags: %08x\n", args->flags);
760 return msm_gem_new_handle(dev, file, args->size,
761 args->flags, &args->handle, NULL);
764 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
766 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
769 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
770 struct drm_file *file)
772 struct drm_msm_gem_cpu_prep *args = data;
773 struct drm_gem_object *obj;
774 ktime_t timeout = to_ktime(args->timeout);
777 if (args->op & ~MSM_PREP_FLAGS) {
778 DRM_ERROR("invalid op: %08x\n", args->op);
782 obj = drm_gem_object_lookup(file, args->handle);
786 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
788 drm_gem_object_put(obj);
793 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
794 struct drm_file *file)
796 struct drm_msm_gem_cpu_fini *args = data;
797 struct drm_gem_object *obj;
800 obj = drm_gem_object_lookup(file, args->handle);
804 ret = msm_gem_cpu_fini(obj);
806 drm_gem_object_put(obj);
811 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
812 struct drm_file *file, struct drm_gem_object *obj,
815 struct msm_drm_private *priv = dev->dev_private;
816 struct msm_file_private *ctx = file->driver_priv;
822 * Don't pin the memory here - just get an address so that userspace can
825 return msm_gem_get_iova(obj, ctx->aspace, iova);
828 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
829 struct drm_file *file)
831 struct drm_msm_gem_info *args = data;
832 struct drm_gem_object *obj;
833 struct msm_gem_object *msm_obj;
839 switch (args->info) {
840 case MSM_INFO_GET_OFFSET:
841 case MSM_INFO_GET_IOVA:
842 /* value returned as immediate, not pointer, so len==0: */
846 case MSM_INFO_SET_NAME:
847 case MSM_INFO_GET_NAME:
853 obj = drm_gem_object_lookup(file, args->handle);
857 msm_obj = to_msm_bo(obj);
859 switch (args->info) {
860 case MSM_INFO_GET_OFFSET:
861 args->value = msm_gem_mmap_offset(obj);
863 case MSM_INFO_GET_IOVA:
864 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
866 case MSM_INFO_SET_NAME:
867 /* length check should leave room for terminating null: */
868 if (args->len >= sizeof(msm_obj->name)) {
872 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
874 msm_obj->name[0] = '\0';
878 msm_obj->name[args->len] = '\0';
879 for (i = 0; i < args->len; i++) {
880 if (!isprint(msm_obj->name[i])) {
881 msm_obj->name[i] = '\0';
886 case MSM_INFO_GET_NAME:
887 if (args->value && (args->len < strlen(msm_obj->name))) {
891 args->len = strlen(msm_obj->name);
893 if (copy_to_user(u64_to_user_ptr(args->value),
894 msm_obj->name, args->len))
900 drm_gem_object_put(obj);
905 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
906 struct drm_file *file)
908 struct msm_drm_private *priv = dev->dev_private;
909 struct drm_msm_wait_fence *args = data;
910 ktime_t timeout = to_ktime(args->timeout);
911 struct msm_gpu_submitqueue *queue;
912 struct msm_gpu *gpu = priv->gpu;
916 DRM_ERROR("invalid pad: %08x\n", args->pad);
923 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
927 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
930 msm_submitqueue_put(queue);
934 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
935 struct drm_file *file)
937 struct drm_msm_gem_madvise *args = data;
938 struct drm_gem_object *obj;
941 switch (args->madv) {
942 case MSM_MADV_DONTNEED:
943 case MSM_MADV_WILLNEED:
949 obj = drm_gem_object_lookup(file, args->handle);
954 ret = msm_gem_madvise(obj, args->madv);
956 args->retained = ret;
960 drm_gem_object_put(obj);
966 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
967 struct drm_file *file)
969 struct drm_msm_submitqueue *args = data;
971 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
974 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
975 args->flags, &args->id);
978 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
979 struct drm_file *file)
981 return msm_submitqueue_query(dev, file->driver_priv, data);
984 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
985 struct drm_file *file)
987 u32 id = *(u32 *) data;
989 return msm_submitqueue_remove(file->driver_priv, id);
992 static const struct drm_ioctl_desc msm_ioctls[] = {
993 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
994 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
995 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
996 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
997 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
998 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
999 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1001 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1003 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1006 static const struct file_operations fops = {
1007 .owner = THIS_MODULE,
1009 .release = drm_release,
1010 .unlocked_ioctl = drm_ioctl,
1011 .compat_ioctl = drm_compat_ioctl,
1014 .llseek = no_llseek,
1015 .mmap = msm_gem_mmap,
1018 static const struct drm_driver msm_driver = {
1019 .driver_features = DRIVER_GEM |
1025 .postclose = msm_postclose,
1026 .lastclose = drm_fb_helper_lastclose,
1027 .irq_handler = msm_irq,
1028 .irq_preinstall = msm_irq_preinstall,
1029 .irq_postinstall = msm_irq_postinstall,
1030 .irq_uninstall = msm_irq_uninstall,
1031 .dumb_create = msm_gem_dumb_create,
1032 .dumb_map_offset = msm_gem_dumb_map_offset,
1033 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1034 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1035 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1036 .gem_prime_mmap = msm_gem_prime_mmap,
1037 #ifdef CONFIG_DEBUG_FS
1038 .debugfs_init = msm_debugfs_init,
1040 .ioctls = msm_ioctls,
1041 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1044 .desc = "MSM Snapdragon DRM",
1046 .major = MSM_VERSION_MAJOR,
1047 .minor = MSM_VERSION_MINOR,
1048 .patchlevel = MSM_VERSION_PATCHLEVEL,
1051 static int __maybe_unused msm_runtime_suspend(struct device *dev)
1053 struct drm_device *ddev = dev_get_drvdata(dev);
1054 struct msm_drm_private *priv = ddev->dev_private;
1055 struct msm_mdss *mdss = priv->mdss;
1059 if (mdss && mdss->funcs)
1060 return mdss->funcs->disable(mdss);
1065 static int __maybe_unused msm_runtime_resume(struct device *dev)
1067 struct drm_device *ddev = dev_get_drvdata(dev);
1068 struct msm_drm_private *priv = ddev->dev_private;
1069 struct msm_mdss *mdss = priv->mdss;
1073 if (mdss && mdss->funcs)
1074 return mdss->funcs->enable(mdss);
1079 static int __maybe_unused msm_pm_suspend(struct device *dev)
1082 if (pm_runtime_suspended(dev))
1085 return msm_runtime_suspend(dev);
1088 static int __maybe_unused msm_pm_resume(struct device *dev)
1090 if (pm_runtime_suspended(dev))
1093 return msm_runtime_resume(dev);
1096 static int __maybe_unused msm_pm_prepare(struct device *dev)
1098 struct drm_device *ddev = dev_get_drvdata(dev);
1099 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1101 if (!priv || !priv->kms)
1104 return drm_mode_config_helper_suspend(ddev);
1107 static void __maybe_unused msm_pm_complete(struct device *dev)
1109 struct drm_device *ddev = dev_get_drvdata(dev);
1110 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL;
1112 if (!priv || !priv->kms)
1115 drm_mode_config_helper_resume(ddev);
1118 static const struct dev_pm_ops msm_pm_ops = {
1119 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1120 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1121 .prepare = msm_pm_prepare,
1122 .complete = msm_pm_complete,
1126 * Componentized driver support:
1130 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1131 * so probably some room for some helpers
1133 static int compare_of(struct device *dev, void *data)
1135 return dev->of_node == data;
1139 * Identify what components need to be added by parsing what remote-endpoints
1140 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1141 * is no external component that we need to add since LVDS is within MDP4
1144 static int add_components_mdp(struct device *mdp_dev,
1145 struct component_match **matchptr)
1147 struct device_node *np = mdp_dev->of_node;
1148 struct device_node *ep_node;
1149 struct device *master_dev;
1152 * on MDP4 based platforms, the MDP platform device is the component
1153 * master that adds other display interface components to itself.
1155 * on MDP5 based platforms, the MDSS platform device is the component
1156 * master that adds MDP5 and other display interface components to
1159 if (of_device_is_compatible(np, "qcom,mdp4"))
1160 master_dev = mdp_dev;
1162 master_dev = mdp_dev->parent;
1164 for_each_endpoint_of_node(np, ep_node) {
1165 struct device_node *intf;
1166 struct of_endpoint ep;
1169 ret = of_graph_parse_endpoint(ep_node, &ep);
1171 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1172 of_node_put(ep_node);
1177 * The LCDC/LVDS port on MDP4 is a speacial case where the
1178 * remote-endpoint isn't a component that we need to add
1180 if (of_device_is_compatible(np, "qcom,mdp4") &&
1185 * It's okay if some of the ports don't have a remote endpoint
1186 * specified. It just means that the port isn't connected to
1187 * any external interface.
1189 intf = of_graph_get_remote_port_parent(ep_node);
1193 if (of_device_is_available(intf))
1194 drm_of_component_match_add(master_dev, matchptr,
1203 static int compare_name_mdp(struct device *dev, void *data)
1205 return (strstr(dev_name(dev), "mdp") != NULL);
1208 static int add_display_components(struct platform_device *pdev,
1209 struct component_match **matchptr)
1211 struct device *mdp_dev;
1212 struct device *dev = &pdev->dev;
1216 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1217 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1218 * Populate the children devices, find the MDP5/DPU node, and then add
1219 * the interfaces to our components list.
1221 switch (get_mdp_ver(pdev)) {
1224 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1226 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1230 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1232 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1233 of_platform_depopulate(dev);
1237 put_device(mdp_dev);
1239 /* add the MDP component itself */
1240 drm_of_component_match_add(dev, matchptr, compare_of,
1249 ret = add_components_mdp(mdp_dev, matchptr);
1251 of_platform_depopulate(dev);
1257 * We don't know what's the best binding to link the gpu with the drm device.
1258 * Fow now, we just hunt for all the possible gpus that we support, and add them
1261 static const struct of_device_id msm_gpu_match[] = {
1262 { .compatible = "qcom,adreno" },
1263 { .compatible = "qcom,adreno-3xx" },
1264 { .compatible = "amd,imageon" },
1265 { .compatible = "qcom,kgsl-3d0" },
1269 static int add_gpu_components(struct device *dev,
1270 struct component_match **matchptr)
1272 struct device_node *np;
1274 np = of_find_matching_node(NULL, msm_gpu_match);
1278 if (of_device_is_available(np))
1279 drm_of_component_match_add(dev, matchptr, compare_of, np);
1286 static int msm_drm_bind(struct device *dev)
1288 return msm_drm_init(dev, &msm_driver);
1291 static void msm_drm_unbind(struct device *dev)
1293 msm_drm_uninit(dev);
1296 static const struct component_master_ops msm_drm_ops = {
1297 .bind = msm_drm_bind,
1298 .unbind = msm_drm_unbind,
1305 static int msm_pdev_probe(struct platform_device *pdev)
1307 struct component_match *match = NULL;
1310 if (get_mdp_ver(pdev)) {
1311 ret = add_display_components(pdev, &match);
1316 ret = add_gpu_components(&pdev->dev, &match);
1320 /* on all devices that I am aware of, iommu's which can map
1321 * any address the cpu can see are used:
1323 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1327 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1334 of_platform_depopulate(&pdev->dev);
1338 static int msm_pdev_remove(struct platform_device *pdev)
1340 component_master_del(&pdev->dev, &msm_drm_ops);
1341 of_platform_depopulate(&pdev->dev);
1346 static void msm_pdev_shutdown(struct platform_device *pdev)
1348 struct drm_device *drm = platform_get_drvdata(pdev);
1349 struct msm_drm_private *priv = drm ? drm->dev_private : NULL;
1351 if (!priv || !priv->kms)
1354 drm_atomic_helper_shutdown(drm);
1357 static const struct of_device_id dt_match[] = {
1358 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1359 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1360 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1361 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1362 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
1363 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
1364 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
1367 MODULE_DEVICE_TABLE(of, dt_match);
1369 static struct platform_driver msm_platform_driver = {
1370 .probe = msm_pdev_probe,
1371 .remove = msm_pdev_remove,
1372 .shutdown = msm_pdev_shutdown,
1375 .of_match_table = dt_match,
1380 static int __init msm_drm_register(void)
1390 msm_hdmi_register();
1393 return platform_driver_register(&msm_platform_driver);
1396 static void __exit msm_drm_unregister(void)
1399 platform_driver_unregister(&msm_platform_driver);
1400 msm_dp_unregister();
1401 msm_hdmi_unregister();
1402 adreno_unregister();
1403 msm_edp_unregister();
1404 msm_dsi_unregister();
1405 msm_mdp_unregister();
1406 msm_dpu_unregister();
1409 module_init(msm_drm_register);
1410 module_exit(msm_drm_unregister);
1412 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1413 MODULE_DESCRIPTION("MSM DRM Driver");
1414 MODULE_LICENSE("GPL");