4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
31 Copyright (C) 2013-2021 by the following authors:
32 - Rob Clark <robdclark@gmail.com> (robclark)
33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
35 Permission is hereby granted, free of charge, to any person obtaining
36 a copy of this software and associated documentation files (the
37 "Software"), to deal in the Software without restriction, including
38 without limitation the rights to use, copy, modify, merge, publish,
39 distribute, sublicense, and/or sell copies of the Software, and to
40 permit persons to whom the Software is furnished to do so, subject to
41 the following conditions:
43 The above copyright notice and this permission notice (including the
44 next paragraph) shall be included in all copies or substantial
45 portions of the Software.
47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
57 enum hdmi_hdcp_key_state {
58 HDCP_KEYS_STATE_NO_KEYS = 0,
59 HDCP_KEYS_STATE_NOT_CHECKED = 1,
60 HDCP_KEYS_STATE_CHECKING = 2,
61 HDCP_KEYS_STATE_VALID = 3,
62 HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
63 HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
64 HDCP_KEYS_STATE_PROD_AKSV = 6,
65 HDCP_KEYS_STATE_RESERVED = 7,
68 enum hdmi_ddc_read_write {
80 #define REG_HDMI_CTRL 0x00000000
81 #define HDMI_CTRL_ENABLE 0x00000001
82 #define HDMI_CTRL_HDMI 0x00000002
83 #define HDMI_CTRL_ENCRYPTED 0x00000004
85 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
86 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
88 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
89 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001
90 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002
91 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
92 #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4
93 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
95 return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
97 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
98 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
99 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16
100 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
102 return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
104 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
106 #define REG_HDMI_VBI_PKT_CTRL 0x00000028
107 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
108 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
109 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
110 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
111 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
112 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
114 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
115 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
116 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
117 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
118 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
119 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
120 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
122 #define REG_HDMI_INFOFRAME_CTRL1 0x00000030
123 #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
124 #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
125 static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
127 return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
129 #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
130 #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
131 static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
133 return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
135 #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
136 #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
137 static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
139 return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
141 #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
142 #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
143 static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
145 return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
148 #define REG_HDMI_GEN_PKT_CTRL 0x00000034
149 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
150 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
151 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
152 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2
153 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
155 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
157 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
158 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
159 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
160 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16
161 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
163 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
165 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
166 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24
167 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
169 return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
172 #define REG_HDMI_GC 0x00000040
173 #define HDMI_GC_MUTE 0x00000001
175 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
176 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
177 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
179 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
181 #define REG_HDMI_GENERIC0_HDR 0x00000084
183 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
185 #define REG_HDMI_GENERIC1_HDR 0x000000a4
187 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
189 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
191 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
192 #define HDMI_ACR_0_CTS__MASK 0xfffff000
193 #define HDMI_ACR_0_CTS__SHIFT 12
194 static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
196 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
199 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
200 #define HDMI_ACR_1_N__MASK 0xffffffff
201 #define HDMI_ACR_1_N__SHIFT 0
202 static inline uint32_t HDMI_ACR_1_N(uint32_t val)
204 return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
207 #define REG_HDMI_AUDIO_INFO0 0x000000e4
208 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
209 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
210 static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
212 return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
214 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
215 #define HDMI_AUDIO_INFO0_CC__SHIFT 8
216 static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
218 return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
221 #define REG_HDMI_AUDIO_INFO1 0x000000e8
222 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
223 #define HDMI_AUDIO_INFO1_CA__SHIFT 0
224 static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
226 return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
228 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
229 #define HDMI_AUDIO_INFO1_LSV__SHIFT 11
230 static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
232 return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
234 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000
236 #define REG_HDMI_HDCP_CTRL 0x00000110
237 #define HDMI_HDCP_CTRL_ENABLE 0x00000001
238 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
240 #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
241 #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
243 #define REG_HDMI_HDCP_INT_CTRL 0x00000118
244 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
245 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
246 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
247 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
248 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
249 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
250 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
251 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
252 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
253 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
254 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
255 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
256 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
258 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
259 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
260 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
261 #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
262 #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
263 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
264 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28
265 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
267 return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
270 #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
271 #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
273 #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
274 #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
276 #define REG_HDMI_HDCP_DDC_STATUS 0x00000128
277 #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
278 #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
279 #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
280 #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
281 #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
282 #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
283 #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
285 #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
287 #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
289 #define REG_HDMI_HDCP_RESET 0x00000130
290 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
292 #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
294 #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
296 #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
298 #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
300 #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
302 #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
304 #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
306 #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
308 #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
310 #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
312 #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
314 #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
316 #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
318 #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
320 #define REG_HDMI_VENSPEC_INFO0 0x0000016c
322 #define REG_HDMI_VENSPEC_INFO1 0x00000170
324 #define REG_HDMI_VENSPEC_INFO2 0x00000174
326 #define REG_HDMI_VENSPEC_INFO3 0x00000178
328 #define REG_HDMI_VENSPEC_INFO4 0x0000017c
330 #define REG_HDMI_VENSPEC_INFO5 0x00000180
332 #define REG_HDMI_VENSPEC_INFO6 0x00000184
334 #define REG_HDMI_AUDIO_CFG 0x000001d0
335 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
336 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
337 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4
338 static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
340 return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
343 #define REG_HDMI_USEC_REFTIMER 0x00000208
345 #define REG_HDMI_DDC_CTRL 0x0000020c
346 #define HDMI_DDC_CTRL_GO 0x00000001
347 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
348 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004
349 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
350 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
351 #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20
352 static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
354 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
357 #define REG_HDMI_DDC_ARBITRATION 0x00000210
358 #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
360 #define REG_HDMI_DDC_INT_CTRL 0x00000214
361 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
362 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
363 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
365 #define REG_HDMI_DDC_SW_STATUS 0x00000218
366 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000
367 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000
368 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000
369 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000
371 #define REG_HDMI_DDC_HW_STATUS 0x0000021c
372 #define HDMI_DDC_HW_STATUS_DONE 0x00000008
374 #define REG_HDMI_DDC_SPEED 0x00000220
375 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
376 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
377 static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
379 return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
381 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
382 #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16
383 static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
385 return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
388 #define REG_HDMI_DDC_SETUP 0x00000224
389 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
390 #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24
391 static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
393 return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
396 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
398 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
399 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
400 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
401 static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
403 return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
405 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
406 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000
407 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
408 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
409 #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16
410 static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
412 return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
415 #define REG_HDMI_DDC_DATA 0x00000238
416 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
417 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0
418 static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
420 return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
422 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
423 #define HDMI_DDC_DATA_DATA__SHIFT 8
424 static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
426 return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
428 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
429 #define HDMI_DDC_DATA_INDEX__SHIFT 16
430 static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
432 return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
434 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
436 #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
438 #define REG_HDMI_HDCP_SHA_STATUS 0x00000240
439 #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
440 #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
442 #define REG_HDMI_HDCP_SHA_DATA 0x00000244
443 #define HDMI_HDCP_SHA_DATA_DONE 0x00000001
445 #define REG_HDMI_HPD_INT_STATUS 0x00000250
446 #define HDMI_HPD_INT_STATUS_INT 0x00000001
447 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
449 #define REG_HDMI_HPD_INT_CTRL 0x00000254
450 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
451 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
452 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
453 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
454 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
455 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
457 #define REG_HDMI_HPD_CTRL 0x00000258
458 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
459 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
460 static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
462 return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
464 #define HDMI_HPD_CTRL_ENABLE 0x10000000
466 #define REG_HDMI_DDC_REF 0x0000027c
467 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
468 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
469 #define HDMI_DDC_REF_REFTIMER__SHIFT 0
470 static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
472 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
475 #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
477 #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
479 #define REG_HDMI_CEC_CTRL 0x0000028c
481 #define REG_HDMI_CEC_WR_DATA 0x00000290
483 #define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
485 #define REG_HDMI_CEC_STATUS 0x00000298
487 #define REG_HDMI_CEC_INT 0x0000029c
489 #define REG_HDMI_CEC_ADDR 0x000002a0
491 #define REG_HDMI_CEC_TIME 0x000002a4
493 #define REG_HDMI_CEC_REFTIMER 0x000002a8
495 #define REG_HDMI_CEC_RD_DATA 0x000002ac
497 #define REG_HDMI_CEC_RD_FILTER 0x000002b0
499 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4
500 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
501 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0
502 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
504 return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
506 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
507 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16
508 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
510 return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
513 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8
514 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
515 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0
516 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
518 return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
520 #define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
521 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16
522 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
524 return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
527 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
528 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
529 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
530 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
532 return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
534 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
535 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
536 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
538 return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
541 #define REG_HDMI_TOTAL 0x000002c0
542 #define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
543 #define HDMI_TOTAL_H_TOTAL__SHIFT 0
544 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
546 return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
548 #define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
549 #define HDMI_TOTAL_V_TOTAL__SHIFT 16
550 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
552 return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
555 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
556 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
557 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
558 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
560 return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
563 #define REG_HDMI_FRAME_CTRL 0x000002c8
564 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
565 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
566 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
567 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
569 #define REG_HDMI_AUD_INT 0x000002cc
570 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
571 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
572 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
573 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
575 #define REG_HDMI_PHY_CTRL 0x000002d4
576 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
577 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
578 #define HDMI_PHY_CTRL_SW_RESET 0x00000004
579 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
581 #define REG_HDMI_CEC_WR_RANGE 0x000002dc
583 #define REG_HDMI_CEC_RD_RANGE 0x000002e0
585 #define REG_HDMI_VERSION 0x000002e4
587 #define REG_HDMI_CEC_COMPL_CTL 0x00000360
589 #define REG_HDMI_CEC_RD_START_RANGE 0x00000364
591 #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
593 #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
595 #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
597 #define REG_HDMI_8x60_PHY_REG0 0x00000000
598 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
599 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
600 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
602 return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
605 #define REG_HDMI_8x60_PHY_REG1 0x00000004
606 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
607 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
608 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
610 return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
612 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
613 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
614 static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
616 return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
619 #define REG_HDMI_8x60_PHY_REG2 0x00000008
620 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
621 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
622 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
623 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
624 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
625 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
626 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
627 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
629 #define REG_HDMI_8x60_PHY_REG3 0x0000000c
630 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
632 #define REG_HDMI_8x60_PHY_REG4 0x00000010
634 #define REG_HDMI_8x60_PHY_REG5 0x00000014
636 #define REG_HDMI_8x60_PHY_REG6 0x00000018
638 #define REG_HDMI_8x60_PHY_REG7 0x0000001c
640 #define REG_HDMI_8x60_PHY_REG8 0x00000020
642 #define REG_HDMI_8x60_PHY_REG9 0x00000024
644 #define REG_HDMI_8x60_PHY_REG10 0x00000028
646 #define REG_HDMI_8x60_PHY_REG11 0x0000002c
648 #define REG_HDMI_8x60_PHY_REG12 0x00000030
649 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
650 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
651 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
653 #define REG_HDMI_8960_PHY_REG0 0x00000000
655 #define REG_HDMI_8960_PHY_REG1 0x00000004
657 #define REG_HDMI_8960_PHY_REG2 0x00000008
659 #define REG_HDMI_8960_PHY_REG3 0x0000000c
661 #define REG_HDMI_8960_PHY_REG4 0x00000010
663 #define REG_HDMI_8960_PHY_REG5 0x00000014
665 #define REG_HDMI_8960_PHY_REG6 0x00000018
667 #define REG_HDMI_8960_PHY_REG7 0x0000001c
669 #define REG_HDMI_8960_PHY_REG8 0x00000020
671 #define REG_HDMI_8960_PHY_REG9 0x00000024
673 #define REG_HDMI_8960_PHY_REG10 0x00000028
675 #define REG_HDMI_8960_PHY_REG11 0x0000002c
677 #define REG_HDMI_8960_PHY_REG12 0x00000030
678 #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
679 #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
681 #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
683 #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
685 #define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
687 #define REG_HDMI_8960_PHY_REG13 0x00000040
689 #define REG_HDMI_8960_PHY_REG14 0x00000044
691 #define REG_HDMI_8960_PHY_REG15 0x00000048
693 #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
695 #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
697 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
699 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
701 #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
703 #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
705 #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
706 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
707 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
709 #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
711 #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
713 #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
715 #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
717 #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
719 #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
721 #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
723 #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
725 #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
727 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
729 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
731 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
733 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
735 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
737 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
739 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
741 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
743 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
745 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
747 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
749 #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
751 #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
753 #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
755 #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
757 #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
759 #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
761 #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
763 #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
765 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
767 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
769 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
771 #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
772 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
774 #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
776 #define REG_HDMI_8x74_ANA_CFG0 0x00000000
778 #define REG_HDMI_8x74_ANA_CFG1 0x00000004
780 #define REG_HDMI_8x74_PD_CTRL0 0x00000010
782 #define REG_HDMI_8x74_PD_CTRL1 0x00000014
784 #define REG_HDMI_8x74_BIST_CFG0 0x00000034
786 #define REG_HDMI_8x74_BIST_PATN0 0x0000003c
788 #define REG_HDMI_8x74_BIST_PATN1 0x00000040
790 #define REG_HDMI_8x74_BIST_PATN2 0x00000044
792 #define REG_HDMI_8x74_BIST_PATN3 0x00000048
794 #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
796 #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
798 #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
800 #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
802 #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
804 #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
806 #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
808 #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
810 #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
811 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
812 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
813 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
814 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
816 #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
818 #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
820 #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
822 #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
824 #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
826 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
828 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
830 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
832 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
834 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
836 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
838 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
840 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
842 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
844 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
846 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
848 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
850 #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
851 #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
853 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
855 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
857 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
859 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
861 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
863 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
865 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
867 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
869 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
871 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
873 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
875 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
877 #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
879 #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
881 #define REG_HDMI_8996_PHY_CFG 0x00000000
883 #define REG_HDMI_8996_PHY_PD_CTL 0x00000004
885 #define REG_HDMI_8996_PHY_MODE 0x00000008
887 #define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
889 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
891 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
893 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
895 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
897 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
899 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
901 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
903 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
905 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
907 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
909 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
911 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
913 #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
915 #define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
917 #define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
919 #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
921 #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
923 #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
925 #define REG_HDMI_8996_PHY_CLOCK 0x00000058
927 #define REG_HDMI_8996_PHY_MISC1 0x0000005c
929 #define REG_HDMI_8996_PHY_MISC2 0x00000060
931 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
933 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
935 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
937 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
939 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
941 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
943 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
945 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
947 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
949 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
951 #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
953 #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
955 #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
957 #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
959 #define REG_HDMI_8996_PHY_STATUS 0x0000009c
961 #define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
963 #define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
965 #define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
967 #define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
969 #define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
971 #define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
973 #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
975 #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
977 #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
979 #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
981 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
983 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
985 #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
987 #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
989 #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
991 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
993 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
995 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
997 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
999 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
1001 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
1003 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
1005 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
1007 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
1009 #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
1011 #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
1013 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
1015 #define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
1017 #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
1019 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
1021 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
1023 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
1025 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
1027 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
1029 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
1031 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
1033 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
1035 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
1037 #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
1039 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
1041 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
1043 #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
1045 #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
1047 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
1049 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
1051 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
1053 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
1055 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
1057 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
1059 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
1061 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
1063 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
1065 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
1067 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
1069 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
1071 #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
1073 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
1075 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
1077 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
1079 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
1081 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
1083 #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
1085 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
1087 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
1089 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
1091 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
1093 #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
1095 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
1097 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
1099 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
1101 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
1103 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
1105 #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
1107 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
1109 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
1111 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
1113 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
1115 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
1117 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
1119 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
1121 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
1123 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
1125 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
1127 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
1129 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
1131 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
1133 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
1135 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
1137 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
1139 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
1141 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
1143 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
1145 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
1147 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
1149 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
1151 #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
1153 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
1155 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
1157 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
1159 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
1161 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
1163 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
1165 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
1167 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
1169 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
1171 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
1173 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
1175 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
1177 #define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
1179 #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
1181 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
1183 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
1185 #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
1187 #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
1189 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
1191 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
1193 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
1195 #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
1197 #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
1199 #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
1201 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
1203 #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
1205 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
1207 #define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
1209 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
1211 #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
1213 #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
1215 #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
1217 #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
1219 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
1221 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
1223 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
1225 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
1227 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
1229 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
1231 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
1233 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
1235 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
1237 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
1239 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
1241 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
1243 #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
1245 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
1247 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
1249 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
1251 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
1253 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
1255 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
1257 #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
1259 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
1261 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
1263 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
1265 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
1267 #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
1269 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
1271 #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
1273 #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
1275 #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
1277 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
1279 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
1281 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
1283 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
1285 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
1287 #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
1289 #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
1291 #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
1293 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
1295 #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
1297 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
1299 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
1301 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
1303 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
1305 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
1307 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
1309 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
1311 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
1313 #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
1315 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
1317 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
1319 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
1321 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
1323 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
1325 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
1327 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
1329 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
1331 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
1333 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
1335 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
1337 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
1339 #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
1341 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
1343 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
1345 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
1347 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
1349 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
1351 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
1353 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
1355 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
1357 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
1359 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
1361 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
1363 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
1365 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
1367 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
1369 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
1371 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
1373 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
1375 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
1378 #endif /* HDMI_XML */