1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
13 * DSI PLL 28nm - clock diagram (eg: DSI0):
15 * dsi0analog_postdiv_clk
16 * | dsi0indirect_path_div2_clk
18 * +------+ | +----+ | |\ dsi0byte_mux
19 * dsi0vco_clk --o--| DIV1 |--o--| /2 |--o--| \ |
20 * | +------+ +----+ | m| | +----+
21 * | | u|--o--| /4 |-- dsi0pllbyte
23 * o--------------------------| /
26 * o----------| DIV3 |------------------------- dsi0pll
30 #define POLL_MAX_READS 10
31 #define POLL_TIMEOUT_US 50
33 #define NUM_PROVIDED_CLKS 2
35 #define VCO_REF_CLK_RATE 19200000
36 #define VCO_MIN_RATE 350000000
37 #define VCO_MAX_RATE 750000000
39 #define DSI_BYTE_PLL_CLK 0
40 #define DSI_PIXEL_PLL_CLK 1
42 #define LPFR_LUT_SIZE 10
44 unsigned long vco_rate;
48 /* Loop filter resistance: */
49 static const struct lpfr_cfg lpfr_lut[LPFR_LUT_SIZE] = {
62 struct pll_28nm_cached_state {
63 unsigned long vco_rate;
70 struct msm_dsi_pll base;
73 struct platform_device *pdev;
79 struct clk *clks[NUM_DSI_CLOCKS_MAX];
83 struct clk *provided_clks[NUM_PROVIDED_CLKS];
84 struct clk_onecell_data clk_data;
86 struct pll_28nm_cached_state cached_state;
89 #define to_pll_28nm(x) container_of(x, struct dsi_pll_28nm, base)
91 static bool pll_28nm_poll_for_ready(struct dsi_pll_28nm *pll_28nm,
92 u32 nb_tries, u32 timeout_us)
94 bool pll_locked = false;
98 val = pll_read(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_STATUS);
99 pll_locked = !!(val & DSI_28nm_PHY_PLL_STATUS_PLL_RDY);
106 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
111 static void pll_28nm_software_reset(struct dsi_pll_28nm *pll_28nm)
113 void __iomem *base = pll_28nm->mmio;
116 * Add HW recommended delays after toggling the software
117 * reset bit off and back on.
119 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG,
120 DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, 1);
121 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1);
127 static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
128 unsigned long parent_rate)
130 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
131 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
132 struct device *dev = &pll_28nm->pdev->dev;
133 void __iomem *base = pll_28nm->mmio;
134 unsigned long div_fbx1000, gen_vco_clk;
135 u32 refclk_cfg, frac_n_mode, frac_n_value;
136 u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
137 u32 cal_cfg10, cal_cfg11;
141 VERB("rate=%lu, parent's=%lu", rate, parent_rate);
143 /* Force postdiv2 to be div-4 */
144 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3);
146 /* Configure the Loop filter resistance */
147 for (i = 0; i < LPFR_LUT_SIZE; i++)
148 if (rate <= lpfr_lut[i].vco_rate)
150 if (i == LPFR_LUT_SIZE) {
151 DRM_DEV_ERROR(dev, "unable to get loop filter resistance. vco=%lu\n",
155 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance);
157 /* Loop filter capacitance values : c1 and c2 */
158 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
159 pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
161 rem = rate % VCO_REF_CLK_RATE;
163 refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
165 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
166 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
170 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
171 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
174 DBG("refclk_cfg = %d", refclk_cfg);
176 rem = div_fbx1000 % 1000;
177 frac_n_value = (rem << 16) / 1000;
179 DBG("div_fb = %lu", div_fbx1000);
180 DBG("frac_n_value = %d", frac_n_value);
182 DBG("Generated VCO Clock: %lu", gen_vco_clk);
184 sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
185 sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
188 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0);
189 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(
190 (u32)(((div_fbx1000 / 1000) & 0x3f) - 1));
191 sdm_cfg3 = frac_n_value >> 8;
192 sdm_cfg2 = frac_n_value & 0xff;
194 sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP;
195 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(
196 (u32)(((div_fbx1000 / 1000) & 0x3f) - 1));
197 sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0);
202 DBG("sdm_cfg0=%d", sdm_cfg0);
203 DBG("sdm_cfg1=%d", sdm_cfg1);
204 DBG("sdm_cfg2=%d", sdm_cfg2);
205 DBG("sdm_cfg3=%d", sdm_cfg3);
207 cal_cfg11 = (u32)(gen_vco_clk / (256 * 1000000));
208 cal_cfg10 = (u32)((gen_vco_clk % (256 * 1000000)) / 1000000);
209 DBG("cal_cfg10=%d, cal_cfg11=%d", cal_cfg10, cal_cfg11);
211 pll_write(base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG, 0x02);
212 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG3, 0x2b);
213 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG4, 0x06);
214 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
216 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);
217 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2,
218 DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(sdm_cfg2));
219 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3,
220 DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(sdm_cfg3));
221 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);
223 /* Add hardware recommended delay for correct PLL configuration */
224 if (pll_28nm->vco_delay)
225 udelay(pll_28nm->vco_delay);
227 pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);
228 pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00);
229 pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31);
230 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);
231 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12);
232 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG6, 0x30);
233 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG7, 0x00);
234 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG8, 0x60);
235 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG9, 0x00);
236 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff);
237 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG11, cal_cfg11 & 0xff);
238 pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20);
243 static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw)
245 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
246 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
248 return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS,
252 static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
253 unsigned long parent_rate)
255 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
256 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
257 void __iomem *base = pll_28nm->mmio;
258 u32 sdm0, doubler, sdm_byp_div;
259 u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
260 u32 ref_clk = VCO_REF_CLK_RATE;
261 unsigned long vco_rate;
263 VERB("parent_rate=%lu", parent_rate);
265 /* Check to see if the ref clk doubler is enabled */
266 doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
267 DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
268 ref_clk += (doubler * VCO_REF_CLK_RATE);
270 /* see if it is integer mode or sdm mode */
271 sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
272 if (sdm0 & DSI_28nm_PHY_PLL_SDM_CFG0_BYP) {
275 pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0),
276 DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV) + 1;
277 vco_rate = ref_clk * sdm_byp_div;
281 pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1),
282 DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET);
283 DBG("sdm_dc_off = %d", sdm_dc_off);
284 sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2),
285 DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0);
286 sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3),
287 DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8);
288 sdm_freq_seed = (sdm3 << 8) | sdm2;
289 DBG("sdm_freq_seed = %d", sdm_freq_seed);
291 vco_rate = (ref_clk * (sdm_dc_off + 1)) +
292 mult_frac(ref_clk, sdm_freq_seed, BIT(16));
293 DBG("vco rate = %lu", vco_rate);
296 DBG("returning vco rate = %lu", vco_rate);
301 static const struct clk_ops clk_ops_dsi_pll_28nm_vco = {
302 .round_rate = msm_dsi_pll_helper_clk_round_rate,
303 .set_rate = dsi_pll_28nm_clk_set_rate,
304 .recalc_rate = dsi_pll_28nm_clk_recalc_rate,
305 .prepare = msm_dsi_pll_helper_clk_prepare,
306 .unprepare = msm_dsi_pll_helper_clk_unprepare,
307 .is_enabled = dsi_pll_28nm_clk_is_enabled,
313 static int dsi_pll_28nm_enable_seq_hpm(struct msm_dsi_pll *pll)
315 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
316 struct device *dev = &pll_28nm->pdev->dev;
317 void __iomem *base = pll_28nm->mmio;
318 u32 max_reads = 5, timeout_us = 100;
323 DBG("id=%d", pll_28nm->id);
325 pll_28nm_software_reset(pll_28nm);
328 * PLL power up sequence.
329 * Add necessary delays recommended by hardware.
331 val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
332 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
334 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
335 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
337 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
338 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
340 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
341 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
343 for (i = 0; i < 2; i++) {
344 /* DSI Uniphy lock detect setting */
345 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2,
347 pll_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d);
349 /* poll for PLL ready status */
350 locked = pll_28nm_poll_for_ready(pll_28nm,
351 max_reads, timeout_us);
355 pll_28nm_software_reset(pll_28nm);
358 * PLL power up sequence.
359 * Add necessary delays recommended by hardware.
361 val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
362 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1);
364 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
365 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
367 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
368 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250);
370 val &= ~DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
371 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200);
373 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B;
374 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
376 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
377 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600);
380 if (unlikely(!locked))
381 DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
383 DBG("DSI PLL Lock success");
385 return locked ? 0 : -EINVAL;
388 static int dsi_pll_28nm_enable_seq_lp(struct msm_dsi_pll *pll)
390 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
391 struct device *dev = &pll_28nm->pdev->dev;
392 void __iomem *base = pll_28nm->mmio;
394 u32 max_reads = 10, timeout_us = 50;
397 DBG("id=%d", pll_28nm->id);
399 pll_28nm_software_reset(pll_28nm);
402 * PLL power up sequence.
403 * Add necessary delays recommended by hardware.
405 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500);
407 val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B;
408 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
410 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B;
411 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
413 val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B |
414 DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE;
415 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500);
417 /* DSI PLL toggle lock detect setting */
418 pll_write_ndelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x04, 500);
419 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x05, 512);
421 locked = pll_28nm_poll_for_ready(pll_28nm, max_reads, timeout_us);
423 if (unlikely(!locked))
424 DRM_DEV_ERROR(dev, "DSI PLL lock failed\n");
426 DBG("DSI PLL lock success");
428 return locked ? 0 : -EINVAL;
431 static void dsi_pll_28nm_disable_seq(struct msm_dsi_pll *pll)
433 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
435 DBG("id=%d", pll_28nm->id);
436 pll_write(pll_28nm->mmio + REG_DSI_28nm_PHY_PLL_GLB_CFG, 0x00);
439 static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
441 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
442 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
443 void __iomem *base = pll_28nm->mmio;
445 cached_state->postdiv3 =
446 pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG);
447 cached_state->postdiv1 =
448 pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
449 cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
450 if (dsi_pll_28nm_clk_is_enabled(&pll->clk_hw))
451 cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
453 cached_state->vco_rate = 0;
456 static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
458 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
459 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state;
460 void __iomem *base = pll_28nm->mmio;
463 ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
464 cached_state->vco_rate, 0);
466 DRM_DEV_ERROR(&pll_28nm->pdev->dev,
467 "restore vco rate failed. ret=%d\n", ret);
471 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
472 cached_state->postdiv3);
473 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
474 cached_state->postdiv1);
475 pll_write(base + REG_DSI_28nm_PHY_PLL_VREG_CFG,
476 cached_state->byte_mux);
481 static int dsi_pll_28nm_get_provider(struct msm_dsi_pll *pll,
482 struct clk **byte_clk_provider,
483 struct clk **pixel_clk_provider)
485 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
487 if (byte_clk_provider)
488 *byte_clk_provider = pll_28nm->provided_clks[DSI_BYTE_PLL_CLK];
489 if (pixel_clk_provider)
490 *pixel_clk_provider =
491 pll_28nm->provided_clks[DSI_PIXEL_PLL_CLK];
496 static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll)
498 struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
501 msm_dsi_pll_helper_unregister_clks(pll_28nm->pdev,
502 pll_28nm->clks, pll_28nm->num_clks);
504 for (i = 0; i < NUM_PROVIDED_CLKS; i++)
505 pll_28nm->provided_clks[i] = NULL;
507 pll_28nm->num_clks = 0;
508 pll_28nm->clk_data.clks = NULL;
509 pll_28nm->clk_data.clk_num = 0;
512 static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
514 char clk_name[32], parent1[32], parent2[32], vco_name[32];
515 struct clk_init_data vco_init = {
516 .parent_names = (const char *[]){ "xo" },
519 .flags = CLK_IGNORE_UNUSED,
520 .ops = &clk_ops_dsi_pll_28nm_vco,
522 struct device *dev = &pll_28nm->pdev->dev;
523 struct clk **clks = pll_28nm->clks;
524 struct clk **provided_clks = pll_28nm->provided_clks;
528 DBG("%d", pll_28nm->id);
530 snprintf(vco_name, 32, "dsi%dvco_clk", pll_28nm->id);
531 pll_28nm->base.clk_hw.init = &vco_init;
532 clks[num++] = clk_register(dev, &pll_28nm->base.clk_hw);
534 snprintf(clk_name, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
535 snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
536 clks[num++] = clk_register_divider(dev, clk_name,
537 parent1, CLK_SET_RATE_PARENT,
539 REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG,
542 snprintf(clk_name, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
543 snprintf(parent1, 32, "dsi%danalog_postdiv_clk", pll_28nm->id);
544 clks[num++] = clk_register_fixed_factor(dev, clk_name,
545 parent1, CLK_SET_RATE_PARENT,
548 snprintf(clk_name, 32, "dsi%dpll", pll_28nm->id);
549 snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
550 clks[num++] = provided_clks[DSI_PIXEL_PLL_CLK] =
551 clk_register_divider(dev, clk_name,
552 parent1, 0, pll_28nm->mmio +
553 REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG,
556 snprintf(clk_name, 32, "dsi%dbyte_mux", pll_28nm->id);
557 snprintf(parent1, 32, "dsi%dvco_clk", pll_28nm->id);
558 snprintf(parent2, 32, "dsi%dindirect_path_div2_clk", pll_28nm->id);
559 clks[num++] = clk_register_mux(dev, clk_name,
562 }), 2, CLK_SET_RATE_PARENT, pll_28nm->mmio +
563 REG_DSI_28nm_PHY_PLL_VREG_CFG, 1, 1, 0, NULL);
565 snprintf(clk_name, 32, "dsi%dpllbyte", pll_28nm->id);
566 snprintf(parent1, 32, "dsi%dbyte_mux", pll_28nm->id);
567 clks[num++] = provided_clks[DSI_BYTE_PLL_CLK] =
568 clk_register_fixed_factor(dev, clk_name,
569 parent1, CLK_SET_RATE_PARENT, 1, 4);
571 pll_28nm->num_clks = num;
573 pll_28nm->clk_data.clk_num = NUM_PROVIDED_CLKS;
574 pll_28nm->clk_data.clks = provided_clks;
576 ret = of_clk_add_provider(dev->of_node,
577 of_clk_src_onecell_get, &pll_28nm->clk_data);
579 DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
586 struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
587 enum msm_dsi_phy_type type, int id)
589 struct dsi_pll_28nm *pll_28nm;
590 struct msm_dsi_pll *pll;
594 return ERR_PTR(-ENODEV);
596 pll_28nm = devm_kzalloc(&pdev->dev, sizeof(*pll_28nm), GFP_KERNEL);
598 return ERR_PTR(-ENOMEM);
600 pll_28nm->pdev = pdev;
603 pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
604 if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
605 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map pll base\n", __func__);
606 return ERR_PTR(-ENOMEM);
609 pll = &pll_28nm->base;
610 pll->min_rate = VCO_MIN_RATE;
611 pll->max_rate = VCO_MAX_RATE;
612 pll->get_provider = dsi_pll_28nm_get_provider;
613 pll->destroy = dsi_pll_28nm_destroy;
614 pll->disable_seq = dsi_pll_28nm_disable_seq;
615 pll->save_state = dsi_pll_28nm_save_state;
616 pll->restore_state = dsi_pll_28nm_restore_state;
618 if (type == MSM_DSI_PHY_28NM_HPM) {
619 pll_28nm->vco_delay = 1;
622 pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_hpm;
623 pll->enable_seqs[1] = dsi_pll_28nm_enable_seq_hpm;
624 pll->enable_seqs[2] = dsi_pll_28nm_enable_seq_hpm;
625 } else if (type == MSM_DSI_PHY_28NM_LP) {
626 pll_28nm->vco_delay = 1000;
629 pll->enable_seqs[0] = dsi_pll_28nm_enable_seq_lp;
631 DRM_DEV_ERROR(&pdev->dev, "phy type (%d) is not 28nm\n", type);
632 return ERR_PTR(-EINVAL);
635 ret = pll_28nm_register(pll_28nm);
637 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);