drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0
   3  * Copyright (c) 2018, The Linux Foundation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/iopoll.h>
   9
  10 #include "dsi_phy.h"
  11 #include "dsi.xml.h"
  12
  13 /*
  14  * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
  15  *
  16  *           dsi0_pll_out_div_clk  dsi0_pll_bit_clk
  17  *                              |                |
  18  *                              |                |
  19  *                 +---------+  |  +----------+  |  +----+
  20  *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
  21  *                 +---------+  |  +----------+  |  +----+
  22  *                              |                |
  23  *                              |                |         dsi0_pll_by_2_bit_clk
  24  *                              |                |          |
  25  *                              |                |  +----+  |  |\  dsi0_pclk_mux
  26  *                              |                |--| /2 |--o--| \   |
  27  *                              |                |  +----+     |  \  |  +---------+
  28  *                              |                --------------|  |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
  29  *                              |------------------------------|  /     +---------+
  30  *                              |          +-----+             | /
  31  *                              -----------| /4? |--o----------|/
  32  *                                         +-----+  |           |
  33  *                                                  |           |dsiclk_sel
  34  *                                                  |
  35  *                                                  dsi0_pll_post_out_div_clk
  36  */
  37
  38 #define VCO_REF_CLK_RATE                19200000
  39
  40 struct dsi_pll_regs {
  41         u32 pll_prop_gain_rate;
  42         u32 pll_lockdet_rate;
  43         u32 decimal_div_start;
  44         u32 frac_div_start_low;
  45         u32 frac_div_start_mid;
  46         u32 frac_div_start_high;
  47         u32 pll_clock_inverters;
  48         u32 ssc_stepsize_low;
  49         u32 ssc_stepsize_high;
  50         u32 ssc_div_per_low;
  51         u32 ssc_div_per_high;
  52         u32 ssc_adjper_low;
  53         u32 ssc_adjper_high;
  54         u32 ssc_control;
  55 };
  56
  57 /* Hardware is V4.1 */
  58 #define DSI_PHY_7NM_QUIRK_V4_1          BIT(0)
  59
  60 struct dsi_pll_config {
  61         u32 ref_freq;
  62         bool div_override;
  63         u32 output_div;
  64         bool ignore_frac;
  65         bool disable_prescaler;
  66         bool enable_ssc;
  67         bool ssc_center;
  68         u32 dec_bits;
  69         u32 frac_bits;
  70         u32 lock_timer;
  71         u32 ssc_freq;
  72         u32 ssc_offset;
  73         u32 ssc_adj_per;
  74         u32 thresh_cycles;
  75         u32 refclk_cycles;
  76 };
  77
  78 struct pll_7nm_cached_state {
  79         unsigned long vco_rate;
  80         u8 bit_clk_div;
  81         u8 pix_clk_div;
  82         u8 pll_out_div;
  83         u8 pll_mux;
  84 };
  85
  86 struct dsi_pll_7nm {
  87         struct clk_hw clk_hw;
  88
  89         struct msm_dsi_phy *phy;
  90
  91         u64 vco_ref_clk_rate;
  92         u64 vco_current_rate;
  93
  94         /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */
  95         spinlock_t postdiv_lock;
  96
  97         struct dsi_pll_config pll_configuration;
  98         struct dsi_pll_regs reg_setup;
  99
 100         struct pll_7nm_cached_state cached_state;
 101
 102         struct dsi_pll_7nm *slave;
 103 };
 104
 105 #define to_pll_7nm(x)   container_of(x, struct dsi_pll_7nm, clk_hw)
 106
 107 /*
 108  * Global list of private DSI PLL struct pointers. We need this for Dual DSI
 109  * mode, where the master PLL's clk_ops needs access the slave's private data
 110  */
 111 static struct dsi_pll_7nm *pll_7nm_list[DSI_MAX];
 112
 113 static void dsi_pll_setup_config(struct dsi_pll_7nm *pll)
 114 {
 115         struct dsi_pll_config *config = &pll->pll_configuration;
 116
 117         config->ref_freq = pll->vco_ref_clk_rate;
 118         config->output_div = 1;
 119         config->dec_bits = 8;
 120         config->frac_bits = 18;
 121         config->lock_timer = 64;
 122         config->ssc_freq = 31500;
 123         config->ssc_offset = 4800;
 124         config->ssc_adj_per = 2;
 125         config->thresh_cycles = 32;
 126         config->refclk_cycles = 256;
 127
 128         config->div_override = false;
 129         config->ignore_frac = false;
 130         config->disable_prescaler = false;
 131
 132         /* TODO: ssc enable */
 133         config->enable_ssc = false;
 134         config->ssc_center = 0;
 135 }
 136
 137 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll)
 138 {
 139         struct dsi_pll_config *config = &pll->pll_configuration;
 140         struct dsi_pll_regs *regs = &pll->reg_setup;
 141         u64 fref = pll->vco_ref_clk_rate;
 142         u64 pll_freq;
 143         u64 divider;
 144         u64 dec, dec_multiple;
 145         u32 frac;
 146         u64 multiplier;
 147
 148         pll_freq = pll->vco_current_rate;
 149
 150         if (config->disable_prescaler)
 151                 divider = fref;
 152         else
 153                 divider = fref * 2;
 154
 155         multiplier = 1 << config->frac_bits;
 156         dec_multiple = div_u64(pll_freq * multiplier, divider);
 157         div_u64_rem(dec_multiple, multiplier, &frac);
 158
 159         dec = div_u64(dec_multiple, multiplier);
 160
 161         if (!(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1))
 162                 regs->pll_clock_inverters = 0x28;
 163         else if (pll_freq <= 1000000000ULL)
 164                 regs->pll_clock_inverters = 0xa0;
 165         else if (pll_freq <= 2500000000ULL)
 166                 regs->pll_clock_inverters = 0x20;
 167         else if (pll_freq <= 3020000000ULL)
 168                 regs->pll_clock_inverters = 0x00;
 169         else
 170                 regs->pll_clock_inverters = 0x40;
 171
 172         regs->pll_lockdet_rate = config->lock_timer;
 173         regs->decimal_div_start = dec;
 174         regs->frac_div_start_low = (frac & 0xff);
 175         regs->frac_div_start_mid = (frac & 0xff00) >> 8;
 176         regs->frac_div_start_high = (frac & 0x30000) >> 16;
 177 }
 178
 179 #define SSC_CENTER              BIT(0)
 180 #define SSC_EN                  BIT(1)
 181
 182 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll)
 183 {
 184         struct dsi_pll_config *config = &pll->pll_configuration;
 185         struct dsi_pll_regs *regs = &pll->reg_setup;
 186         u32 ssc_per;
 187         u32 ssc_mod;
 188         u64 ssc_step_size;
 189         u64 frac;
 190
 191         if (!config->enable_ssc) {
 192                 DBG("SSC not enabled\n");
 193                 return;
 194         }
 195
 196         ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
 197         ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
 198         ssc_per -= ssc_mod;
 199
 200         frac = regs->frac_div_start_low |
 201                         (regs->frac_div_start_mid << 8) |
 202                         (regs->frac_div_start_high << 16);
 203         ssc_step_size = regs->decimal_div_start;
 204         ssc_step_size *= (1 << config->frac_bits);
 205         ssc_step_size += frac;
 206         ssc_step_size *= config->ssc_offset;
 207         ssc_step_size *= (config->ssc_adj_per + 1);
 208         ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
 209         ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
 210
 211         regs->ssc_div_per_low = ssc_per & 0xFF;
 212         regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
 213         regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
 214         regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
 215         regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
 216         regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
 217
 218         regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
 219
 220         pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
 221                  regs->decimal_div_start, frac, config->frac_bits);
 222         pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
 223                  ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
 224 }
 225
 226 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll)
 227 {
 228         void __iomem *base = pll->phy->pll_base;
 229         struct dsi_pll_regs *regs = &pll->reg_setup;
 230
 231         if (pll->pll_configuration.enable_ssc) {
 232                 pr_debug("SSC is enabled\n");
 233
 234                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
 235                           regs->ssc_stepsize_low);
 236                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
 237                           regs->ssc_stepsize_high);
 238                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1,
 239                           regs->ssc_div_per_low);
 240                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
 241                           regs->ssc_div_per_high);
 242                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1,
 243                           regs->ssc_adjper_low);
 244                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1,
 245                           regs->ssc_adjper_high);
 246                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_SSC_CONTROL,
 247                           SSC_EN | regs->ssc_control);
 248         }
 249 }
 250
 251 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
 252 {
 253         void __iomem *base = pll->phy->pll_base;
 254         u8 analog_controls_five_1 = 0x01, vco_config_1 = 0x00;
 255
 256         if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
 257                 if (pll->vco_current_rate >= 3100000000ULL)
 258                         analog_controls_five_1 = 0x03;
 259
 260                 if (pll->vco_current_rate < 1520000000ULL)
 261                         vco_config_1 = 0x08;
 262                 else if (pll->vco_current_rate < 2990000000ULL)
 263                         vco_config_1 = 0x01;
 264         }
 265
 266         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
 267                   analog_controls_five_1);
 268         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
 269         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE, 0x01);
 270         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
 271         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
 272         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DSM_DIVIDER, 0x00);
 273         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
 274         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
 275         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE, 0xba);
 276         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
 277         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_OUTDIV, 0x00);
 278         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE, 0x00);
 279         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
 280         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x0a);
 281         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1, 0xc0);
 282         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x84);
 283         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0x82);
 284         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1, 0x4c);
 285         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
 286         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x29);
 287         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PFILT, 0x2f);
 288         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT, 0x2a);
 289         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_IFILT,
 290                   pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1 ? 0x3f : 0x22);
 291
 292         if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
 293                 dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
 294                 if (pll->slave)
 295                         dsi_phy_write(pll->slave->phy->pll_base + REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE, 0x22);
 296         }
 297 }
 298
 299 static void dsi_pll_commit(struct dsi_pll_7nm *pll)
 300 {
 301         void __iomem *base = pll->phy->pll_base;
 302         struct dsi_pll_regs *reg = &pll->reg_setup;
 303
 304         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
 305         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1, reg->decimal_div_start);
 306         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1, reg->frac_div_start_low);
 307         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1, reg->frac_div_start_mid);
 308         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high);
 309         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1, reg->pll_lockdet_rate);
 310         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
 311         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CMODE_1, 0x10); /* TODO: 0x00 for CPHY */
 312         dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS, reg->pll_clock_inverters);
 313 }
 314
 315 static int dsi_pll_7nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 316                                      unsigned long parent_rate)
 317 {
 318         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
 319
 320         DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_7nm->phy->id, rate,
 321             parent_rate);
 322
 323         pll_7nm->vco_current_rate = rate;
 324         pll_7nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
 325
 326         dsi_pll_setup_config(pll_7nm);
 327
 328         dsi_pll_calc_dec_frac(pll_7nm);
 329
 330         dsi_pll_calc_ssc(pll_7nm);
 331
 332         dsi_pll_commit(pll_7nm);
 333
 334         dsi_pll_config_hzindep_reg(pll_7nm);
 335
 336         dsi_pll_ssc_commit(pll_7nm);
 337
 338         /* flush, ensure all register writes are done*/
 339         wmb();
 340
 341         return 0;
 342 }
 343
 344 static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll)
 345 {
 346         int rc;
 347         u32 status = 0;
 348         u32 const delay_us = 100;
 349         u32 const timeout_us = 5000;
 350
 351         rc = readl_poll_timeout_atomic(pll->phy->pll_base +
 352                                        REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE,
 353                                        status,
 354                                        ((status & BIT(0)) > 0),
 355                                        delay_us,
 356                                        timeout_us);
 357         if (rc)
 358                 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
 359                        pll->phy->id, status);
 360
 361         return rc;
 362 }
 363
 364 static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
 365 {
 366         u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
 367
 368         dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0);
 369         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data & ~BIT(5));
 370         ndelay(250);
 371 }
 372
 373 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
 374 {
 375         u32 data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0);
 376
 377         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0, data | BIT(5));
 378         dsi_phy_write(pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
 379         ndelay(250);
 380 }
 381
 382 static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
 383 {
 384         u32 data;
 385
 386         data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
 387         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5));
 388 }
 389
 390 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
 391 {
 392         u32 data;
 393
 394         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x04);
 395
 396         data = dsi_phy_read(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
 397         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1,
 398                   data | BIT(5) | BIT(4));
 399 }
 400
 401 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
 402 {
 403         /*
 404          * Reset the PHY digital domain. This would be needed when
 405          * coming out of a CX or analog rail power collapse while
 406          * ensuring that the pads maintain LP00 or LP11 state
 407          */
 408         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, BIT(0));
 409         wmb(); /* Ensure that the reset is deasserted */
 410         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4, 0x0);
 411         wmb(); /* Ensure that the reset is deasserted */
 412 }
 413
 414 static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
 415 {
 416         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
 417         int rc;
 418
 419         dsi_pll_enable_pll_bias(pll_7nm);
 420         if (pll_7nm->slave)
 421                 dsi_pll_enable_pll_bias(pll_7nm->slave);
 422
 423         /* Start PLL */
 424         dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x01);
 425
 426         /*
 427          * ensure all PLL configurations are written prior to checking
 428          * for PLL lock.
 429          */
 430         wmb();
 431
 432         /* Check for PLL lock */
 433         rc = dsi_pll_7nm_lock_status(pll_7nm);
 434         if (rc) {
 435                 pr_err("PLL(%d) lock failed\n", pll_7nm->phy->id);
 436                 goto error;
 437         }
 438
 439         pll_7nm->phy->pll_on = true;
 440
 441         /*
 442          * assert power on reset for PHY digital in case the PLL is
 443          * enabled after CX of analog domain power collapse. This needs
 444          * to be done before enabling the global clk.
 445          */
 446         dsi_pll_phy_dig_reset(pll_7nm);
 447         if (pll_7nm->slave)
 448                 dsi_pll_phy_dig_reset(pll_7nm->slave);
 449
 450         dsi_pll_enable_global_clk(pll_7nm);
 451         if (pll_7nm->slave)
 452                 dsi_pll_enable_global_clk(pll_7nm->slave);
 453
 454 error:
 455         return rc;
 456 }
 457
 458 static void dsi_pll_disable_sub(struct dsi_pll_7nm *pll)
 459 {
 460         dsi_phy_write(pll->phy->base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0);
 461         dsi_pll_disable_pll_bias(pll);
 462 }
 463
 464 static void dsi_pll_7nm_vco_unprepare(struct clk_hw *hw)
 465 {
 466         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
 467
 468         /*
 469          * To avoid any stray glitches while abruptly powering down the PLL
 470          * make sure to gate the clock using the clock enable bit before
 471          * powering down the PLL
 472          */
 473         dsi_pll_disable_global_clk(pll_7nm);
 474         dsi_phy_write(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0);
 475         dsi_pll_disable_sub(pll_7nm);
 476         if (pll_7nm->slave) {
 477                 dsi_pll_disable_global_clk(pll_7nm->slave);
 478                 dsi_pll_disable_sub(pll_7nm->slave);
 479         }
 480         /* flush, ensure all register writes are done */
 481         wmb();
 482         pll_7nm->phy->pll_on = false;
 483 }
 484
 485 static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
 486                                                   unsigned long parent_rate)
 487 {
 488         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
 489         struct dsi_pll_config *config = &pll_7nm->pll_configuration;
 490         void __iomem *base = pll_7nm->phy->pll_base;
 491         u64 ref_clk = pll_7nm->vco_ref_clk_rate;
 492         u64 vco_rate = 0x0;
 493         u64 multiplier;
 494         u32 frac;
 495         u32 dec;
 496         u64 pll_freq, tmp64;
 497
 498         dec = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1);
 499         dec &= 0xff;
 500
 501         frac = dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1);
 502         frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1) &
 503                   0xff) << 8);
 504         frac |= ((dsi_phy_read(base + REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
 505                   0x3) << 16);
 506
 507         /*
 508          * TODO:
 509          *      1. Assumes prescaler is disabled
 510          */
 511         multiplier = 1 << config->frac_bits;
 512         pll_freq = dec * (ref_clk * 2);
 513         tmp64 = (ref_clk * 2 * frac);
 514         pll_freq += div_u64(tmp64, multiplier);
 515
 516         vco_rate = pll_freq;
 517
 518         DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
 519             pll_7nm->phy->id, (unsigned long)vco_rate, dec, frac);
 520
 521         return (unsigned long)vco_rate;
 522 }
 523
 524 static long dsi_pll_7nm_clk_round_rate(struct clk_hw *hw,
 525                 unsigned long rate, unsigned long *parent_rate)
 526 {
 527         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
 528
 529         if      (rate < pll_7nm->phy->cfg->min_pll_rate)
 530                 return  pll_7nm->phy->cfg->min_pll_rate;
 531         else if (rate > pll_7nm->phy->cfg->max_pll_rate)
 532                 return  pll_7nm->phy->cfg->max_pll_rate;
 533         else
 534                 return rate;
 535 }
 536
 537 static const struct clk_ops clk_ops_dsi_pll_7nm_vco = {
 538         .round_rate = dsi_pll_7nm_clk_round_rate,
 539         .set_rate = dsi_pll_7nm_vco_set_rate,
 540         .recalc_rate = dsi_pll_7nm_vco_recalc_rate,
 541         .prepare = dsi_pll_7nm_vco_prepare,
 542         .unprepare = dsi_pll_7nm_vco_unprepare,
 543 };
 544
 545 /*
 546  * PLL Callbacks
 547  */
 548
 549 static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
 550 {
 551         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
 552         struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
 553         void __iomem *phy_base = pll_7nm->phy->base;
 554         u32 cmn_clk_cfg0, cmn_clk_cfg1;
 555
 556         cached->pll_out_div = dsi_phy_read(pll_7nm->phy->pll_base +
 557                                        REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
 558         cached->pll_out_div &= 0x3;
 559
 560         cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
 561         cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
 562         cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
 563
 564         cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
 565         cached->pll_mux = cmn_clk_cfg1 & 0x3;
 566
 567         DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
 568             pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
 569             cached->pix_clk_div, cached->pll_mux);
 570 }
 571
 572 static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
 573 {
 574         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
 575         struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;
 576         void __iomem *phy_base = pll_7nm->phy->base;
 577         u32 val;
 578         int ret;
 579
 580         val = dsi_phy_read(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
 581         val &= ~0x3;
 582         val |= cached->pll_out_div;
 583         dsi_phy_write(pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE, val);
 584
 585         dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0,
 586                   cached->bit_clk_div | (cached->pix_clk_div << 4));
 587
 588         val = dsi_phy_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
 589         val &= ~0x3;
 590         val |= cached->pll_mux;
 591         dsi_phy_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);
 592
 593         ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
 594                         pll_7nm->vco_current_rate,
 595                         pll_7nm->vco_ref_clk_rate);
 596         if (ret) {
 597                 DRM_DEV_ERROR(&pll_7nm->phy->pdev->dev,
 598                         "restore vco rate failed. ret=%d\n", ret);
 599                 return ret;
 600         }
 601
 602         DBG("DSI PLL%d", pll_7nm->phy->id);
 603
 604         return 0;
 605 }
 606
 607 static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
 608 {
 609         struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
 610         void __iomem *base = phy->base;
 611         u32 data = 0x0; /* internal PLL */
 612
 613         DBG("DSI PLL%d", pll_7nm->phy->id);
 614
 615         switch (phy->usecase) {
 616         case MSM_DSI_PHY_STANDALONE:
 617                 break;
 618         case MSM_DSI_PHY_MASTER:
 619                 pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
 620                 break;
 621         case MSM_DSI_PHY_SLAVE:
 622                 data = 0x1; /* external PLL */
 623                 break;
 624         default:
 625                 return -EINVAL;
 626         }
 627
 628         /* set PLL src */
 629         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2));
 630
 631         return 0;
 632 }
 633
 634 /*
 635  * The post dividers and mux clocks are created using the standard divider and
 636  * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
 637  * state to follow the master PLL's divider/mux state. Therefore, we don't
 638  * require special clock ops that also configure the slave PLL registers
 639  */
 640 static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks)
 641 {
 642         char clk_name[32], parent[32], vco_name[32];
 643         char parent2[32], parent3[32], parent4[32];
 644         struct clk_init_data vco_init = {
 645                 .parent_names = (const char *[]){ "bi_tcxo" },
 646                 .num_parents = 1,
 647                 .name = vco_name,
 648                 .flags = CLK_IGNORE_UNUSED,
 649                 .ops = &clk_ops_dsi_pll_7nm_vco,
 650         };
 651         struct device *dev = &pll_7nm->phy->pdev->dev;
 652         struct clk_hw *hw;
 653         int ret;
 654
 655         DBG("DSI%d", pll_7nm->phy->id);
 656
 657         snprintf(vco_name, 32, "dsi%dvco_clk", pll_7nm->phy->id);
 658         pll_7nm->clk_hw.init = &vco_init;
 659
 660         ret = devm_clk_hw_register(dev, &pll_7nm->clk_hw);
 661         if (ret)
 662                 return ret;
 663
 664         snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
 665         snprintf(parent, 32, "dsi%dvco_clk", pll_7nm->phy->id);
 666
 667         hw = devm_clk_hw_register_divider(dev, clk_name,
 668                                      parent, CLK_SET_RATE_PARENT,
 669                                      pll_7nm->phy->pll_base +
 670                                      REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE,
 671                                      0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
 672         if (IS_ERR(hw)) {
 673                 ret = PTR_ERR(hw);
 674                 goto fail;
 675         }
 676
 677         snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
 678         snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
 679
 680         /* BIT CLK: DIV_CTRL_3_0 */
 681         hw = devm_clk_hw_register_divider(dev, clk_name, parent,
 682                                      CLK_SET_RATE_PARENT,
 683                                      pll_7nm->phy->base +
 684                                      REG_DSI_7nm_PHY_CMN_CLK_CFG0,
 685                                      0, 4, CLK_DIVIDER_ONE_BASED,
 686                                      &pll_7nm->postdiv_lock);
 687         if (IS_ERR(hw)) {
 688                 ret = PTR_ERR(hw);
 689                 goto fail;
 690         }
 691
 692         snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id);
 693         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
 694
 695         /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
 696         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 697                                           CLK_SET_RATE_PARENT, 1, 8);
 698         if (IS_ERR(hw)) {
 699                 ret = PTR_ERR(hw);
 700                 goto fail;
 701         }
 702
 703         provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 704
 705         snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
 706         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
 707
 708         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 709                                           0, 1, 2);
 710         if (IS_ERR(hw)) {
 711                 ret = PTR_ERR(hw);
 712                 goto fail;
 713         }
 714
 715         snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
 716         snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
 717
 718         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 719                                           0, 1, 4);
 720         if (IS_ERR(hw)) {
 721                 ret = PTR_ERR(hw);
 722                 goto fail;
 723         }
 724
 725         snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
 726         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id);
 727         snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id);
 728         snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id);
 729         snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id);
 730
 731         hw = devm_clk_hw_register_mux(dev, clk_name,
 732                                  ((const char *[]){
 733                                  parent, parent2, parent3, parent4
 734                                  }), 4, 0, pll_7nm->phy->base +
 735                                  REG_DSI_7nm_PHY_CMN_CLK_CFG1,
 736                                  0, 2, 0, NULL);
 737         if (IS_ERR(hw)) {
 738                 ret = PTR_ERR(hw);
 739                 goto fail;
 740         }
 741
 742         snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_7nm->phy->id);
 743         snprintf(parent, 32, "dsi%d_pclk_mux", pll_7nm->phy->id);
 744
 745         /* PIX CLK DIV : DIV_CTRL_7_4*/
 746         hw = devm_clk_hw_register_divider(dev, clk_name, parent,
 747                                      0, pll_7nm->phy->base +
 748                                         REG_DSI_7nm_PHY_CMN_CLK_CFG0,
 749                                      4, 4, CLK_DIVIDER_ONE_BASED,
 750                                      &pll_7nm->postdiv_lock);
 751         if (IS_ERR(hw)) {
 752                 ret = PTR_ERR(hw);
 753                 goto fail;
 754         }
 755
 756         provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
 757
 758         return 0;
 759
 760 fail:
 761
 762         return ret;
 763 }
 764
 765 static int dsi_pll_7nm_init(struct msm_dsi_phy *phy)
 766 {
 767         struct platform_device *pdev = phy->pdev;
 768         struct dsi_pll_7nm *pll_7nm;
 769         int ret;
 770
 771         pll_7nm = devm_kzalloc(&pdev->dev, sizeof(*pll_7nm), GFP_KERNEL);
 772         if (!pll_7nm)
 773                 return -ENOMEM;
 774
 775         DBG("DSI PLL%d", phy->id);
 776
 777         pll_7nm_list[phy->id] = pll_7nm;
 778
 779         spin_lock_init(&pll_7nm->postdiv_lock);
 780
 781         pll_7nm->phy = phy;
 782
 783         ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws);
 784         if (ret) {
 785                 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
 786                 return ret;
 787         }
 788
 789         phy->vco_hw = &pll_7nm->clk_hw;
 790
 791         /* TODO: Remove this when we have proper display handover support */
 792         msm_dsi_phy_pll_save_state(phy);
 793
 794         return 0;
 795 }
 796
 797 static int dsi_phy_hw_v4_0_is_pll_on(struct msm_dsi_phy *phy)
 798 {
 799         void __iomem *base = phy->base;
 800         u32 data = 0;
 801
 802         data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL);
 803         mb(); /* make sure read happened */
 804
 805         return (data & BIT(0));
 806 }
 807
 808 static void dsi_phy_hw_v4_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
 809 {
 810         void __iomem *lane_base = phy->lane_base;
 811         int phy_lane_0 = 0;     /* TODO: Support all lane swap configs */
 812
 813         /*
 814          * LPRX and CDRX need to enabled only for physical data lane
 815          * corresponding to the logical data lane 0
 816          */
 817         if (enable)
 818                 dsi_phy_write(lane_base +
 819                               REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
 820         else
 821                 dsi_phy_write(lane_base +
 822                               REG_DSI_7nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
 823 }
 824
 825 static void dsi_phy_hw_v4_0_lane_settings(struct msm_dsi_phy *phy)
 826 {
 827         int i;
 828         const u8 tx_dctrl_0[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
 829         const u8 tx_dctrl_1[] = { 0x40, 0x40, 0x40, 0x46, 0x41 };
 830         const u8 *tx_dctrl = tx_dctrl_0;
 831         void __iomem *lane_base = phy->lane_base;
 832
 833         if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1)
 834                 tx_dctrl = tx_dctrl_1;
 835
 836         /* Strength ctrl settings */
 837         for (i = 0; i < 5; i++) {
 838                 /*
 839                  * Disable LPRX and CDRX for all lanes. And later on, it will
 840                  * be only enabled for the physical data lane corresponding
 841                  * to the logical data lane 0
 842                  */
 843                 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_LPRX_CTRL(i), 0);
 844                 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_PIN_SWAP(i), 0x0);
 845         }
 846
 847         dsi_phy_hw_v4_0_config_lpcdrx(phy, true);
 848
 849         /* other settings */
 850         for (i = 0; i < 5; i++) {
 851                 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG0(i), 0x0);
 852                 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG1(i), 0x0);
 853                 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_CFG2(i), i == 4 ? 0x8a : 0xa);
 854                 dsi_phy_write(lane_base + REG_DSI_7nm_PHY_LN_TX_DCTRL(i), tx_dctrl[i]);
 855         }
 856 }
 857
 858 static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 859                               struct msm_dsi_phy_clk_request *clk_req)
 860 {
 861         int ret;
 862         u32 status;
 863         u32 const delay_us = 5;
 864         u32 const timeout_us = 1000;
 865         struct msm_dsi_dphy_timing *timing = &phy->timing;
 866         void __iomem *base = phy->base;
 867         bool less_than_1500_mhz;
 868         u32 vreg_ctrl_0, glbl_str_swi_cal_sel_ctrl, glbl_hstx_str_ctrl_0;
 869         u32 glbl_rescode_top_ctrl, glbl_rescode_bot_ctrl;
 870         u32 data;
 871
 872         DBG("");
 873
 874         if (msm_dsi_dphy_timing_calc_v4(timing, clk_req)) {
 875                 DRM_DEV_ERROR(&phy->pdev->dev,
 876                         "%s: D-PHY timing calculation failed\n", __func__);
 877                 return -EINVAL;
 878         }
 879
 880         if (dsi_phy_hw_v4_0_is_pll_on(phy))
 881                 pr_warn("PLL turned on before configuring PHY\n");
 882
 883         /* wait for REFGEN READY */
 884         ret = readl_poll_timeout_atomic(base + REG_DSI_7nm_PHY_CMN_PHY_STATUS,
 885                                         status, (status & BIT(0)),
 886                                         delay_us, timeout_us);
 887         if (ret) {
 888                 pr_err("Ref gen not ready. Aborting\n");
 889                 return -EINVAL;
 890         }
 891
 892         /* TODO: CPHY enable path (this is for DPHY only) */
 893
 894         /* Alter PHY configurations if data rate less than 1.5GHZ*/
 895         less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000);
 896
 897         if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) {
 898                 vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52;
 899                 glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x00;
 900                 glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 :  0x3c;
 901                 glbl_str_swi_cal_sel_ctrl = 0x00;
 902                 glbl_hstx_str_ctrl_0 = 0x88;
 903         } else {
 904                 vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
 905                 glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;
 906                 glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88;
 907                 glbl_rescode_top_ctrl = 0x03;
 908                 glbl_rescode_bot_ctrl = 0x3c;
 909         }
 910
 911         /* de-assert digital and pll power down */
 912         data = BIT(6) | BIT(5);
 913         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
 914
 915         /* Assert PLL core reset */
 916         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_PLL_CNTRL, 0x00);
 917
 918         /* turn off resync FIFO */
 919         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
 920
 921         /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
 922         data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
 923         data = data & (0xf0);
 924         if (data == 0x20)
 925                 dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
 926
 927         /* Configure PHY lane swap (TODO: we need to calculate this) */
 928         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG0, 0x21);
 929         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CFG1, 0x84);
 930
 931         /* Enable LDO */
 932         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
 933         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_VREG_CTRL_1, 0x5c);
 934         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_3, 0x00);
 935         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
 936                       glbl_str_swi_cal_sel_ctrl);
 937         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0,
 938                       glbl_hstx_str_ctrl_0);
 939         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0, 0x00);
 940         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
 941                       glbl_rescode_top_ctrl);
 942         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
 943                       glbl_rescode_bot_ctrl);
 944         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
 945
 946         /* Remove power down from all blocks */
 947         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x7f);
 948
 949         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0x1f);
 950
 951         /* Select full-rate mode */
 952         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_2, 0x40);
 953
 954         ret = dsi_7nm_set_usecase(phy);
 955         if (ret) {
 956                 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
 957                         __func__, ret);
 958                 return ret;
 959         }
 960
 961         /* DSI PHY timings */
 962         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0, 0x00);
 963         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1, timing->clk_zero);
 964         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2, timing->clk_prepare);
 965         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3, timing->clk_trail);
 966         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4, timing->hs_exit);
 967         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5, timing->hs_zero);
 968         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6, timing->hs_prepare);
 969         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7, timing->hs_trail);
 970         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8, timing->hs_rqst);
 971         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9, 0x02);
 972         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10, 0x04);
 973         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11, 0x00);
 974         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12,
 975                       timing->shared_timings.clk_pre);
 976         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13,
 977                       timing->shared_timings.clk_post);
 978
 979         /* DSI lane settings */
 980         dsi_phy_hw_v4_0_lane_settings(phy);
 981
 982         DBG("DSI%d PHY enabled", phy->id);
 983
 984         return 0;
 985 }
 986
 987 static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
 988 {
 989         void __iomem *base = phy->base;
 990         u32 data;
 991
 992         DBG("");
 993
 994         if (dsi_phy_hw_v4_0_is_pll_on(phy))
 995                 pr_warn("Turning OFF PHY while PLL is on\n");
 996
 997         dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
 998         data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_CTRL_0);
 999
1000         /* disable all lanes */
1001         data &= ~0x1F;
1002         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);
1003         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0, 0);
1004
1005         /* Turn off all PHY blocks */
1006         dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, 0x00);
1007         /* make sure phy is turned off */
1008         wmb();
1009
1010         DBG("DSI%d PHY disabled", phy->id);
1011 }
1012
1013 const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
1014         .src_pll_truthtable = { {false, false}, {true, false} },
1015         .has_phy_lane = true,
1016         .reg_cfg = {
1017                 .num = 1,
1018                 .regs = {
1019                         {"vdds", 36000, 32},
1020                 },
1021         },
1022         .ops = {
1023                 .enable = dsi_7nm_phy_enable,
1024                 .disable = dsi_7nm_phy_disable,
1025                 .pll_init = dsi_pll_7nm_init,
1026                 .save_pll_state = dsi_7nm_pll_save_state,
1027                 .restore_pll_state = dsi_7nm_pll_restore_state,
1028         },
1029         .min_pll_rate = 600000000UL,
1030         .max_pll_rate = (5000000000ULL < ULONG_MAX) ? 5000000000ULL : ULONG_MAX,
1031         .io_start = { 0xae94400, 0xae96400 },
1032         .num_dsi_phy = 2,
1033         .quirks = DSI_PHY_7NM_QUIRK_V4_1,
1034 };
1035
1036 const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
1037         .src_pll_truthtable = { {false, false}, {true, false} },
1038         .has_phy_lane = true,
1039         .reg_cfg = {
1040                 .num = 1,
1041                 .regs = {
1042                         {"vdds", 36000, 32},
1043                 },
1044         },
1045         .ops = {
1046                 .enable = dsi_7nm_phy_enable,
1047                 .disable = dsi_7nm_phy_disable,
1048                 .pll_init = dsi_pll_7nm_init,
1049                 .save_pll_state = dsi_7nm_pll_save_state,
1050                 .restore_pll_state = dsi_7nm_pll_restore_state,
1051         },
1052         .min_pll_rate = 1000000000UL,
1053         .max_pll_rate = 3500000000UL,
1054         .io_start = { 0xae94400, 0xae96400 },
1055         .num_dsi_phy = 2,
1056 };