drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9
  10 #include "dsi_phy.h"
  11 #include "dsi.xml.h"
  12 #include "dsi_phy_14nm.xml.h"
  13
  14 #define PHY_14NM_CKLN_IDX       4
  15
  16 /*
  17  * DSI PLL 14nm - clock diagram (eg: DSI0):
  18  *
  19  *         dsi0n1_postdiv_clk
  20  *                         |
  21  *                         |
  22  *                 +----+  |  +----+
  23  *  dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
  24  *                 +----+  |  +----+
  25  *                         |           dsi0n1_postdivby2_clk
  26  *                         |   +----+  |
  27  *                         o---| /2 |--o--|\
  28  *                         |   +----+     | \   +----+
  29  *                         |              |  |--| n2 |-- dsi0pll
  30  *                         o--------------| /   +----+
  31  *                                        |/
  32  */
  33
  34 #define POLL_MAX_READS                  15
  35 #define POLL_TIMEOUT_US                 1000
  36
  37 #define VCO_REF_CLK_RATE                19200000
  38 #define VCO_MIN_RATE                    1300000000UL
  39 #define VCO_MAX_RATE                    2600000000UL
  40
  41 struct dsi_pll_config {
  42         u64 vco_current_rate;
  43
  44         u32 ssc_en;     /* SSC enable/disable */
  45
  46         /* fixed params */
  47         u32 plllock_cnt;
  48         u32 ssc_center;
  49         u32 ssc_adj_period;
  50         u32 ssc_spread;
  51         u32 ssc_freq;
  52
  53         /* calculated */
  54         u32 dec_start;
  55         u32 div_frac_start;
  56         u32 ssc_period;
  57         u32 ssc_step_size;
  58         u32 plllock_cmp;
  59         u32 pll_vco_div_ref;
  60         u32 pll_vco_count;
  61         u32 pll_kvco_div_ref;
  62         u32 pll_kvco_count;
  63 };
  64
  65 struct pll_14nm_cached_state {
  66         unsigned long vco_rate;
  67         u8 n2postdiv;
  68         u8 n1postdiv;
  69 };
  70
  71 struct dsi_pll_14nm {
  72         struct clk_hw clk_hw;
  73
  74         struct msm_dsi_phy *phy;
  75
  76         /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
  77         spinlock_t postdiv_lock;
  78
  79         struct pll_14nm_cached_state cached_state;
  80
  81         struct dsi_pll_14nm *slave;
  82 };
  83
  84 #define to_pll_14nm(x)  container_of(x, struct dsi_pll_14nm, clk_hw)
  85
  86 /*
  87  * Private struct for N1/N2 post-divider clocks. These clocks are similar to
  88  * the generic clk_divider class of clocks. The only difference is that it
  89  * also sets the slave DSI PLL's post-dividers if in bonded DSI mode
  90  */
  91 struct dsi_pll_14nm_postdiv {
  92         struct clk_hw hw;
  93
  94         /* divider params */
  95         u8 shift;
  96         u8 width;
  97         u8 flags; /* same flags as used by clk_divider struct */
  98
  99         struct dsi_pll_14nm *pll;
 100 };
 101
 102 #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw)
 103
 104 /*
 105  * Global list of private DSI PLL struct pointers. We need this for bonded DSI
 106  * mode, where the master PLL's clk_ops needs access the slave's private data
 107  */
 108 static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];
 109
 110 static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
 111                                     u32 nb_tries, u32 timeout_us)
 112 {
 113         bool pll_locked = false, pll_ready = false;
 114         void __iomem *base = pll_14nm->phy->pll_base;
 115         u32 tries, val;
 116
 117         tries = nb_tries;
 118         while (tries--) {
 119                 val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
 120                 pll_locked = !!(val & BIT(5));
 121
 122                 if (pll_locked)
 123                         break;
 124
 125                 udelay(timeout_us);
 126         }
 127
 128         if (!pll_locked)
 129                 goto out;
 130
 131         tries = nb_tries;
 132         while (tries--) {
 133                 val = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
 134                 pll_ready = !!(val & BIT(0));
 135
 136                 if (pll_ready)
 137                         break;
 138
 139                 udelay(timeout_us);
 140         }
 141
 142 out:
 143         DBG("DSI PLL is %slocked, %sready", pll_locked ? "" : "*not* ", pll_ready ? "" : "*not* ");
 144
 145         return pll_locked && pll_ready;
 146 }
 147
 148 static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf)
 149 {
 150         /* fixed input */
 151         pconf->plllock_cnt = 1;
 152
 153         /*
 154          * SSC is enabled by default. We might need DT props for configuring
 155          * some SSC params like PPM and center/down spread etc.
 156          */
 157         pconf->ssc_en = 1;
 158         pconf->ssc_center = 0;          /* down spread by default */
 159         pconf->ssc_spread = 5;          /* PPM / 1000 */
 160         pconf->ssc_freq = 31500;        /* default recommended */
 161         pconf->ssc_adj_period = 37;
 162 }
 163
 164 #define CEIL(x, y)              (((x) + ((y) - 1)) / (y))
 165
 166 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
 167 {
 168         u32 period, ssc_period;
 169         u32 ref, rem;
 170         u64 step_size;
 171
 172         DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE);
 173
 174         ssc_period = pconf->ssc_freq / 500;
 175         period = (u32)VCO_REF_CLK_RATE / 1000;
 176         ssc_period  = CEIL(period, ssc_period);
 177         ssc_period -= 1;
 178         pconf->ssc_period = ssc_period;
 179
 180         DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq,
 181             pconf->ssc_spread, pconf->ssc_period);
 182
 183         step_size = (u32)pconf->vco_current_rate;
 184         ref = VCO_REF_CLK_RATE;
 185         ref /= 1000;
 186         step_size = div_u64(step_size, ref);
 187         step_size <<= 20;
 188         step_size = div_u64(step_size, 1000);
 189         step_size *= pconf->ssc_spread;
 190         step_size = div_u64(step_size, 1000);
 191         step_size *= (pconf->ssc_adj_period + 1);
 192
 193         rem = 0;
 194         step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
 195         if (rem)
 196                 step_size++;
 197
 198         DBG("step_size=%lld", step_size);
 199
 200         step_size &= 0x0ffff;   /* take lower 16 bits */
 201
 202         pconf->ssc_step_size = step_size;
 203 }
 204
 205 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
 206 {
 207         u64 multiplier = BIT(20);
 208         u64 dec_start_multiple, dec_start, pll_comp_val;
 209         u32 duration, div_frac_start;
 210         u64 vco_clk_rate = pconf->vco_current_rate;
 211         u64 fref = VCO_REF_CLK_RATE;
 212
 213         DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
 214
 215         dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
 216         dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
 217
 218         pconf->dec_start = (u32)dec_start;
 219         pconf->div_frac_start = div_frac_start;
 220
 221         if (pconf->plllock_cnt == 0)
 222                 duration = 1024;
 223         else if (pconf->plllock_cnt == 1)
 224                 duration = 256;
 225         else if (pconf->plllock_cnt == 2)
 226                 duration = 128;
 227         else
 228                 duration = 32;
 229
 230         pll_comp_val = duration * dec_start_multiple;
 231         pll_comp_val = div_u64(pll_comp_val, multiplier);
 232         do_div(pll_comp_val, 10);
 233
 234         pconf->plllock_cmp = (u32)pll_comp_val;
 235 }
 236
 237 static u32 pll_14nm_kvco_slop(u32 vrate)
 238 {
 239         u32 slop = 0;
 240
 241         if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL)
 242                 slop =  600;
 243         else if (vrate > 1800000000UL && vrate < 2300000000UL)
 244                 slop = 400;
 245         else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE)
 246                 slop = 280;
 247
 248         return slop;
 249 }
 250
 251 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
 252 {
 253         u64 vco_clk_rate = pconf->vco_current_rate;
 254         u64 fref = VCO_REF_CLK_RATE;
 255         u32 vco_measure_time = 5;
 256         u32 kvco_measure_time = 5;
 257         u64 data;
 258         u32 cnt;
 259
 260         data = fref * vco_measure_time;
 261         do_div(data, 1000000);
 262         data &= 0x03ff; /* 10 bits */
 263         data -= 2;
 264         pconf->pll_vco_div_ref = data;
 265
 266         data = div_u64(vco_clk_rate, 1000000);  /* unit is Mhz */
 267         data *= vco_measure_time;
 268         do_div(data, 10);
 269         pconf->pll_vco_count = data;
 270
 271         data = fref * kvco_measure_time;
 272         do_div(data, 1000000);
 273         data &= 0x03ff; /* 10 bits */
 274         data -= 1;
 275         pconf->pll_kvco_div_ref = data;
 276
 277         cnt = pll_14nm_kvco_slop(vco_clk_rate);
 278         cnt *= 2;
 279         cnt /= 100;
 280         cnt *= kvco_measure_time;
 281         pconf->pll_kvco_count = cnt;
 282 }
 283
 284 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf)
 285 {
 286         void __iomem *base = pll->phy->pll_base;
 287         u8 data;
 288
 289         data = pconf->ssc_adj_period;
 290         data &= 0x0ff;
 291         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
 292         data = (pconf->ssc_adj_period >> 8);
 293         data &= 0x03;
 294         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
 295
 296         data = pconf->ssc_period;
 297         data &= 0x0ff;
 298         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
 299         data = (pconf->ssc_period >> 8);
 300         data &= 0x0ff;
 301         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
 302
 303         data = pconf->ssc_step_size;
 304         data &= 0x0ff;
 305         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
 306         data = (pconf->ssc_step_size >> 8);
 307         data &= 0x0ff;
 308         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
 309
 310         data = (pconf->ssc_center & 0x01);
 311         data <<= 1;
 312         data |= 0x01; /* enable */
 313         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
 314
 315         wmb();  /* make sure register committed */
 316 }
 317
 318 static void pll_db_commit_common(struct dsi_pll_14nm *pll,
 319                                  struct dsi_pll_config *pconf)
 320 {
 321         void __iomem *base = pll->phy->pll_base;
 322         u8 data;
 323
 324         /* confgiure the non frequency dependent pll registers */
 325         data = 0;
 326         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
 327
 328         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, 1);
 329
 330         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, 48);
 331         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, 4 << 3); /* bandgap_timer */
 332         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, 5); /* pll_wakeup_timer */
 333
 334         data = pconf->pll_vco_div_ref & 0xff;
 335         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
 336         data = (pconf->pll_vco_div_ref >> 8) & 0x3;
 337         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
 338
 339         data = pconf->pll_kvco_div_ref & 0xff;
 340         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
 341         data = (pconf->pll_kvco_div_ref >> 8) & 0x3;
 342         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
 343
 344         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, 16);
 345
 346         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, 4);
 347
 348         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, 4);
 349
 350         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, 1 << 3 | 1);
 351
 352         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, 0 << 3 | 0);
 353
 354         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, 0 << 3 | 0);
 355
 356         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, 4 << 3 | 4);
 357
 358         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, 1 << 4 | 11);
 359
 360         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, 7);
 361
 362         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, 1 << 4 | 2);
 363 }
 364
 365 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
 366 {
 367         void __iomem *cmn_base = pll_14nm->phy->base;
 368
 369         /* de assert pll start and apply pll sw reset */
 370
 371         /* stop pll */
 372         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
 373
 374         /* pll sw reset */
 375         dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
 376         wmb();  /* make sure register committed */
 377
 378         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
 379         wmb();  /* make sure register committed */
 380 }
 381
 382 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
 383                                struct dsi_pll_config *pconf)
 384 {
 385         void __iomem *base = pll->phy->pll_base;
 386         void __iomem *cmn_base = pll->phy->base;
 387         u8 data;
 388
 389         DBG("DSI%d PLL", pll->phy->id);
 390
 391         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, 0x3c);
 392
 393         pll_db_commit_common(pll, pconf);
 394
 395         pll_14nm_software_reset(pll);
 396
 397         /* Use the /2 path in Mux */
 398         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, 1);
 399
 400         data = 0xff; /* data, clk, pll normal operation */
 401         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
 402
 403         /* configure the frequency dependent pll registers */
 404         data = pconf->dec_start;
 405         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
 406
 407         data = pconf->div_frac_start & 0xff;
 408         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
 409         data = (pconf->div_frac_start >> 8) & 0xff;
 410         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
 411         data = (pconf->div_frac_start >> 16) & 0xf;
 412         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
 413
 414         data = pconf->plllock_cmp & 0xff;
 415         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
 416
 417         data = (pconf->plllock_cmp >> 8) & 0xff;
 418         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
 419
 420         data = (pconf->plllock_cmp >> 16) & 0x3;
 421         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
 422
 423         data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */
 424         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
 425
 426         data = pconf->pll_vco_count & 0xff;
 427         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
 428         data = (pconf->pll_vco_count >> 8) & 0xff;
 429         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
 430
 431         data = pconf->pll_kvco_count & 0xff;
 432         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
 433         data = (pconf->pll_kvco_count >> 8) & 0x3;
 434         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
 435
 436         /*
 437          * High nibble configures the post divider internal to the VCO. It's
 438          * fixed to divide by 1 for now.
 439          *
 440          * 0: divided by 1
 441          * 1: divided by 2
 442          * 2: divided by 4
 443          * 3: divided by 8
 444          */
 445         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, 0 << 4 | 3);
 446
 447         if (pconf->ssc_en)
 448                 pll_db_commit_ssc(pll, pconf);
 449
 450         wmb();  /* make sure register committed */
 451 }
 452
 453 /*
 454  * VCO clock Callbacks
 455  */
 456 static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 457                                      unsigned long parent_rate)
 458 {
 459         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
 460         struct dsi_pll_config conf;
 461
 462         DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate,
 463             parent_rate);
 464
 465         dsi_pll_14nm_config_init(&conf);
 466         conf.vco_current_rate = rate;
 467
 468         pll_14nm_dec_frac_calc(pll_14nm, &conf);
 469
 470         if (conf.ssc_en)
 471                 pll_14nm_ssc_calc(pll_14nm, &conf);
 472
 473         pll_14nm_calc_vco_count(pll_14nm, &conf);
 474
 475         /* commit the slave DSI PLL registers if we're master. Note that we
 476          * don't lock the slave PLL. We just ensure that the PLL/PHY registers
 477          * of the master and slave are identical
 478          */
 479         if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
 480                 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
 481
 482                 pll_db_commit_14nm(pll_14nm_slave, &conf);
 483         }
 484
 485         pll_db_commit_14nm(pll_14nm, &conf);
 486
 487         return 0;
 488 }
 489
 490 static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
 491                                                   unsigned long parent_rate)
 492 {
 493         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
 494         void __iomem *base = pll_14nm->phy->pll_base;
 495         u64 vco_rate, multiplier = BIT(20);
 496         u32 div_frac_start;
 497         u32 dec_start;
 498         u64 ref_clk = parent_rate;
 499
 500         dec_start = dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
 501         dec_start &= 0x0ff;
 502
 503         DBG("dec_start = %x", dec_start);
 504
 505         div_frac_start = (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
 506                                 & 0xf) << 16;
 507         div_frac_start |= (dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
 508                                 & 0xff) << 8;
 509         div_frac_start |= dsi_phy_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
 510                                 & 0xff;
 511
 512         DBG("div_frac_start = %x", div_frac_start);
 513
 514         vco_rate = ref_clk * dec_start;
 515
 516         vco_rate += ((ref_clk * div_frac_start) / multiplier);
 517
 518         /*
 519          * Recalculating the rate from dec_start and frac_start doesn't end up
 520          * the rate we originally set. Convert the freq to KHz, round it up and
 521          * convert it back to MHz.
 522          */
 523         vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000;
 524
 525         DBG("returning vco rate = %lu", (unsigned long)vco_rate);
 526
 527         return (unsigned long)vco_rate;
 528 }
 529
 530 static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw)
 531 {
 532         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
 533         void __iomem *base = pll_14nm->phy->pll_base;
 534         void __iomem *cmn_base = pll_14nm->phy->base;
 535         bool locked;
 536
 537         DBG("");
 538
 539         if (unlikely(pll_14nm->phy->pll_on))
 540                 return 0;
 541
 542         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
 543         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
 544
 545         locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
 546                                          POLL_TIMEOUT_US);
 547
 548         if (unlikely(!locked)) {
 549                 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n");
 550                 return -EINVAL;
 551         }
 552
 553         DBG("DSI PLL lock success");
 554         pll_14nm->phy->pll_on = true;
 555
 556         return 0;
 557 }
 558
 559 static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw)
 560 {
 561         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
 562         void __iomem *cmn_base = pll_14nm->phy->base;
 563
 564         DBG("");
 565
 566         if (unlikely(!pll_14nm->phy->pll_on))
 567                 return;
 568
 569         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
 570
 571         pll_14nm->phy->pll_on = false;
 572 }
 573
 574 static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw,
 575                 unsigned long rate, unsigned long *parent_rate)
 576 {
 577         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw);
 578
 579         if      (rate < pll_14nm->phy->cfg->min_pll_rate)
 580                 return  pll_14nm->phy->cfg->min_pll_rate;
 581         else if (rate > pll_14nm->phy->cfg->max_pll_rate)
 582                 return  pll_14nm->phy->cfg->max_pll_rate;
 583         else
 584                 return rate;
 585 }
 586
 587 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
 588         .round_rate = dsi_pll_14nm_clk_round_rate,
 589         .set_rate = dsi_pll_14nm_vco_set_rate,
 590         .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
 591         .prepare = dsi_pll_14nm_vco_prepare,
 592         .unprepare = dsi_pll_14nm_vco_unprepare,
 593 };
 594
 595 /*
 596  * N1 and N2 post-divider clock callbacks
 597  */
 598 #define div_mask(width) ((1 << (width)) - 1)
 599 static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
 600                                                       unsigned long parent_rate)
 601 {
 602         struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
 603         struct dsi_pll_14nm *pll_14nm = postdiv->pll;
 604         void __iomem *base = pll_14nm->phy->base;
 605         u8 shift = postdiv->shift;
 606         u8 width = postdiv->width;
 607         u32 val;
 608
 609         DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate);
 610
 611         val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
 612         val &= div_mask(width);
 613
 614         return divider_recalc_rate(hw, parent_rate, val, NULL,
 615                                    postdiv->flags, width);
 616 }
 617
 618 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
 619                                             unsigned long rate,
 620                                             unsigned long *prate)
 621 {
 622         struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
 623         struct dsi_pll_14nm *pll_14nm = postdiv->pll;
 624
 625         DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate);
 626
 627         return divider_round_rate(hw, rate, prate, NULL,
 628                                   postdiv->width,
 629                                   postdiv->flags);
 630 }
 631
 632 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 633                                          unsigned long parent_rate)
 634 {
 635         struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
 636         struct dsi_pll_14nm *pll_14nm = postdiv->pll;
 637         void __iomem *base = pll_14nm->phy->base;
 638         spinlock_t *lock = &pll_14nm->postdiv_lock;
 639         u8 shift = postdiv->shift;
 640         u8 width = postdiv->width;
 641         unsigned int value;
 642         unsigned long flags = 0;
 643         u32 val;
 644
 645         DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate,
 646             parent_rate);
 647
 648         value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
 649                                 postdiv->flags);
 650
 651         spin_lock_irqsave(lock, flags);
 652
 653         val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 654         val &= ~(div_mask(width) << shift);
 655
 656         val |= value << shift;
 657         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
 658
 659         /* If we're master in bonded DSI mode, then the slave PLL's post-dividers
 660          * follow the master's post dividers
 661          */
 662         if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) {
 663                 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
 664                 void __iomem *slave_base = pll_14nm_slave->phy->base;
 665
 666                 dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
 667         }
 668
 669         spin_unlock_irqrestore(lock, flags);
 670
 671         return 0;
 672 }
 673
 674 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
 675         .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,
 676         .round_rate = dsi_pll_14nm_postdiv_round_rate,
 677         .set_rate = dsi_pll_14nm_postdiv_set_rate,
 678 };
 679
 680 /*
 681  * PLL Callbacks
 682  */
 683
 684 static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy)
 685 {
 686         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
 687         struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
 688         void __iomem *cmn_base = pll_14nm->phy->base;
 689         u32 data;
 690
 691         data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
 692
 693         cached_state->n1postdiv = data & 0xf;
 694         cached_state->n2postdiv = (data >> 4) & 0xf;
 695
 696         DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id,
 697             cached_state->n1postdiv, cached_state->n2postdiv);
 698
 699         cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw);
 700 }
 701
 702 static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy)
 703 {
 704         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
 705         struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
 706         void __iomem *cmn_base = pll_14nm->phy->base;
 707         u32 data;
 708         int ret;
 709
 710         ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw,
 711                                         cached_state->vco_rate, 0);
 712         if (ret) {
 713                 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev,
 714                         "restore vco rate failed. ret=%d\n", ret);
 715                 return ret;
 716         }
 717
 718         data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
 719
 720         DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id,
 721             cached_state->n1postdiv, cached_state->n2postdiv);
 722
 723         dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
 724
 725         /* also restore post-dividers for slave DSI PLL */
 726         if (phy->usecase == MSM_DSI_PHY_MASTER) {
 727                 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
 728                 void __iomem *slave_base = pll_14nm_slave->phy->base;
 729
 730                 dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy)
 737 {
 738         struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw);
 739         void __iomem *base = phy->pll_base;
 740         u32 clkbuflr_en, bandgap = 0;
 741
 742         switch (phy->usecase) {
 743         case MSM_DSI_PHY_STANDALONE:
 744                 clkbuflr_en = 0x1;
 745                 break;
 746         case MSM_DSI_PHY_MASTER:
 747                 clkbuflr_en = 0x3;
 748                 pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX];
 749                 break;
 750         case MSM_DSI_PHY_SLAVE:
 751                 clkbuflr_en = 0x0;
 752                 bandgap = 0x3;
 753                 break;
 754         default:
 755                 return -EINVAL;
 756         }
 757
 758         dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
 759         if (bandgap)
 760                 dsi_phy_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
 761
 762         return 0;
 763 }
 764
 765 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
 766                                                 const char *name,
 767                                                 const char *parent_name,
 768                                                 unsigned long flags,
 769                                                 u8 shift)
 770 {
 771         struct dsi_pll_14nm_postdiv *pll_postdiv;
 772         struct device *dev = &pll_14nm->phy->pdev->dev;
 773         struct clk_init_data postdiv_init = {
 774                 .parent_names = (const char *[]) { parent_name },
 775                 .num_parents = 1,
 776                 .name = name,
 777                 .flags = flags,
 778                 .ops = &clk_ops_dsi_pll_14nm_postdiv,
 779         };
 780         int ret;
 781
 782         pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
 783         if (!pll_postdiv)
 784                 return ERR_PTR(-ENOMEM);
 785
 786         pll_postdiv->pll = pll_14nm;
 787         pll_postdiv->shift = shift;
 788         /* both N1 and N2 postdividers are 4 bits wide */
 789         pll_postdiv->width = 4;
 790         /* range of each divider is from 1 to 15 */
 791         pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
 792         pll_postdiv->hw.init = &postdiv_init;
 793
 794         ret = devm_clk_hw_register(dev, &pll_postdiv->hw);
 795         if (ret)
 796                 return ERR_PTR(ret);
 797
 798         return &pll_postdiv->hw;
 799 }
 800
 801 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks)
 802 {
 803         char clk_name[32], parent[32], vco_name[32];
 804         struct clk_init_data vco_init = {
 805                 .parent_names = (const char *[]){ "xo" },
 806                 .num_parents = 1,
 807                 .name = vco_name,
 808                 .flags = CLK_IGNORE_UNUSED,
 809                 .ops = &clk_ops_dsi_pll_14nm_vco,
 810         };
 811         struct device *dev = &pll_14nm->phy->pdev->dev;
 812         struct clk_hw *hw;
 813         int ret;
 814
 815         DBG("DSI%d", pll_14nm->phy->id);
 816
 817         snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->phy->id);
 818         pll_14nm->clk_hw.init = &vco_init;
 819
 820         ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw);
 821         if (ret)
 822                 return ret;
 823
 824         snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
 825         snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->phy->id);
 826
 827         /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
 828         hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
 829                                        CLK_SET_RATE_PARENT, 0);
 830         if (IS_ERR(hw))
 831                 return PTR_ERR(hw);
 832
 833         snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->phy->id);
 834         snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
 835
 836         /* DSI Byte clock = VCO_CLK / N1 / 8 */
 837         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 838                                           CLK_SET_RATE_PARENT, 1, 8);
 839         if (IS_ERR(hw))
 840                 return PTR_ERR(hw);
 841
 842         provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 843
 844         snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
 845         snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->phy->id);
 846
 847         /*
 848          * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
 849          * on the way. Don't let it set parent.
 850          */
 851         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
 852         if (IS_ERR(hw))
 853                 return PTR_ERR(hw);
 854
 855         snprintf(clk_name, 32, "dsi%dpll", pll_14nm->phy->id);
 856         snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->phy->id);
 857
 858         /* DSI pixel clock = VCO_CLK / N1 / 2 / N2
 859          * This is the output of N2 post-divider, bits 4-7 in
 860          * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
 861          */
 862         hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4);
 863         if (IS_ERR(hw))
 864                 return PTR_ERR(hw);
 865
 866         provided_clocks[DSI_PIXEL_PLL_CLK]      = hw;
 867
 868         return 0;
 869 }
 870
 871 static int dsi_pll_14nm_init(struct msm_dsi_phy *phy)
 872 {
 873         struct platform_device *pdev = phy->pdev;
 874         struct dsi_pll_14nm *pll_14nm;
 875         int ret;
 876
 877         if (!pdev)
 878                 return -ENODEV;
 879
 880         pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
 881         if (!pll_14nm)
 882                 return -ENOMEM;
 883
 884         DBG("PLL%d", phy->id);
 885
 886         pll_14nm_list[phy->id] = pll_14nm;
 887
 888         spin_lock_init(&pll_14nm->postdiv_lock);
 889
 890         pll_14nm->phy = phy;
 891
 892         ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws);
 893         if (ret) {
 894                 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
 895                 return ret;
 896         }
 897
 898         phy->vco_hw = &pll_14nm->clk_hw;
 899
 900         return 0;
 901 }
 902
 903 static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
 904                                      struct msm_dsi_dphy_timing *timing,
 905                                      int lane_idx)
 906 {
 907         void __iomem *base = phy->lane_base;
 908         bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX);
 909         u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
 910         u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
 911         u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail;
 912         u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst;
 913         u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly;
 914         u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
 915                                    timing->hs_halfbyte_en;
 916
 917         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx),
 918                       DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
 919         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx),
 920                       DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero));
 921         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx),
 922                       DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare));
 923         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx),
 924                       DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail));
 925         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx),
 926                       DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst));
 927         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx),
 928                       DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly));
 929         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx),
 930                       halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0);
 931         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx),
 932                       DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
 933                       DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
 934         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx),
 935                       DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get));
 936         dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx),
 937                       DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
 938 }
 939
 940 static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy,
 941                                struct msm_dsi_phy_clk_request *clk_req)
 942 {
 943         struct msm_dsi_dphy_timing *timing = &phy->timing;
 944         u32 data;
 945         int i;
 946         int ret;
 947         void __iomem *base = phy->base;
 948         void __iomem *lane_base = phy->lane_base;
 949         u32 glbl_test_ctrl;
 950
 951         if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
 952                 DRM_DEV_ERROR(&phy->pdev->dev,
 953                         "%s: D-PHY timing calculation failed\n", __func__);
 954                 return -EINVAL;
 955         }
 956
 957         data = 0x1c;
 958         if (phy->usecase != MSM_DSI_PHY_STANDALONE)
 959                 data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32);
 960         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
 961
 962         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1);
 963
 964         /* 4 data lanes + 1 clk lane configuration */
 965         for (i = 0; i < 5; i++) {
 966                 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i),
 967                               0x1d);
 968
 969                 dsi_phy_write(lane_base +
 970                               REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff);
 971                 dsi_phy_write(lane_base +
 972                               REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i),
 973                               (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06);
 974
 975                 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i),
 976                               (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f);
 977                 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10);
 978                 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i),
 979                               0);
 980                 dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i),
 981                               0x88);
 982
 983                 dsi_14nm_dphy_set_timing(phy, timing, i);
 984         }
 985
 986         /* Make sure PLL is not start */
 987         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00);
 988
 989         wmb(); /* make sure everything is written before reset and enable */
 990
 991         /* reset digital block */
 992         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80);
 993         wmb(); /* ensure reset is asserted */
 994         udelay(100);
 995         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
 996
 997         glbl_test_ctrl = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL);
 998         if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE)
 999                 glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
1000         else
1001                 glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL;
1002         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, glbl_test_ctrl);
1003         ret = dsi_14nm_set_usecase(phy);
1004         if (ret) {
1005                 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
1006                         __func__, ret);
1007                 return ret;
1008         }
1009
1010         /* Remove power down from PLL and all lanes */
1011         dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff);
1012
1013         return 0;
1014 }
1015
1016 static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
1017 {
1018         dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0);
1019         dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0);
1020
1021         /* ensure that the phy is completely disabled */
1022         wmb();
1023 }
1024
1025 const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
1026         .has_phy_lane = true,
1027         .reg_cfg = {
1028                 .num = 1,
1029                 .regs = {
1030                         {"vcca", 17000, 32},
1031                 },
1032         },
1033         .ops = {
1034                 .enable = dsi_14nm_phy_enable,
1035                 .disable = dsi_14nm_phy_disable,
1036                 .pll_init = dsi_pll_14nm_init,
1037                 .save_pll_state = dsi_14nm_pll_save_state,
1038                 .restore_pll_state = dsi_14nm_pll_restore_state,
1039         },
1040         .min_pll_rate = VCO_MIN_RATE,
1041         .max_pll_rate = VCO_MAX_RATE,
1042         .io_start = { 0x994400, 0x996400 },
1043         .num_dsi_phy = 2,
1044 };
1045
1046 const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
1047         .has_phy_lane = true,
1048         .reg_cfg = {
1049                 .num = 1,
1050                 .regs = {
1051                         {"vcca", 73400, 32},
1052                 },
1053         },
1054         .ops = {
1055                 .enable = dsi_14nm_phy_enable,
1056                 .disable = dsi_14nm_phy_disable,
1057                 .pll_init = dsi_pll_14nm_init,
1058                 .save_pll_state = dsi_14nm_pll_save_state,
1059                 .restore_pll_state = dsi_14nm_pll_restore_state,
1060         },
1061         .min_pll_rate = VCO_MIN_RATE,
1062         .max_pll_rate = VCO_MAX_RATE,
1063         .io_start = { 0xc994400, 0xc996000 },
1064         .num_dsi_phy = 2,
1065 };
1066
1067 const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
1068         .has_phy_lane = true,
1069         .reg_cfg = {
1070                 .num = 1,
1071                 .regs = {
1072                         {"vcca", 17000, 32},
1073                 },
1074         },
1075         .ops = {
1076                 .enable = dsi_14nm_phy_enable,
1077                 .disable = dsi_14nm_phy_disable,
1078                 .pll_init = dsi_pll_14nm_init,
1079                 .save_pll_state = dsi_14nm_pll_save_state,
1080                 .restore_pll_state = dsi_14nm_pll_restore_state,
1081         },
1082         .min_pll_rate = VCO_MIN_RATE,
1083         .max_pll_rate = VCO_MAX_RATE,
1084         .io_start = { 0x1a94400, 0x1a96400 },
1085         .num_dsi_phy = 2,
1086 };