drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0
   3  * Copyright (c) 2018, The Linux Foundation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/iopoll.h>
   9
  10 #include "dsi_phy.h"
  11 #include "dsi.xml.h"
  12
  13 /*
  14  * DSI PLL 10nm - clock diagram (eg: DSI0):
  15  *
  16  *           dsi0_pll_out_div_clk  dsi0_pll_bit_clk
  17  *                              |                |
  18  *                              |                |
  19  *                 +---------+  |  +----------+  |  +----+
  20  *  dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
  21  *                 +---------+  |  +----------+  |  +----+
  22  *                              |                |
  23  *                              |                |         dsi0_pll_by_2_bit_clk
  24  *                              |                |          |
  25  *                              |                |  +----+  |  |\  dsi0_pclk_mux
  26  *                              |                |--| /2 |--o--| \   |
  27  *                              |                |  +----+     |  \  |  +---------+
  28  *                              |                --------------|  |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
  29  *                              |------------------------------|  /     +---------+
  30  *                              |          +-----+             | /
  31  *                              -----------| /4? |--o----------|/
  32  *                                         +-----+  |           |
  33  *                                                  |           |dsiclk_sel
  34  *                                                  |
  35  *                                                  dsi0_pll_post_out_div_clk
  36  */
  37
  38 #define VCO_REF_CLK_RATE                19200000
  39
  40 struct dsi_pll_regs {
  41         u32 pll_prop_gain_rate;
  42         u32 pll_lockdet_rate;
  43         u32 decimal_div_start;
  44         u32 frac_div_start_low;
  45         u32 frac_div_start_mid;
  46         u32 frac_div_start_high;
  47         u32 pll_clock_inverters;
  48         u32 ssc_stepsize_low;
  49         u32 ssc_stepsize_high;
  50         u32 ssc_div_per_low;
  51         u32 ssc_div_per_high;
  52         u32 ssc_adjper_low;
  53         u32 ssc_adjper_high;
  54         u32 ssc_control;
  55 };
  56
  57 /* v3.0.0 10nm implementation that requires the old timings settings */
  58 #define DSI_PHY_10NM_QUIRK_OLD_TIMINGS  BIT(0)
  59
  60 struct dsi_pll_config {
  61         u32 ref_freq;
  62         bool div_override;
  63         u32 output_div;
  64         bool ignore_frac;
  65         bool disable_prescaler;
  66         bool enable_ssc;
  67         bool ssc_center;
  68         u32 dec_bits;
  69         u32 frac_bits;
  70         u32 lock_timer;
  71         u32 ssc_freq;
  72         u32 ssc_offset;
  73         u32 ssc_adj_per;
  74         u32 thresh_cycles;
  75         u32 refclk_cycles;
  76 };
  77
  78 struct pll_10nm_cached_state {
  79         unsigned long vco_rate;
  80         u8 bit_clk_div;
  81         u8 pix_clk_div;
  82         u8 pll_out_div;
  83         u8 pll_mux;
  84 };
  85
  86 struct dsi_pll_10nm {
  87         struct clk_hw clk_hw;
  88
  89         struct msm_dsi_phy *phy;
  90
  91         u64 vco_ref_clk_rate;
  92         u64 vco_current_rate;
  93
  94         /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
  95         spinlock_t postdiv_lock;
  96
  97         struct dsi_pll_config pll_configuration;
  98         struct dsi_pll_regs reg_setup;
  99
 100         struct pll_10nm_cached_state cached_state;
 101
 102         struct dsi_pll_10nm *slave;
 103 };
 104
 105 #define to_pll_10nm(x)  container_of(x, struct dsi_pll_10nm, clk_hw)
 106
 107 /*
 108  * Global list of private DSI PLL struct pointers. We need this for Dual DSI
 109  * mode, where the master PLL's clk_ops needs access the slave's private data
 110  */
 111 static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX];
 112
 113 static void dsi_pll_setup_config(struct dsi_pll_10nm *pll)
 114 {
 115         struct dsi_pll_config *config = &pll->pll_configuration;
 116
 117         config->ref_freq = pll->vco_ref_clk_rate;
 118         config->output_div = 1;
 119         config->dec_bits = 8;
 120         config->frac_bits = 18;
 121         config->lock_timer = 64;
 122         config->ssc_freq = 31500;
 123         config->ssc_offset = 5000;
 124         config->ssc_adj_per = 2;
 125         config->thresh_cycles = 32;
 126         config->refclk_cycles = 256;
 127
 128         config->div_override = false;
 129         config->ignore_frac = false;
 130         config->disable_prescaler = false;
 131
 132         config->enable_ssc = false;
 133         config->ssc_center = 0;
 134 }
 135
 136 static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
 137 {
 138         struct dsi_pll_config *config = &pll->pll_configuration;
 139         struct dsi_pll_regs *regs = &pll->reg_setup;
 140         u64 fref = pll->vco_ref_clk_rate;
 141         u64 pll_freq;
 142         u64 divider;
 143         u64 dec, dec_multiple;
 144         u32 frac;
 145         u64 multiplier;
 146
 147         pll_freq = pll->vco_current_rate;
 148
 149         if (config->disable_prescaler)
 150                 divider = fref;
 151         else
 152                 divider = fref * 2;
 153
 154         multiplier = 1 << config->frac_bits;
 155         dec_multiple = div_u64(pll_freq * multiplier, divider);
 156         dec = div_u64_rem(dec_multiple, multiplier, &frac);
 157
 158         if (pll_freq <= 1900000000UL)
 159                 regs->pll_prop_gain_rate = 8;
 160         else if (pll_freq <= 3000000000UL)
 161                 regs->pll_prop_gain_rate = 10;
 162         else
 163                 regs->pll_prop_gain_rate = 12;
 164         if (pll_freq < 1100000000UL)
 165                 regs->pll_clock_inverters = 8;
 166         else
 167                 regs->pll_clock_inverters = 0;
 168
 169         regs->pll_lockdet_rate = config->lock_timer;
 170         regs->decimal_div_start = dec;
 171         regs->frac_div_start_low = (frac & 0xff);
 172         regs->frac_div_start_mid = (frac & 0xff00) >> 8;
 173         regs->frac_div_start_high = (frac & 0x30000) >> 16;
 174 }
 175
 176 #define SSC_CENTER              BIT(0)
 177 #define SSC_EN                  BIT(1)
 178
 179 static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
 180 {
 181         struct dsi_pll_config *config = &pll->pll_configuration;
 182         struct dsi_pll_regs *regs = &pll->reg_setup;
 183         u32 ssc_per;
 184         u32 ssc_mod;
 185         u64 ssc_step_size;
 186         u64 frac;
 187
 188         if (!config->enable_ssc) {
 189                 DBG("SSC not enabled\n");
 190                 return;
 191         }
 192
 193         ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
 194         ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
 195         ssc_per -= ssc_mod;
 196
 197         frac = regs->frac_div_start_low |
 198                         (regs->frac_div_start_mid << 8) |
 199                         (regs->frac_div_start_high << 16);
 200         ssc_step_size = regs->decimal_div_start;
 201         ssc_step_size *= (1 << config->frac_bits);
 202         ssc_step_size += frac;
 203         ssc_step_size *= config->ssc_offset;
 204         ssc_step_size *= (config->ssc_adj_per + 1);
 205         ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
 206         ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
 207
 208         regs->ssc_div_per_low = ssc_per & 0xFF;
 209         regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
 210         regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
 211         regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
 212         regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
 213         regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
 214
 215         regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
 216
 217         pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
 218                  regs->decimal_div_start, frac, config->frac_bits);
 219         pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
 220                  ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
 221 }
 222
 223 static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
 224 {
 225         void __iomem *base = pll->phy->pll_base;
 226         struct dsi_pll_regs *regs = &pll->reg_setup;
 227
 228         if (pll->pll_configuration.enable_ssc) {
 229                 pr_debug("SSC is enabled\n");
 230
 231                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
 232                           regs->ssc_stepsize_low);
 233                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
 234                           regs->ssc_stepsize_high);
 235                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
 236                           regs->ssc_div_per_low);
 237                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
 238                           regs->ssc_div_per_high);
 239                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
 240                           regs->ssc_adjper_low);
 241                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
 242                           regs->ssc_adjper_high);
 243                 dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
 244                           SSC_EN | regs->ssc_control);
 245         }
 246 }
 247
 248 static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
 249 {
 250         void __iomem *base = pll->phy->pll_base;
 251
 252         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
 253         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
 254         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
 255         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
 256         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
 257         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
 258         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
 259                   0xba);
 260         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
 261         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
 262         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
 263         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
 264         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
 265         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
 266         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa);
 267         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
 268                   0x4c);
 269         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
 270         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
 271         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
 272 }
 273
 274 static void dsi_pll_commit(struct dsi_pll_10nm *pll)
 275 {
 276         void __iomem *base = pll->phy->pll_base;
 277         struct dsi_pll_regs *reg = &pll->reg_setup;
 278
 279         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
 280         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
 281                   reg->decimal_div_start);
 282         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
 283                   reg->frac_div_start_low);
 284         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
 285                   reg->frac_div_start_mid);
 286         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
 287                   reg->frac_div_start_high);
 288         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1,
 289                   reg->pll_lockdet_rate);
 290         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
 291         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
 292         dsi_phy_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
 293                   reg->pll_clock_inverters);
 294 }
 295
 296 static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
 297                                      unsigned long parent_rate)
 298 {
 299         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 300
 301         DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
 302             parent_rate);
 303
 304         pll_10nm->vco_current_rate = rate;
 305         pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
 306
 307         dsi_pll_setup_config(pll_10nm);
 308
 309         dsi_pll_calc_dec_frac(pll_10nm);
 310
 311         dsi_pll_calc_ssc(pll_10nm);
 312
 313         dsi_pll_commit(pll_10nm);
 314
 315         dsi_pll_config_hzindep_reg(pll_10nm);
 316
 317         dsi_pll_ssc_commit(pll_10nm);
 318
 319         /* flush, ensure all register writes are done*/
 320         wmb();
 321
 322         return 0;
 323 }
 324
 325 static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
 326 {
 327         struct device *dev = &pll->phy->pdev->dev;
 328         int rc;
 329         u32 status = 0;
 330         u32 const delay_us = 100;
 331         u32 const timeout_us = 5000;
 332
 333         rc = readl_poll_timeout_atomic(pll->phy->pll_base +
 334                                        REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE,
 335                                        status,
 336                                        ((status & BIT(0)) > 0),
 337                                        delay_us,
 338                                        timeout_us);
 339         if (rc)
 340                 DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n",
 341                               pll->phy->id, status);
 342
 343         return rc;
 344 }
 345
 346 static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
 347 {
 348         u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
 349
 350         dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
 351         dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
 352                   data & ~BIT(5));
 353         ndelay(250);
 354 }
 355
 356 static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
 357 {
 358         u32 data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
 359
 360         dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0,
 361                   data | BIT(5));
 362         dsi_phy_write(pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
 363         ndelay(250);
 364 }
 365
 366 static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
 367 {
 368         u32 data;
 369
 370         data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
 371         dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
 372                   data & ~BIT(5));
 373 }
 374
 375 static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
 376 {
 377         u32 data;
 378
 379         data = dsi_phy_read(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
 380         dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
 381                   data | BIT(5));
 382 }
 383
 384 static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
 385 {
 386         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 387         struct device *dev = &pll_10nm->phy->pdev->dev;
 388         int rc;
 389
 390         dsi_pll_enable_pll_bias(pll_10nm);
 391         if (pll_10nm->slave)
 392                 dsi_pll_enable_pll_bias(pll_10nm->slave);
 393
 394         rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
 395         if (rc) {
 396                 DRM_DEV_ERROR(dev, "vco_set_rate failed, rc=%d\n", rc);
 397                 return rc;
 398         }
 399
 400         /* Start PLL */
 401         dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
 402                   0x01);
 403
 404         /*
 405          * ensure all PLL configurations are written prior to checking
 406          * for PLL lock.
 407          */
 408         wmb();
 409
 410         /* Check for PLL lock */
 411         rc = dsi_pll_10nm_lock_status(pll_10nm);
 412         if (rc) {
 413                 DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->phy->id);
 414                 goto error;
 415         }
 416
 417         pll_10nm->phy->pll_on = true;
 418
 419         dsi_pll_enable_global_clk(pll_10nm);
 420         if (pll_10nm->slave)
 421                 dsi_pll_enable_global_clk(pll_10nm->slave);
 422
 423         dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
 424                   0x01);
 425         if (pll_10nm->slave)
 426                 dsi_phy_write(pll_10nm->slave->phy->base +
 427                           REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
 428
 429 error:
 430         return rc;
 431 }
 432
 433 static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
 434 {
 435         dsi_phy_write(pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
 436         dsi_pll_disable_pll_bias(pll);
 437 }
 438
 439 static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
 440 {
 441         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 442
 443         /*
 444          * To avoid any stray glitches while abruptly powering down the PLL
 445          * make sure to gate the clock using the clock enable bit before
 446          * powering down the PLL
 447          */
 448         dsi_pll_disable_global_clk(pll_10nm);
 449         dsi_phy_write(pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
 450         dsi_pll_disable_sub(pll_10nm);
 451         if (pll_10nm->slave) {
 452                 dsi_pll_disable_global_clk(pll_10nm->slave);
 453                 dsi_pll_disable_sub(pll_10nm->slave);
 454         }
 455         /* flush, ensure all register writes are done */
 456         wmb();
 457         pll_10nm->phy->pll_on = false;
 458 }
 459
 460 static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
 461                                                   unsigned long parent_rate)
 462 {
 463         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 464         struct dsi_pll_config *config = &pll_10nm->pll_configuration;
 465         void __iomem *base = pll_10nm->phy->pll_base;
 466         u64 ref_clk = pll_10nm->vco_ref_clk_rate;
 467         u64 vco_rate = 0x0;
 468         u64 multiplier;
 469         u32 frac;
 470         u32 dec;
 471         u64 pll_freq, tmp64;
 472
 473         dec = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
 474         dec &= 0xff;
 475
 476         frac = dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
 477         frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
 478                   0xff) << 8);
 479         frac |= ((dsi_phy_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
 480                   0x3) << 16);
 481
 482         /*
 483          * TODO:
 484          *      1. Assumes prescaler is disabled
 485          */
 486         multiplier = 1 << config->frac_bits;
 487         pll_freq = dec * (ref_clk * 2);
 488         tmp64 = (ref_clk * 2 * frac);
 489         pll_freq += div_u64(tmp64, multiplier);
 490
 491         vco_rate = pll_freq;
 492
 493         DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
 494             pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);
 495
 496         return (unsigned long)vco_rate;
 497 }
 498
 499 static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
 500                 unsigned long rate, unsigned long *parent_rate)
 501 {
 502         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
 503
 504         if      (rate < pll_10nm->phy->cfg->min_pll_rate)
 505                 return  pll_10nm->phy->cfg->min_pll_rate;
 506         else if (rate > pll_10nm->phy->cfg->max_pll_rate)
 507                 return  pll_10nm->phy->cfg->max_pll_rate;
 508         else
 509                 return rate;
 510 }
 511
 512 static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
 513         .round_rate = dsi_pll_10nm_clk_round_rate,
 514         .set_rate = dsi_pll_10nm_vco_set_rate,
 515         .recalc_rate = dsi_pll_10nm_vco_recalc_rate,
 516         .prepare = dsi_pll_10nm_vco_prepare,
 517         .unprepare = dsi_pll_10nm_vco_unprepare,
 518 };
 519
 520 /*
 521  * PLL Callbacks
 522  */
 523
 524 static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)
 525 {
 526         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
 527         struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
 528         void __iomem *phy_base = pll_10nm->phy->base;
 529         u32 cmn_clk_cfg0, cmn_clk_cfg1;
 530
 531         cached->pll_out_div = dsi_phy_read(pll_10nm->phy->pll_base +
 532                                        REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
 533         cached->pll_out_div &= 0x3;
 534
 535         cmn_clk_cfg0 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
 536         cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
 537         cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
 538
 539         cmn_clk_cfg1 = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
 540         cached->pll_mux = cmn_clk_cfg1 & 0x3;
 541
 542         DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
 543             pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
 544             cached->pix_clk_div, cached->pll_mux);
 545 }
 546
 547 static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
 548 {
 549         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
 550         struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
 551         void __iomem *phy_base = pll_10nm->phy->base;
 552         u32 val;
 553         int ret;
 554
 555         val = dsi_phy_read(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
 556         val &= ~0x3;
 557         val |= cached->pll_out_div;
 558         dsi_phy_write(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
 559
 560         dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
 561                   cached->bit_clk_div | (cached->pix_clk_div << 4));
 562
 563         val = dsi_phy_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
 564         val &= ~0x3;
 565         val |= cached->pll_mux;
 566         dsi_phy_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
 567
 568         ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
 569                         pll_10nm->vco_current_rate,
 570                         pll_10nm->vco_ref_clk_rate);
 571         if (ret) {
 572                 DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
 573                         "restore vco rate failed. ret=%d\n", ret);
 574                 return ret;
 575         }
 576
 577         DBG("DSI PLL%d", pll_10nm->phy->id);
 578
 579         return 0;
 580 }
 581
 582 static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
 583 {
 584         struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
 585         void __iomem *base = phy->base;
 586         u32 data = 0x0; /* internal PLL */
 587
 588         DBG("DSI PLL%d", pll_10nm->phy->id);
 589
 590         switch (phy->usecase) {
 591         case MSM_DSI_PHY_STANDALONE:
 592                 break;
 593         case MSM_DSI_PHY_MASTER:
 594                 pll_10nm->slave = pll_10nm_list[(pll_10nm->phy->id + 1) % DSI_MAX];
 595                 break;
 596         case MSM_DSI_PHY_SLAVE:
 597                 data = 0x1; /* external PLL */
 598                 break;
 599         default:
 600                 return -EINVAL;
 601         }
 602
 603         /* set PLL src */
 604         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
 605
 606         return 0;
 607 }
 608
 609 /*
 610  * The post dividers and mux clocks are created using the standard divider and
 611  * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
 612  * state to follow the master PLL's divider/mux state. Therefore, we don't
 613  * require special clock ops that also configure the slave PLL registers
 614  */
 615 static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks)
 616 {
 617         char clk_name[32], parent[32], vco_name[32];
 618         char parent2[32], parent3[32], parent4[32];
 619         struct clk_init_data vco_init = {
 620                 .parent_names = (const char *[]){ "xo" },
 621                 .num_parents = 1,
 622                 .name = vco_name,
 623                 .flags = CLK_IGNORE_UNUSED,
 624                 .ops = &clk_ops_dsi_pll_10nm_vco,
 625         };
 626         struct device *dev = &pll_10nm->phy->pdev->dev;
 627         struct clk_hw *hw;
 628         int ret;
 629
 630         DBG("DSI%d", pll_10nm->phy->id);
 631
 632         snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->phy->id);
 633         pll_10nm->clk_hw.init = &vco_init;
 634
 635         ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
 636         if (ret)
 637                 return ret;
 638
 639         snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
 640         snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->phy->id);
 641
 642         hw = devm_clk_hw_register_divider(dev, clk_name,
 643                                      parent, CLK_SET_RATE_PARENT,
 644                                      pll_10nm->phy->pll_base +
 645                                      REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
 646                                      0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
 647         if (IS_ERR(hw)) {
 648                 ret = PTR_ERR(hw);
 649                 goto fail;
 650         }
 651
 652         snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
 653         snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
 654
 655         /* BIT CLK: DIV_CTRL_3_0 */
 656         hw = devm_clk_hw_register_divider(dev, clk_name, parent,
 657                                      CLK_SET_RATE_PARENT,
 658                                      pll_10nm->phy->base +
 659                                      REG_DSI_10nm_PHY_CMN_CLK_CFG0,
 660                                      0, 4, CLK_DIVIDER_ONE_BASED,
 661                                      &pll_10nm->postdiv_lock);
 662         if (IS_ERR(hw)) {
 663                 ret = PTR_ERR(hw);
 664                 goto fail;
 665         }
 666
 667         snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);
 668         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
 669
 670         /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
 671         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 672                                           CLK_SET_RATE_PARENT, 1, 8);
 673         if (IS_ERR(hw)) {
 674                 ret = PTR_ERR(hw);
 675                 goto fail;
 676         }
 677
 678         provided_clocks[DSI_BYTE_PLL_CLK] = hw;
 679
 680         snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
 681         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
 682
 683         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 684                                           0, 1, 2);
 685         if (IS_ERR(hw)) {
 686                 ret = PTR_ERR(hw);
 687                 goto fail;
 688         }
 689
 690         snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
 691         snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
 692
 693         hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
 694                                           0, 1, 4);
 695         if (IS_ERR(hw)) {
 696                 ret = PTR_ERR(hw);
 697                 goto fail;
 698         }
 699
 700         snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
 701         snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->phy->id);
 702         snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
 703         snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
 704         snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
 705
 706         hw = devm_clk_hw_register_mux(dev, clk_name,
 707                                  ((const char *[]){
 708                                  parent, parent2, parent3, parent4
 709                                  }), 4, 0, pll_10nm->phy->base +
 710                                  REG_DSI_10nm_PHY_CMN_CLK_CFG1,
 711                                  0, 2, 0, NULL);
 712         if (IS_ERR(hw)) {
 713                 ret = PTR_ERR(hw);
 714                 goto fail;
 715         }
 716
 717         snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id);
 718         snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->phy->id);
 719
 720         /* PIX CLK DIV : DIV_CTRL_7_4*/
 721         hw = devm_clk_hw_register_divider(dev, clk_name, parent,
 722                                      0, pll_10nm->phy->base +
 723                                         REG_DSI_10nm_PHY_CMN_CLK_CFG0,
 724                                      4, 4, CLK_DIVIDER_ONE_BASED,
 725                                      &pll_10nm->postdiv_lock);
 726         if (IS_ERR(hw)) {
 727                 ret = PTR_ERR(hw);
 728                 goto fail;
 729         }
 730
 731         provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
 732
 733         return 0;
 734
 735 fail:
 736
 737         return ret;
 738 }
 739
 740 static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
 741 {
 742         struct platform_device *pdev = phy->pdev;
 743         struct dsi_pll_10nm *pll_10nm;
 744         int ret;
 745
 746         pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
 747         if (!pll_10nm)
 748                 return -ENOMEM;
 749
 750         DBG("DSI PLL%d", phy->id);
 751
 752         pll_10nm_list[phy->id] = pll_10nm;
 753
 754         spin_lock_init(&pll_10nm->postdiv_lock);
 755
 756         pll_10nm->phy = phy;
 757
 758         ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
 759         if (ret) {
 760                 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
 761                 return ret;
 762         }
 763
 764         phy->vco_hw = &pll_10nm->clk_hw;
 765
 766         /* TODO: Remove this when we have proper display handover support */
 767         msm_dsi_phy_pll_save_state(phy);
 768
 769         return 0;
 770 }
 771
 772 static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy)
 773 {
 774         void __iomem *base = phy->base;
 775         u32 data = 0;
 776
 777         data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
 778         mb(); /* make sure read happened */
 779
 780         return (data & BIT(0));
 781 }
 782
 783 static void dsi_phy_hw_v3_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
 784 {
 785         void __iomem *lane_base = phy->lane_base;
 786         int phy_lane_0 = 0;     /* TODO: Support all lane swap configs */
 787
 788         /*
 789          * LPRX and CDRX need to enabled only for physical data lane
 790          * corresponding to the logical data lane 0
 791          */
 792         if (enable)
 793                 dsi_phy_write(lane_base +
 794                               REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0x3);
 795         else
 796                 dsi_phy_write(lane_base +
 797                               REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0), 0);
 798 }
 799
 800 static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
 801 {
 802         int i;
 803         u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
 804         void __iomem *lane_base = phy->lane_base;
 805
 806         if (phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)
 807                 tx_dctrl[3] = 0x02;
 808
 809         /* Strength ctrl settings */
 810         for (i = 0; i < 5; i++) {
 811                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i),
 812                               0x55);
 813                 /*
 814                  * Disable LPRX and CDRX for all lanes. And later on, it will
 815                  * be only enabled for the physical data lane corresponding
 816                  * to the logical data lane 0
 817                  */
 818                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0);
 819                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0);
 820                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i),
 821                               0x88);
 822         }
 823
 824         dsi_phy_hw_v3_0_config_lpcdrx(phy, true);
 825
 826         /* other settings */
 827         for (i = 0; i < 5; i++) {
 828                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0);
 829                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0);
 830                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0);
 831                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i),
 832                               i == 4 ? 0x80 : 0x0);
 833                 dsi_phy_write(lane_base +
 834                               REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i), 0x0);
 835                 dsi_phy_write(lane_base +
 836                               REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i), 0x0);
 837                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i),
 838                               tx_dctrl[i]);
 839         }
 840
 841         if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) {
 842                 /* Toggle BIT 0 to release freeze I/0 */
 843                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
 844                 dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
 845         }
 846 }
 847
 848 static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 849                                struct msm_dsi_phy_clk_request *clk_req)
 850 {
 851         int ret;
 852         u32 status;
 853         u32 const delay_us = 5;
 854         u32 const timeout_us = 1000;
 855         struct msm_dsi_dphy_timing *timing = &phy->timing;
 856         void __iomem *base = phy->base;
 857         u32 data;
 858
 859         DBG("");
 860
 861         if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) {
 862                 DRM_DEV_ERROR(&phy->pdev->dev,
 863                         "%s: D-PHY timing calculation failed\n", __func__);
 864                 return -EINVAL;
 865         }
 866
 867         if (dsi_phy_hw_v3_0_is_pll_on(phy))
 868                 pr_warn("PLL turned on before configuring PHY\n");
 869
 870         /* wait for REFGEN READY */
 871         ret = readl_poll_timeout_atomic(base + REG_DSI_10nm_PHY_CMN_PHY_STATUS,
 872                                         status, (status & BIT(0)),
 873                                         delay_us, timeout_us);
 874         if (ret) {
 875                 pr_err("Ref gen not ready. Aborting\n");
 876                 return -EINVAL;
 877         }
 878
 879         /* de-assert digital and pll power down */
 880         data = BIT(6) | BIT(5);
 881         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
 882
 883         /* Assert PLL core reset */
 884         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00);
 885
 886         /* turn off resync FIFO */
 887         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x00);
 888
 889         /* Select MS1 byte-clk */
 890         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL, 0x10);
 891
 892         /* Enable LDO */
 893         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_VREG_CTRL, 0x59);
 894
 895         /* Configure PHY lane swap (TODO: we need to calculate this) */
 896         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG0, 0x21);
 897         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CFG1, 0x84);
 898
 899         /* DSI PHY timings */
 900         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0,
 901                       timing->hs_halfbyte_en);
 902         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1,
 903                       timing->clk_zero);
 904         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2,
 905                       timing->clk_prepare);
 906         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3,
 907                       timing->clk_trail);
 908         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4,
 909                       timing->hs_exit);
 910         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5,
 911                       timing->hs_zero);
 912         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6,
 913                       timing->hs_prepare);
 914         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7,
 915                       timing->hs_trail);
 916         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8,
 917                       timing->hs_rqst);
 918         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9,
 919                       timing->ta_go | (timing->ta_sure << 3));
 920         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10,
 921                       timing->ta_get);
 922         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11,
 923                       0x00);
 924
 925         /* Remove power down from all blocks */
 926         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x7f);
 927
 928         /* power up lanes */
 929         data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
 930
 931         /* TODO: only power up lanes that are used */
 932         data |= 0x1F;
 933         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
 934         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0x1F);
 935
 936         /* Select full-rate mode */
 937         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_2, 0x40);
 938
 939         ret = dsi_10nm_set_usecase(phy);
 940         if (ret) {
 941                 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
 942                         __func__, ret);
 943                 return ret;
 944         }
 945
 946         /* DSI lane settings */
 947         dsi_phy_hw_v3_0_lane_settings(phy);
 948
 949         DBG("DSI%d PHY enabled", phy->id);
 950
 951         return 0;
 952 }
 953
 954 static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
 955 {
 956         void __iomem *base = phy->base;
 957         u32 data;
 958
 959         DBG("");
 960
 961         if (dsi_phy_hw_v3_0_is_pll_on(phy))
 962                 pr_warn("Turning OFF PHY while PLL is on\n");
 963
 964         dsi_phy_hw_v3_0_config_lpcdrx(phy, false);
 965         data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
 966
 967         /* disable all lanes */
 968         data &= ~0x1F;
 969         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, data);
 970         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0, 0);
 971
 972         /* Turn off all PHY blocks */
 973         dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_CTRL_0, 0x00);
 974         /* make sure phy is turned off */
 975         wmb();
 976
 977         DBG("DSI%d PHY disabled", phy->id);
 978 }
 979
 980 const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
 981         .src_pll_truthtable = { {false, false}, {true, false} },
 982         .has_phy_lane = true,
 983         .reg_cfg = {
 984                 .num = 1,
 985                 .regs = {
 986                         {"vdds", 36000, 32},
 987                 },
 988         },
 989         .ops = {
 990                 .enable = dsi_10nm_phy_enable,
 991                 .disable = dsi_10nm_phy_disable,
 992                 .pll_init = dsi_pll_10nm_init,
 993                 .save_pll_state = dsi_10nm_pll_save_state,
 994                 .restore_pll_state = dsi_10nm_pll_restore_state,
 995         },
 996         .min_pll_rate = 1000000000UL,
 997         .max_pll_rate = 3500000000UL,
 998         .io_start = { 0xae94400, 0xae96400 },
 999         .num_dsi_phy = 2,
1000 };
1001
1002 const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
1003         .src_pll_truthtable = { {false, false}, {true, false} },
1004         .has_phy_lane = true,
1005         .reg_cfg = {
1006                 .num = 1,
1007                 .regs = {
1008                         {"vdds", 36000, 32},
1009                 },
1010         },
1011         .ops = {
1012                 .enable = dsi_10nm_phy_enable,
1013                 .disable = dsi_10nm_phy_disable,
1014                 .pll_init = dsi_pll_10nm_init,
1015                 .save_pll_state = dsi_10nm_pll_save_state,
1016                 .restore_pll_state = dsi_10nm_pll_restore_state,
1017         },
1018         .min_pll_rate = 1000000000UL,
1019         .max_pll_rate = 3500000000UL,
1020         .io_start = { 0xc994400, 0xc996400 },
1021         .num_dsi_phy = 2,
1022         .quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,
1023 };