1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/platform_device.h>
11 #define S_DIV_ROUND_UP(n, d) \
12 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
14 static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
15 s32 min_result, bool even)
19 v = (tmax - tmin) * percent;
20 v = S_DIV_ROUND_UP(v, 100) + tmin;
21 if (even && (v & 0x1))
22 return max_t(s32, min_result, v - 1);
24 return max_t(s32, min_result, v);
27 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
28 s32 ui, s32 coeff, s32 pcnt)
30 s32 tmax, tmin, clk_z;
34 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
35 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
38 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
41 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
45 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
46 timing->clk_zero = clk_z + 8 - temp;
49 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
50 struct msm_dsi_phy_clk_request *clk_req)
52 const unsigned long bit_rate = clk_req->bitclk_rate;
53 const unsigned long esc_rate = clk_req->escclk_rate;
57 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
59 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
60 s32 coeff = 1000; /* Precision, should avoid overflow */
63 if (!bit_rate || !esc_rate)
66 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
67 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
69 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
70 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
71 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
75 timing->hs_rqst = temp;
77 timing->hs_rqst = max_t(s32, 0, temp - 2);
79 /* Calculate clk_zero after clk_prepare and hs_rqst */
80 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
82 temp = 105 * coeff + 12 * ui - 20 * coeff;
83 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
84 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
85 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
87 temp = 85 * coeff + 6 * ui;
88 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
89 temp = 40 * coeff + 4 * ui;
90 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
91 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
94 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
95 temp = 145 * coeff + 10 * ui - temp;
96 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
97 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
99 temp = 105 * coeff + 12 * ui - 20 * coeff;
100 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
101 temp = 60 * coeff + 4 * ui;
102 tmin = DIV_ROUND_UP(temp, ui) - 2;
103 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
106 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
107 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
110 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
111 temp = 60 * coeff + 52 * ui - 24 * ui - temp;
112 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
113 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
116 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
117 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
118 temp += 8 * ui + lpx;
119 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
121 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
122 timing->shared_timings.clk_pre = temp >> 1;
123 timing->shared_timings.clk_pre_inc_by_2 = true;
125 timing->shared_timings.clk_pre =
126 linear_inter(tmax, tmin, pcnt2, 0, false);
127 timing->shared_timings.clk_pre_inc_by_2 = false;
134 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
135 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
136 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
137 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
138 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
144 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
145 struct msm_dsi_phy_clk_request *clk_req)
147 const unsigned long bit_rate = clk_req->bitclk_rate;
148 const unsigned long esc_rate = clk_req->escclk_rate;
157 s32 coeff = 1000; /* Precision, should avoid overflow */
158 s32 hb_en, hb_en_ckln, pd_ckln, pd;
162 if (!bit_rate || !esc_rate)
165 timing->hs_halfbyte_en = 0;
167 timing->hs_halfbyte_en_ckln = 0;
169 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
170 pd_ckln = timing->hs_prep_dly_ckln;
171 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
172 pd = timing->hs_prep_dly;
174 val = (hb_en << 2) + (pd << 1);
175 val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
177 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
180 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
181 tmin = max_t(s32, temp, 0);
182 temp = (95 * coeff - val_ckln * ui) / ui_x8;
183 tmax = max_t(s32, temp, 0);
184 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
186 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
187 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
188 tmax = (tmin > 255) ? 511 : 255;
189 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
191 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
192 temp = 105 * coeff + 12 * ui - 20 * coeff;
193 tmax = (temp + 3 * ui) / ui_x8;
194 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
196 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
197 tmin = max_t(s32, temp, 0);
198 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
199 tmax = max_t(s32, temp, 0);
200 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
202 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
203 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
205 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
207 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
208 temp = 105 * coeff + 12 * ui - 20 * coeff;
209 tmax = (temp + 3 * ui) / ui_x8;
210 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
212 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
213 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
215 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
217 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
219 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
220 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
222 temp = 60 * coeff + 52 * ui - 43 * ui;
223 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
225 timing->shared_timings.clk_post =
226 linear_inter(tmax, tmin, pcnt2, 0, false);
228 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
229 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
230 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
231 (((timing->hs_rqst_ckln << 3) + 8) * ui);
232 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
235 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
236 timing->shared_timings.clk_pre = temp >> 1;
237 timing->shared_timings.clk_pre_inc_by_2 = 1;
239 timing->shared_timings.clk_pre =
240 linear_inter(tmax, tmin, pcnt2, 0, false);
241 timing->shared_timings.clk_pre_inc_by_2 = 0;
248 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
249 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
250 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
251 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
252 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
253 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
254 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
255 timing->hs_prep_dly_ckln);
260 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
261 struct msm_dsi_phy_clk_request *clk_req)
263 const unsigned long bit_rate = clk_req->bitclk_rate;
264 const unsigned long esc_rate = clk_req->escclk_rate;
273 s32 coeff = 1000; /* Precision, should avoid overflow */
274 s32 hb_en, hb_en_ckln;
277 if (!bit_rate || !esc_rate)
280 timing->hs_halfbyte_en = 0;
282 timing->hs_halfbyte_en_ckln = 0;
285 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
288 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
289 tmin = max_t(s32, temp, 0);
290 temp = (95 * coeff) / ui_x8;
291 tmax = max_t(s32, temp, 0);
292 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
294 temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
295 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
296 tmax = (tmin > 255) ? 511 : 255;
297 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
299 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
300 temp = 105 * coeff + 12 * ui - 20 * coeff;
301 tmax = (temp + 3 * ui) / ui_x8;
302 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
304 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
305 tmin = max_t(s32, temp, 0);
306 temp = (85 * coeff + 6 * ui) / ui_x8;
307 tmax = max_t(s32, temp, 0);
308 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
310 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
311 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
313 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
315 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
316 temp = 105 * coeff + 12 * ui - 20 * coeff;
317 tmax = (temp / ui_x8) - 1;
318 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
320 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
321 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
323 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
325 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
327 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
328 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
330 temp = 60 * coeff + 52 * ui - 43 * ui;
331 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
333 timing->shared_timings.clk_post =
334 linear_inter(tmax, tmin, pcnt2, 0, false);
336 temp = 8 * ui + (timing->clk_prepare << 3) * ui;
337 temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
338 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
339 (((timing->hs_rqst_ckln << 3) + 8) * ui);
340 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
343 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
344 timing->shared_timings.clk_pre = temp >> 1;
345 timing->shared_timings.clk_pre_inc_by_2 = 1;
347 timing->shared_timings.clk_pre =
348 linear_inter(tmax, tmin, pcnt2, 0, false);
349 timing->shared_timings.clk_pre_inc_by_2 = 0;
356 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
357 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
358 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
359 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
360 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
361 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
362 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
363 timing->hs_prep_dly_ckln);
368 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
369 struct msm_dsi_phy_clk_request *clk_req)
371 const unsigned long bit_rate = clk_req->bitclk_rate;
372 const unsigned long esc_rate = clk_req->escclk_rate;
375 s32 pcnt_clk_prep = 50;
376 s32 pcnt_clk_zero = 2;
377 s32 pcnt_clk_trail = 30;
378 s32 pcnt_hs_prep = 50;
379 s32 pcnt_hs_zero = 10;
380 s32 pcnt_hs_trail = 30;
381 s32 pcnt_hs_exit = 10;
382 s32 coeff = 1000; /* Precision, should avoid overflow */
386 if (!bit_rate || !esc_rate)
391 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
394 /* TODO: verify these calculations against latest downstream driver
395 * everything except clk_post/clk_pre uses calculations from v3 based
396 * on the downstream driver having the same calculations for v3 and v4
399 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
400 tmin = max_t(s32, temp, 0);
401 temp = (95 * coeff) / ui_x8;
402 tmax = max_t(s32, temp, 0);
403 timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false);
405 temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
406 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
407 tmax = (tmin > 255) ? 511 : 255;
408 timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false);
410 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
411 temp = 105 * coeff + 12 * ui - 20 * coeff;
412 tmax = (temp + 3 * ui) / ui_x8;
413 timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false);
415 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
416 tmin = max_t(s32, temp, 0);
417 temp = (85 * coeff + 6 * ui) / ui_x8;
418 tmax = max_t(s32, temp, 0);
419 timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false);
421 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
422 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
424 timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false);
426 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
427 temp = 105 * coeff + 12 * ui - 20 * coeff;
428 tmax = (temp / ui_x8) - 1;
429 timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false);
431 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
432 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
434 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
436 timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false);
439 * = roundup((mipi_min_ns + t_hs_trail_ns)/(16*bit_clk_ns), 0) - 1
441 temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8;
442 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
444 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false);
447 * val1 = (tlpx_ns + clk_prepare_ns + clk_zero_ns + hs_rqst_ns)
448 * val2 = (16 * bit_clk_ns)
449 * final = roundup(val1/val2, 0) - 1
451 temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff;
452 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
454 timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin;
456 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
457 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
458 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,
459 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst);
464 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
467 int phy_id = phy->id;
470 if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
473 val = dsi_phy_read(phy->base + reg);
475 if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
476 dsi_phy_write(phy->base + reg, val | bit_mask);
478 dsi_phy_write(phy->base + reg, val & (~bit_mask));
481 static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
483 struct regulator_bulk_data *s = phy->supplies;
484 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
485 struct device *dev = &phy->pdev->dev;
486 int num = phy->cfg->reg_cfg.num;
489 for (i = 0; i < num; i++)
490 s[i].supply = regs[i].name;
492 ret = devm_regulator_bulk_get(dev, num, s);
494 if (ret != -EPROBE_DEFER) {
496 "%s: failed to init regulator, ret=%d\n",
506 static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
508 struct regulator_bulk_data *s = phy->supplies;
509 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
510 int num = phy->cfg->reg_cfg.num;
514 for (i = num - 1; i >= 0; i--)
515 if (regs[i].disable_load >= 0)
516 regulator_set_load(s[i].consumer, regs[i].disable_load);
518 regulator_bulk_disable(num, s);
521 static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
523 struct regulator_bulk_data *s = phy->supplies;
524 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
525 struct device *dev = &phy->pdev->dev;
526 int num = phy->cfg->reg_cfg.num;
530 for (i = 0; i < num; i++) {
531 if (regs[i].enable_load >= 0) {
532 ret = regulator_set_load(s[i].consumer,
533 regs[i].enable_load);
536 "regulator %d set op mode failed, %d\n",
543 ret = regulator_bulk_enable(num, s);
545 DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);
552 for (i--; i >= 0; i--)
553 regulator_set_load(s[i].consumer, regs[i].disable_load);
557 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
559 struct device *dev = &phy->pdev->dev;
562 pm_runtime_get_sync(dev);
564 ret = clk_prepare_enable(phy->ahb_clk);
566 DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
567 pm_runtime_put_sync(dev);
573 static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
575 clk_disable_unprepare(phy->ahb_clk);
576 pm_runtime_put_autosuspend(&phy->pdev->dev);
579 static const struct of_device_id dsi_phy_dt_match[] = {
580 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
581 { .compatible = "qcom,dsi-phy-28nm-hpm",
582 .data = &dsi_phy_28nm_hpm_cfgs },
583 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
584 .data = &dsi_phy_28nm_hpm_famb_cfgs },
585 { .compatible = "qcom,dsi-phy-28nm-lp",
586 .data = &dsi_phy_28nm_lp_cfgs },
588 #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
589 { .compatible = "qcom,dsi-phy-20nm",
590 .data = &dsi_phy_20nm_cfgs },
592 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
593 { .compatible = "qcom,dsi-phy-28nm-8960",
594 .data = &dsi_phy_28nm_8960_cfgs },
596 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
597 { .compatible = "qcom,dsi-phy-14nm",
598 .data = &dsi_phy_14nm_cfgs },
599 { .compatible = "qcom,dsi-phy-14nm-660",
600 .data = &dsi_phy_14nm_660_cfgs },
602 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
603 { .compatible = "qcom,dsi-phy-10nm",
604 .data = &dsi_phy_10nm_cfgs },
605 { .compatible = "qcom,dsi-phy-10nm-8998",
606 .data = &dsi_phy_10nm_8998_cfgs },
608 #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
609 { .compatible = "qcom,dsi-phy-7nm",
610 .data = &dsi_phy_7nm_cfgs },
611 { .compatible = "qcom,dsi-phy-7nm-8150",
612 .data = &dsi_phy_7nm_8150_cfgs },
618 * Currently, we only support one SoC for each PHY type. When we have multiple
619 * SoCs for the same PHY, we can try to make the index searching a bit more
622 static int dsi_phy_get_id(struct msm_dsi_phy *phy)
624 struct platform_device *pdev = phy->pdev;
625 const struct msm_dsi_phy_cfg *cfg = phy->cfg;
626 struct resource *res;
629 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
633 for (i = 0; i < cfg->num_dsi_phy; i++) {
634 if (cfg->io_start[i] == res->start)
641 static int dsi_phy_driver_probe(struct platform_device *pdev)
643 struct msm_dsi_phy *phy;
644 struct device *dev = &pdev->dev;
645 const struct of_device_id *match;
648 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
652 match = of_match_node(dsi_phy_dt_match, dev->of_node);
656 phy->provided_clocks = devm_kzalloc(dev,
657 struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS),
659 if (!phy->provided_clocks)
662 phy->provided_clocks->num = NUM_PROVIDED_CLKS;
664 phy->cfg = match->data;
667 phy->id = dsi_phy_get_id(phy);
670 DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",
675 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
676 "qcom,dsi-phy-regulator-ldo-mode");
678 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
679 if (IS_ERR(phy->base)) {
680 DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
685 if (phy->cfg->has_phy_lane) {
686 phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", "DSI_PHY_LANE");
687 if (IS_ERR(phy->lane_base)) {
688 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n", __func__);
694 if (phy->cfg->has_phy_regulator) {
695 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
696 if (IS_ERR(phy->reg_base)) {
697 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n", __func__);
703 ret = dsi_phy_regulator_init(phy);
707 phy->ahb_clk = msm_clk_get(pdev, "iface");
708 if (IS_ERR(phy->ahb_clk)) {
709 DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__);
710 ret = PTR_ERR(phy->ahb_clk);
714 /* PLL init will call into clk_register which requires
715 * register access, so we need to enable power and ahb clock.
717 ret = dsi_phy_enable_resource(phy);
721 if (phy->cfg->ops.pll_init) {
722 ret = phy->cfg->ops.pll_init(phy);
725 "%s: pll init failed: %d, need separate pll clk driver\n",
731 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
732 phy->provided_clocks);
734 DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret);
738 dsi_phy_disable_resource(phy);
740 platform_set_drvdata(pdev, phy);
748 static struct platform_driver dsi_phy_platform_driver = {
749 .probe = dsi_phy_driver_probe,
751 .name = "msm_dsi_phy",
752 .of_match_table = dsi_phy_dt_match,
756 void __init msm_dsi_phy_driver_register(void)
758 platform_driver_register(&dsi_phy_platform_driver);
761 void __exit msm_dsi_phy_driver_unregister(void)
763 platform_driver_unregister(&dsi_phy_platform_driver);
766 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
767 struct msm_dsi_phy_clk_request *clk_req)
769 struct device *dev = &phy->pdev->dev;
772 if (!phy || !phy->cfg->ops.enable)
775 ret = dsi_phy_enable_resource(phy);
777 DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
782 ret = dsi_phy_regulator_enable(phy);
784 DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
789 ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
791 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
796 * Resetting DSI PHY silently changes its PLL registers to reset status,
797 * which will confuse clock driver and result in wrong output rate of
798 * link clocks. Restore PLL status if its PLL is being used as clock
801 if (phy->usecase != MSM_DSI_PHY_SLAVE) {
802 ret = msm_dsi_phy_pll_restore_state(phy);
804 DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n",
806 goto pll_restor_fail;
813 if (phy->cfg->ops.disable)
814 phy->cfg->ops.disable(phy);
816 dsi_phy_regulator_disable(phy);
818 dsi_phy_disable_resource(phy);
823 void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
825 if (!phy || !phy->cfg->ops.disable)
828 phy->cfg->ops.disable(phy);
830 dsi_phy_regulator_disable(phy);
831 dsi_phy_disable_resource(phy);
834 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
835 struct msm_dsi_phy_shared_timings *shared_timings)
837 memcpy(shared_timings, &phy->timing.shared_timings,
838 sizeof(*shared_timings));
841 void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
842 enum msm_dsi_phy_usecase uc)
848 int msm_dsi_phy_get_clk_provider(struct msm_dsi_phy *phy,
849 struct clk **byte_clk_provider, struct clk **pixel_clk_provider)
851 if (byte_clk_provider)
852 *byte_clk_provider = phy->provided_clocks->hws[DSI_BYTE_PLL_CLK]->clk;
853 if (pixel_clk_provider)
854 *pixel_clk_provider = phy->provided_clocks->hws[DSI_PIXEL_PLL_CLK]->clk;
859 void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy)
861 if (phy->cfg->ops.save_pll_state) {
862 phy->cfg->ops.save_pll_state(phy);
863 phy->state_saved = true;
867 int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy)
871 if (phy->cfg->ops.restore_pll_state && phy->state_saved) {
872 ret = phy->cfg->ops.restore_pll_state(phy);
876 phy->state_saved = false;