1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
8 #include <linux/types.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/phy/phy.h>
12 #include <linux/phy/phy-dp.h>
13 #include <linux/pm_opp.h>
14 #include <drm/drm_fixed.h>
15 #include <drm/dp/drm_dp_helper.h>
16 #include <drm/drm_print.h>
22 #define DP_KHZ_TO_HZ 1000
23 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
24 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
26 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
27 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
29 #define MR_LINK_TRAINING1 0x8
30 #define MR_LINK_SYMBOL_ERM 0x80
31 #define MR_LINK_PRBS7 0x100
32 #define MR_LINK_CUSTOM80 0x200
33 #define MR_LINK_TRAINING4 0x40
41 struct dp_tu_calc_input {
42 u64 lclk; /* 162, 270, 540 and 810 */
43 u64 pclk_khz; /* in KHz */
44 u64 hactive; /* active h-width */
45 u64 hporch; /* bp + fp + pulse */
46 int nlanes; /* no.of.lanes */
48 int pixel_enc; /* 444, 420, 422 */
49 int dsc_en; /* dsc on/off */
50 int async_en; /* async mode */
52 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
53 int num_of_dsc_slices; /* number of slices per line */
56 struct dp_vc_tu_mapping_table {
59 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
61 u8 valid_boundary_link;
63 bool boundary_moderation_en;
64 u8 valid_lower_boundary_link;
65 u8 upper_boundary_count;
66 u8 lower_boundary_count;
70 struct dp_ctrl_private {
71 struct dp_ctrl dp_ctrl;
73 struct drm_dp_aux *aux;
74 struct dp_panel *panel;
76 struct dp_power *power;
77 struct dp_parser *parser;
78 struct dp_catalog *catalog;
80 struct completion idle_comp;
81 struct completion video_comp;
84 static int dp_aux_link_configure(struct drm_dp_aux *aux,
85 struct dp_link_info *link)
90 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
91 values[1] = link->num_lanes;
93 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
94 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
96 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
103 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
105 struct dp_ctrl_private *ctrl;
107 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
109 reinit_completion(&ctrl->idle_comp);
110 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
112 if (!wait_for_completion_timeout(&ctrl->idle_comp,
113 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
114 pr_warn("PUSH_IDLE pattern timedout\n");
116 DRM_DEBUG_DP("mainlink off done\n");
119 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
122 const u8 *dpcd = ctrl->panel->dpcd;
124 /* Default-> LSCLK DIV: 1/4 LCLK */
125 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
127 /* Scrambler reset enable */
128 if (drm_dp_alternate_scrambler_reset_cap(dpcd))
129 config |= DP_CONFIGURATION_CTRL_ASSR;
131 tbd = dp_link_get_test_bits_depth(ctrl->link,
132 ctrl->panel->dp_mode.bpp);
134 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
135 pr_debug("BIT_DEPTH not set. Configure default\n");
136 tbd = DP_TEST_BIT_DEPTH_8;
139 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
142 config |= ((ctrl->link->link_params.num_lanes - 1)
143 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
145 if (drm_dp_enhanced_frame_cap(dpcd))
146 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
148 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
150 /* sync clock & static Mvid */
151 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
152 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
154 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
157 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
161 dp_catalog_ctrl_lane_mapping(ctrl->catalog);
162 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
164 dp_ctrl_config_ctrl(ctrl);
166 tb = dp_link_get_test_bits_depth(ctrl->link,
167 ctrl->panel->dp_mode.bpp);
168 cc = dp_link_get_colorimetry_config(ctrl->link);
169 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
170 dp_panel_timing_cfg(ctrl->panel);
174 * The structure and few functions present below are IP/Hardware
175 * specific implementation. Most of the implementation will not
176 * have coding comments
178 struct tu_algo_data {
183 s64 hbp_relative_to_pclk;
184 s64 hbp_relative_to_pclk_fp;
192 uint delay_start_link_extra_pixclk;
193 int extra_buffer_margin;
195 s64 original_ratio_fp;
204 int valid_boundary_link;
205 s64 resulting_valid_fp;
207 s64 effective_valid_fp;
208 s64 effective_valid_recorded_fp;
213 int remainder_tus_upper;
214 int remainder_tus_lower;
217 int delay_start_link;
219 int extra_pclk_cycles;
220 int extra_pclk_cycles_in_link_clk;
222 s64 average_valid2_fp;
223 int new_valid_boundary_link;
224 int remainder_symbols_exist;
226 s64 n_remainder_symbols_per_lane_fp;
227 s64 last_partial_tu_fp;
230 int n_tus_incl_last_incomplete_tu;
231 int extra_pclk_cycles_tmp;
232 int extra_pclk_cycles_in_link_clk_tmp;
233 int extra_required_bytes_new_tmp;
235 int lower_filler_size_tmp;
236 int delay_start_link_tmp;
238 bool boundary_moderation_en;
239 int boundary_mod_lower_err;
240 int upper_boundary_count;
241 int lower_boundary_count;
242 int i_upper_boundary_count;
243 int i_lower_boundary_count;
244 int valid_lower_boundary_link;
245 int even_distribution_BF;
246 int even_distribution_legacy;
247 int even_distribution;
248 int min_hblank_violated;
249 s64 delay_start_time_fp;
257 static int _tu_param_compare(s64 a, s64 b)
261 s64 a_temp, b_temp, minus_1;
266 minus_1 = drm_fixp_from_fraction(-1, 1);
268 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
270 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
274 else if (b_sign > a_sign)
277 if (!a_sign && !b_sign) { /* positive */
282 } else { /* negative */
283 a_temp = drm_fixp_mul(a, minus_1);
284 b_temp = drm_fixp_mul(b, minus_1);
293 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
294 struct tu_algo_data *tu)
296 int nlanes = in->nlanes;
297 int dsc_num_slices = in->num_of_dsc_slices;
298 int dsc_num_bytes = 0;
304 int tot_num_eoc_symbols = 0;
305 int tot_num_hor_bytes = 0;
306 int tot_num_dummy_bytes = 0;
307 int dwidth_dsc_bytes = 0;
310 s64 temp1_fp, temp2_fp, temp3_fp;
312 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
313 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
314 tu->lwidth = in->hactive;
315 tu->hbp_relative_to_pclk = in->hporch;
316 tu->nlanes = in->nlanes;
318 tu->pixelEnc = in->pixel_enc;
319 tu->dsc_en = in->dsc_en;
320 tu->async_en = in->async_en;
321 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
322 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
324 if (tu->pixelEnc == 420) {
325 temp1_fp = drm_fixp_from_fraction(2, 1);
326 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
327 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
328 tu->hbp_relative_to_pclk_fp =
329 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
332 if (tu->pixelEnc == 422) {
354 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
355 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
356 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
357 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
359 temp1_fp = drm_fixp_from_fraction(8, 1);
360 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
362 numerator = drm_fixp2int(temp3_fp);
364 dsc_num_bytes = numerator / dsc_num_slices;
365 eoc_bytes = dsc_num_bytes % nlanes;
366 tot_num_eoc_symbols = nlanes * dsc_num_slices;
367 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
368 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
370 if (dsc_num_bytes == 0)
371 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
373 dwidth_dsc_bytes = (tot_num_hor_bytes +
374 tot_num_eoc_symbols +
375 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
377 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
379 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
380 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
381 pclk_dsc_fp = temp1_fp;
383 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
384 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
385 hbp_dsc_fp = temp2_fp;
388 tu->pclk_fp = pclk_dsc_fp;
389 tu->lwidth_fp = dwidth_dsc_fp;
390 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
394 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
395 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
399 static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
401 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
402 int compare_result_1, compare_result_2, compare_result_3;
404 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
405 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
407 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
409 temp = (tu->i_upper_boundary_count *
410 tu->new_valid_boundary_link +
411 tu->i_lower_boundary_count *
412 (tu->new_valid_boundary_link-1));
413 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
414 (tu->i_upper_boundary_count +
415 tu->i_lower_boundary_count));
417 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
418 temp2_fp = tu->lwidth_fp;
419 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
420 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
421 tu->n_tus = drm_fixp2int(temp2_fp);
422 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
425 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
426 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
427 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
428 temp2_fp = temp1_fp - temp2_fp;
429 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
430 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
431 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
433 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
434 tu->last_partial_tu_fp =
435 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
438 if (tu->n_remainder_symbols_per_lane_fp != 0)
439 tu->remainder_symbols_exist = 1;
441 tu->remainder_symbols_exist = 0;
443 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
444 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
446 tu->paired_tus = (int)((tu->n_tus_per_lane) /
447 (tu->i_upper_boundary_count +
448 tu->i_lower_boundary_count));
450 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
451 (tu->i_upper_boundary_count +
452 tu->i_lower_boundary_count);
454 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
455 tu->remainder_tus_upper = tu->i_upper_boundary_count;
456 tu->remainder_tus_lower = tu->remainder_tus -
457 tu->i_upper_boundary_count;
459 tu->remainder_tus_upper = tu->remainder_tus;
460 tu->remainder_tus_lower = 0;
463 temp = tu->paired_tus * (tu->i_upper_boundary_count *
464 tu->new_valid_boundary_link +
465 tu->i_lower_boundary_count *
466 (tu->new_valid_boundary_link - 1)) +
467 (tu->remainder_tus_upper *
468 tu->new_valid_boundary_link) +
469 (tu->remainder_tus_lower *
470 (tu->new_valid_boundary_link - 1));
471 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
473 if (tu->remainder_symbols_exist) {
474 temp1_fp = tu->total_valid_fp +
475 tu->n_remainder_symbols_per_lane_fp;
476 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
477 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
478 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
480 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
481 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
483 tu->effective_valid_fp = temp1_fp;
485 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
486 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
487 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
489 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
490 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
491 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
493 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
495 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
496 temp2_fp = tu->lwidth_fp;
497 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
498 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
501 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
503 tu->n_tus_incl_last_incomplete_tu = 0;
506 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
507 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
508 temp1_fp = tu->average_valid2_fp - temp2_fp;
509 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
510 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
513 temp1 = drm_fixp2int_ceil(temp1_fp);
515 temp = tu->i_upper_boundary_count * tu->nlanes;
516 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
517 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
518 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
519 temp2_fp = temp1_fp - temp2_fp;
520 temp1_fp = drm_fixp_from_fraction(temp, 1);
521 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
524 temp2 = drm_fixp2int_ceil(temp2_fp);
527 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
529 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
530 temp2_fp = drm_fixp_from_fraction(
531 tu->extra_required_bytes_new_tmp, 1);
532 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
535 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
537 tu->extra_pclk_cycles_tmp = 0;
539 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
540 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
541 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
544 tu->extra_pclk_cycles_in_link_clk_tmp =
545 drm_fixp2int_ceil(temp1_fp);
547 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
549 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
551 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
553 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
554 tu->lower_filler_size_tmp +
555 tu->extra_buffer_margin;
557 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
558 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
560 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
561 if (compare_result_1 == 2)
562 compare_result_1 = 1;
564 compare_result_1 = 0;
566 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
567 if (compare_result_2 == 2)
568 compare_result_2 = 1;
570 compare_result_2 = 0;
572 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
573 tu->delay_start_time_fp);
574 if (compare_result_3 == 2)
575 compare_result_3 = 0;
577 compare_result_3 = 1;
579 if (((tu->even_distribution == 1) ||
580 ((tu->even_distribution_BF == 0) &&
581 (tu->even_distribution_legacy == 0))) &&
582 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
584 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
585 (tu->new_valid_boundary_link - 1) > 0 &&
587 (tu->delay_start_link_tmp <= 1023)) {
588 tu->upper_boundary_count = tu->i_upper_boundary_count;
589 tu->lower_boundary_count = tu->i_lower_boundary_count;
590 tu->err_fp = tu->n_n_err_fp;
591 tu->boundary_moderation_en = true;
592 tu->tu_size_desired = tu->tu_size;
593 tu->valid_boundary_link = tu->new_valid_boundary_link;
594 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
595 tu->even_distribution_BF = 1;
596 tu->delay_start_link = tu->delay_start_link_tmp;
597 } else if (tu->boundary_mod_lower_err == 0) {
598 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
600 if (compare_result_1 == 2)
601 tu->boundary_mod_lower_err = 1;
605 static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in,
606 struct dp_vc_tu_mapping_table *tu_table)
608 struct tu_algo_data *tu;
609 int compare_result_1, compare_result_2;
611 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
613 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
614 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
615 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
616 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
618 u8 DP_BRUTE_FORCE = 1;
619 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
620 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
621 uint HBLANK_MARGIN = 4;
623 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
627 dp_panel_update_tu_timings(in, tu);
629 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
631 temp1_fp = drm_fixp_from_fraction(4, 1);
632 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
633 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
634 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
636 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
637 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
638 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
639 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
640 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
642 tu->original_ratio_fp = tu->ratio_fp;
643 tu->boundary_moderation_en = false;
644 tu->upper_boundary_count = 0;
645 tu->lower_boundary_count = 0;
646 tu->i_upper_boundary_count = 0;
647 tu->i_lower_boundary_count = 0;
648 tu->valid_lower_boundary_link = 0;
649 tu->even_distribution_BF = 0;
650 tu->even_distribution_legacy = 0;
651 tu->even_distribution = 0;
652 tu->delay_start_time_fp = 0;
654 tu->err_fp = drm_fixp_from_fraction(1000, 1);
658 tu->ratio = drm_fixp2int(tu->ratio_fp);
659 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
660 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
662 !tu->ratio && tu->dsc_en == 0) {
663 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
664 tu->ratio = drm_fixp2int(tu->ratio_fp);
666 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
675 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
676 if (!compare_result_1 || compare_result_1 == 1)
677 compare_result_1 = 1;
679 compare_result_1 = 0;
681 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
682 if (!compare_result_2 || compare_result_2 == 2)
683 compare_result_2 = 1;
685 compare_result_2 = 0;
687 if (tu->dsc_en && compare_result_1 && compare_result_2) {
689 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n",
694 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
695 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
696 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
697 temp = drm_fixp2int_ceil(temp2_fp);
698 temp1_fp = drm_fixp_from_fraction(temp, 1);
699 tu->n_err_fp = temp1_fp - temp2_fp;
701 if (tu->n_err_fp < tu->err_fp) {
702 tu->err_fp = tu->n_err_fp;
703 tu->tu_size_desired = tu->tu_size;
707 tu->tu_size_minus1 = tu->tu_size_desired - 1;
709 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
710 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
711 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
713 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
714 temp2_fp = tu->lwidth_fp;
715 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
717 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
718 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
719 tu->n_tus = drm_fixp2int(temp2_fp);
720 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
723 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
724 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n",
725 tu->valid_boundary_link, tu->n_tus);
727 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
728 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
729 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
730 temp2_fp = temp1_fp - temp2_fp;
731 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
732 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
734 temp = drm_fixp2int(temp2_fp);
735 if (temp && temp2_fp)
736 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
740 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
741 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
742 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
744 if (temp && temp1_fp)
745 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
747 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
749 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
750 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
751 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
754 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
756 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
758 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
760 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
761 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
763 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
764 tu->filler_size + tu->extra_buffer_margin;
766 tu->resulting_valid_fp =
767 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
769 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
770 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
771 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
773 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
774 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
775 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
777 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
778 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
780 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
781 tu->delay_start_time_fp);
782 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
783 tu->min_hblank_violated = 1;
785 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
787 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
788 tu->delay_start_time_fp);
789 if (compare_result_2 == 2)
790 tu->min_hblank_violated = 1;
792 tu->delay_start_time_fp = 0;
796 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
797 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
799 temp = drm_fixp2int(tu->diff_abs_fp);
800 if (!temp && tu->diff_abs_fp <= 0xffff)
803 /* if(diff_abs < 0) diff_abs *= -1 */
804 if (tu->diff_abs_fp < 0)
805 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
807 tu->boundary_mod_lower_err = 0;
808 if ((tu->diff_abs_fp != 0 &&
809 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
810 (tu->even_distribution_legacy == 0) ||
811 (DP_BRUTE_FORCE == 1))) ||
812 (tu->min_hblank_violated == 1)) {
814 tu->err_fp = drm_fixp_from_fraction(1000, 1);
816 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
817 temp2_fp = drm_fixp_from_fraction(
818 tu->delay_start_link_extra_pixclk, 1);
819 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
822 tu->extra_buffer_margin =
823 drm_fixp2int_ceil(temp1_fp);
825 tu->extra_buffer_margin = 0;
827 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
828 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
831 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
835 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
836 for (tu->i_upper_boundary_count = 1;
837 tu->i_upper_boundary_count <= 15;
838 tu->i_upper_boundary_count++) {
839 for (tu->i_lower_boundary_count = 1;
840 tu->i_lower_boundary_count <= 15;
841 tu->i_lower_boundary_count++) {
842 _tu_valid_boundary_calc(tu);
846 tu->delay_start_link_extra_pixclk--;
847 } while (tu->boundary_moderation_en != true &&
848 tu->boundary_mod_lower_err == 1 &&
849 tu->delay_start_link_extra_pixclk != 0);
851 if (tu->boundary_moderation_en == true) {
852 temp1_fp = drm_fixp_from_fraction(
853 (tu->upper_boundary_count *
854 tu->valid_boundary_link +
855 tu->lower_boundary_count *
856 (tu->valid_boundary_link - 1)), 1);
857 temp2_fp = drm_fixp_from_fraction(
858 (tu->upper_boundary_count +
859 tu->lower_boundary_count), 1);
860 tu->resulting_valid_fp =
861 drm_fixp_div(temp1_fp, temp2_fp);
863 temp1_fp = drm_fixp_from_fraction(
864 tu->tu_size_desired, 1);
866 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
868 tu->valid_lower_boundary_link =
869 tu->valid_boundary_link - 1;
871 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
872 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
873 temp2_fp = drm_fixp_div(temp1_fp,
874 tu->resulting_valid_fp);
875 tu->n_tus = drm_fixp2int(temp2_fp);
877 tu->tu_size_minus1 = tu->tu_size_desired - 1;
878 tu->even_distribution_BF = 1;
881 drm_fixp_from_fraction(tu->tu_size_desired, 1);
883 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
884 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
888 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
891 temp = drm_fixp2int_ceil(temp2_fp);
895 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
896 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
897 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
898 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
899 temp1_fp = drm_fixp_from_fraction(temp, 1);
900 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
901 temp = drm_fixp2int(temp2_fp);
904 tu->delay_start_link += (int)temp;
906 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
907 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
910 tu_table->valid_boundary_link = tu->valid_boundary_link;
911 tu_table->delay_start_link = tu->delay_start_link;
912 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
913 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
914 tu_table->upper_boundary_count = tu->upper_boundary_count;
915 tu_table->lower_boundary_count = tu->lower_boundary_count;
916 tu_table->tu_size_minus1 = tu->tu_size_minus1;
918 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n",
919 tu_table->valid_boundary_link);
920 DRM_DEBUG_DP("TU: delay_start_link: %d\n",
921 tu_table->delay_start_link);
922 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n",
923 tu_table->boundary_moderation_en);
924 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n",
925 tu_table->valid_lower_boundary_link);
926 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n",
927 tu_table->upper_boundary_count);
928 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n",
929 tu_table->lower_boundary_count);
930 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1);
935 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
936 struct dp_vc_tu_mapping_table *tu_table)
938 struct dp_tu_calc_input in;
939 struct drm_display_mode *drm_mode;
941 drm_mode = &ctrl->panel->dp_mode.drm_mode;
943 in.lclk = ctrl->link->link_params.rate / 1000;
944 in.pclk_khz = drm_mode->clock;
945 in.hactive = drm_mode->hdisplay;
946 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
947 in.nlanes = ctrl->link->link_params.num_lanes;
948 in.bpp = ctrl->panel->dp_mode.bpp;
953 in.num_of_dsc_slices = 0;
954 in.compress_ratio = 100;
956 _dp_ctrl_calc_tu(&in, tu_table);
959 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
962 u32 valid_boundary = 0x0;
963 u32 valid_boundary2 = 0x0;
964 struct dp_vc_tu_mapping_table tu_calc_table;
966 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
968 dp_tu |= tu_calc_table.tu_size_minus1;
969 valid_boundary |= tu_calc_table.valid_boundary_link;
970 valid_boundary |= (tu_calc_table.delay_start_link << 16);
972 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
973 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
974 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
976 if (tu_calc_table.boundary_moderation_en)
977 valid_boundary2 |= BIT(0);
979 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
980 dp_tu, valid_boundary, valid_boundary2);
982 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
983 dp_tu, valid_boundary, valid_boundary2);
986 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
990 if (!wait_for_completion_timeout(&ctrl->video_comp,
991 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
992 DRM_ERROR("wait4video timedout\n");
998 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1000 struct dp_link *link = ctrl->link;
1001 int ret = 0, lane, lane_cnt;
1003 u32 max_level_reached = 0;
1004 u32 voltage_swing_level = link->phy_params.v_level;
1005 u32 pre_emphasis_level = link->phy_params.p_level;
1007 DRM_DEBUG_DP("voltage level: %d emphasis level: %d\n", voltage_swing_level,
1008 pre_emphasis_level);
1009 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1010 voltage_swing_level, pre_emphasis_level);
1015 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1016 DRM_DEBUG_DP("max. voltage swing level reached %d\n",
1017 voltage_swing_level);
1018 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1021 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1022 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n",
1023 pre_emphasis_level);
1024 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1027 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1029 lane_cnt = ctrl->link->link_params.num_lanes;
1030 for (lane = 0; lane < lane_cnt; lane++)
1031 buf[lane] = voltage_swing_level | pre_emphasis_level
1032 | max_level_reached;
1034 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level
1035 | pre_emphasis_level);
1036 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1038 if (ret == lane_cnt)
1044 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1050 DRM_DEBUG_DP("sink: pattern=%x\n", pattern);
1054 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1055 buf |= DP_LINK_SCRAMBLING_DISABLE;
1057 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1061 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1066 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1067 if (len != DP_LINK_STATUS_SIZE) {
1068 DRM_ERROR("DP link status read failed, err: %d\n", len);
1075 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1078 int tries, old_v_level, ret = 0;
1079 u8 link_status[DP_LINK_STATUS_SIZE];
1080 int const maximum_retries = 4;
1082 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1084 *training_step = DP_TRAINING_1;
1086 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, 1);
1089 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1090 DP_LINK_SCRAMBLING_DISABLE);
1092 ret = dp_ctrl_update_vx_px(ctrl);
1097 old_v_level = ctrl->link->phy_params.v_level;
1098 for (tries = 0; tries < maximum_retries; tries++) {
1099 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd);
1101 ret = dp_ctrl_read_link_status(ctrl, link_status);
1105 if (drm_dp_clock_recovery_ok(link_status,
1106 ctrl->link->link_params.num_lanes)) {
1110 if (ctrl->link->phy_params.v_level >=
1111 DP_TRAIN_VOLTAGE_SWING_MAX) {
1112 DRM_ERROR_RATELIMITED("max v_level reached\n");
1116 if (old_v_level != ctrl->link->phy_params.v_level) {
1118 old_v_level = ctrl->link->phy_params.v_level;
1121 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n");
1123 dp_link_adjust_levels(ctrl->link, link_status);
1124 ret = dp_ctrl_update_vx_px(ctrl);
1129 DRM_ERROR("max tries reached\n");
1133 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1137 switch (ctrl->link->link_params.rate) {
1139 ctrl->link->link_params.rate = 540000;
1142 ctrl->link->link_params.rate = 270000;
1145 ctrl->link->link_params.rate = 162000;
1154 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate);
1159 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1162 if (ctrl->link->link_params.num_lanes == 1)
1165 ctrl->link->link_params.num_lanes /= 2;
1166 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1168 ctrl->link->phy_params.p_level = 0;
1169 ctrl->link->phy_params.v_level = 0;
1174 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1176 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1177 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1180 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1183 int tries = 0, ret = 0;
1186 int const maximum_retries = 5;
1187 u8 link_status[DP_LINK_STATUS_SIZE];
1189 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1191 *training_step = DP_TRAINING_2;
1193 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1194 pattern = DP_TRAINING_PATTERN_4;
1196 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1197 pattern = DP_TRAINING_PATTERN_3;
1200 pattern = DP_TRAINING_PATTERN_2;
1204 ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit);
1208 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN);
1210 for (tries = 0; tries <= maximum_retries; tries++) {
1211 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd);
1213 ret = dp_ctrl_read_link_status(ctrl, link_status);
1217 if (drm_dp_channel_eq_ok(link_status,
1218 ctrl->link->link_params.num_lanes)) {
1222 dp_link_adjust_levels(ctrl->link, link_status);
1223 ret = dp_ctrl_update_vx_px(ctrl);
1232 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);
1234 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1238 const u8 *dpcd = ctrl->panel->dpcd;
1239 u8 encoding = DP_SET_ANSI_8B10B;
1242 struct dp_link_info link_info = {0};
1244 dp_ctrl_config_ctrl(ctrl);
1246 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1247 link_info.rate = ctrl->link->link_params.rate;
1248 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1250 dp_aux_link_configure(ctrl->aux, &link_info);
1252 if (drm_dp_max_downspread(dpcd)) {
1253 ssc = DP_SPREAD_AMP_0_5;
1254 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
1257 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1260 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
1261 assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
1262 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1266 ret = dp_ctrl_link_train_1(ctrl, training_step);
1268 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1272 /* print success info as this is a result of user initiated action */
1273 DRM_DEBUG_DP("link training #1 successful\n");
1275 ret = dp_ctrl_link_train_2(ctrl, training_step);
1277 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1281 /* print success info as this is a result of user initiated action */
1282 DRM_DEBUG_DP("link training #2 successful\n");
1285 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1290 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1295 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1297 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1301 * As part of previous calls, DP controller state might have
1302 * transitioned to PUSH_IDLE. In order to start transmitting
1303 * a link training pattern, we have to first do soft reset.
1306 ret = dp_ctrl_link_train(ctrl, training_step);
1311 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1312 enum dp_pm_type module, char *name, unsigned long rate)
1314 u32 num = ctrl->parser->mp[module].num_clk;
1315 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
1317 while (num && strcmp(cfg->clk_name, name)) {
1322 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
1327 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1331 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1334 struct dp_io *dp_io = &ctrl->parser->io;
1335 struct phy *phy = dp_io->phy;
1336 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1337 const u8 *dpcd = ctrl->panel->dpcd;
1339 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1340 opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1341 opts_dp->ssc = drm_dp_max_downspread(dpcd);
1342 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
1343 ctrl->link->link_params.rate * 1000);
1345 phy_configure(phy, &dp_io->phy_opts);
1348 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1350 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1352 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1353 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1358 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
1362 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1363 ctrl->dp_ctrl.pixel_rate * 1000);
1365 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1367 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
1369 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1370 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1375 void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
1377 struct dp_ctrl_private *ctrl;
1379 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1381 dp_catalog_ctrl_reset(ctrl->catalog);
1384 dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
1387 void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
1389 struct dp_ctrl_private *ctrl;
1390 struct dp_io *dp_io;
1393 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1394 dp_io = &ctrl->parser->io;
1397 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1399 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n",
1400 phy, phy->init_count, phy->power_count);
1403 void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
1405 struct dp_ctrl_private *ctrl;
1406 struct dp_io *dp_io;
1409 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1410 dp_io = &ctrl->parser->io;
1413 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1415 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n",
1416 phy, phy->init_count, phy->power_count);
1419 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1421 const u8 *dpcd = ctrl->panel->dpcd;
1424 * For better interop experience, used a fixed NVID=0x8000
1425 * whenever connected to a VGA dongle downstream.
1427 if (drm_dp_is_branch(dpcd))
1428 return (drm_dp_has_quirk(&ctrl->panel->desc,
1429 DP_DPCD_QUIRK_CONSTANT_N));
1434 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1437 struct dp_io *dp_io = &ctrl->parser->io;
1438 struct phy *phy = dp_io->phy;
1439 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1441 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1442 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1443 phy_configure(phy, &dp_io->phy_opts);
1445 * Disable and re-enable the mainlink clock since the
1446 * link clock might have been adjusted as part of the
1449 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1451 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1455 /* hw recommended delay before re-enabling clocks */
1458 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1460 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1467 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1469 struct dp_io *dp_io;
1473 dp_io = &ctrl->parser->io;
1476 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1478 dp_catalog_ctrl_reset(ctrl->catalog);
1480 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1482 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1487 /* aux channel down, reinit phy */
1491 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n",
1492 phy, phy->init_count, phy->power_count);
1496 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1499 int training_step = DP_TRAINING_NONE;
1501 dp_ctrl_push_idle(&ctrl->dp_ctrl);
1503 ctrl->link->phy_params.p_level = 0;
1504 ctrl->link->phy_params.v_level = 0;
1506 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1508 ret = dp_ctrl_setup_main_link(ctrl, &training_step);
1512 dp_ctrl_clear_training_pattern(ctrl);
1514 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1516 ret = dp_ctrl_wait4video_ready(ctrl);
1521 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1525 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1526 DRM_DEBUG_DP("no test pattern selected by sink\n");
1531 * The global reset will need DP link related clocks to be
1532 * running. Add the global reset just before disabling the
1533 * link clocks and core clocks.
1535 ret = dp_ctrl_off_link_stream(&ctrl->dp_ctrl);
1537 DRM_ERROR("failed to disable DP controller\n");
1541 ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1543 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
1545 DRM_ERROR("failed to enable DP link controller\n");
1550 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1552 bool success = false;
1553 u32 pattern_sent = 0x0;
1554 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1556 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested);
1558 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1559 ctrl->link->phy_params.v_level,
1560 ctrl->link->phy_params.p_level)) {
1561 DRM_ERROR("Failed to set v/p levels\n");
1564 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1565 dp_ctrl_update_vx_px(ctrl);
1566 dp_link_send_test_response(ctrl->link);
1568 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1570 switch (pattern_sent) {
1571 case MR_LINK_TRAINING1:
1572 success = (pattern_requested ==
1573 DP_PHY_TEST_PATTERN_D10_2);
1575 case MR_LINK_SYMBOL_ERM:
1576 success = ((pattern_requested ==
1577 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1578 (pattern_requested ==
1579 DP_PHY_TEST_PATTERN_CP2520));
1582 success = (pattern_requested ==
1583 DP_PHY_TEST_PATTERN_PRBS7);
1585 case MR_LINK_CUSTOM80:
1586 success = (pattern_requested ==
1587 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1589 case MR_LINK_TRAINING4:
1590 success = (pattern_requested ==
1591 DP_PHY_TEST_PATTERN_SEL_MASK);
1597 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed",
1602 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1604 struct dp_ctrl_private *ctrl;
1605 u32 sink_request = 0x0;
1608 DRM_ERROR("invalid input\n");
1612 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1613 sink_request = ctrl->link->sink_request;
1615 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1616 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n");
1617 if (dp_ctrl_process_phy_test_request(ctrl)) {
1618 DRM_ERROR("process phy_test_req failed\n");
1623 if (sink_request & DP_LINK_STATUS_UPDATED) {
1624 if (dp_ctrl_link_maintenance(ctrl)) {
1625 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1630 if (sink_request & DP_TEST_LINK_TRAINING) {
1631 dp_link_send_test_response(ctrl->link);
1632 if (dp_ctrl_link_maintenance(ctrl)) {
1633 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1639 static bool dp_ctrl_clock_recovery_any_ok(
1640 const u8 link_status[DP_LINK_STATUS_SIZE],
1645 if (lane_count <= 1)
1649 * only interested in the lane number after reduced
1650 * lane_count = 4, then only interested in 2 lanes
1651 * lane_count = 2, then only interested in 1 lane
1653 reduced_cnt = lane_count >> 1;
1655 return drm_dp_clock_recovery_ok(link_status, reduced_cnt);
1658 static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl)
1660 u8 link_status[DP_LINK_STATUS_SIZE];
1661 int num_lanes = ctrl->link->link_params.num_lanes;
1663 dp_ctrl_read_link_status(ctrl, link_status);
1665 return drm_dp_channel_eq_ok(link_status, num_lanes);
1668 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1671 struct dp_ctrl_private *ctrl;
1673 int link_train_max_retries = 5;
1674 u32 const phy_cts_pixel_clk_khz = 148500;
1675 u8 link_status[DP_LINK_STATUS_SIZE];
1676 unsigned int training_step;
1681 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1683 rate = ctrl->panel->link_info.rate;
1685 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1687 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1688 DRM_DEBUG_DP("using phy test link parameters\n");
1689 if (!ctrl->panel->dp_mode.drm_mode.clock)
1690 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
1692 ctrl->link->link_params.rate = rate;
1693 ctrl->link->link_params.num_lanes =
1694 ctrl->panel->link_info.num_lanes;
1695 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1698 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1699 ctrl->link->link_params.rate,
1700 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1702 ctrl->link->phy_params.p_level = 0;
1703 ctrl->link->phy_params.v_level = 0;
1705 rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1709 while (--link_train_max_retries) {
1710 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1712 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
1717 training_step = DP_TRAINING_NONE;
1718 rc = dp_ctrl_setup_main_link(ctrl, &training_step);
1720 /* training completed successfully */
1722 } else if (training_step == DP_TRAINING_1) {
1723 /* link train_1 failed */
1724 if (!dp_catalog_link_is_connected(ctrl->catalog))
1727 dp_ctrl_read_link_status(ctrl, link_status);
1729 rc = dp_ctrl_link_rate_down_shift(ctrl);
1730 if (rc < 0) { /* already in RBR = 1.6G */
1731 if (dp_ctrl_clock_recovery_any_ok(link_status,
1732 ctrl->link->link_params.num_lanes)) {
1734 * some lanes are ready,
1735 * reduce lane number
1737 rc = dp_ctrl_link_lane_down_shift(ctrl);
1738 if (rc < 0) { /* lane == 1 already */
1739 /* end with failure */
1743 /* end with failure */
1744 break; /* lane == 1 already */
1747 } else if (training_step == DP_TRAINING_2) {
1748 /* link train_2 failed */
1749 if (!dp_catalog_link_is_connected(ctrl->catalog))
1752 dp_ctrl_read_link_status(ctrl, link_status);
1754 if (!drm_dp_clock_recovery_ok(link_status,
1755 ctrl->link->link_params.num_lanes))
1756 rc = dp_ctrl_link_rate_down_shift(ctrl);
1758 rc = dp_ctrl_link_lane_down_shift(ctrl);
1761 /* end with failure */
1762 break; /* lane == 1 already */
1765 /* stop link training before start re training */
1766 dp_ctrl_clear_training_pattern(ctrl);
1770 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1773 if (rc == 0) { /* link train successfully */
1775 * do not stop train pattern here
1776 * stop link training at on_stream
1777 * to pass compliance test
1781 * link training failed
1782 * end txing train pattern here
1784 dp_ctrl_clear_training_pattern(ctrl);
1786 dp_ctrl_deinitialize_mainlink(ctrl);
1793 static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl)
1795 int training_step = DP_TRAINING_NONE;
1797 return dp_ctrl_setup_main_link(ctrl, &training_step);
1800 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
1803 bool mainlink_ready = false;
1804 struct dp_ctrl_private *ctrl;
1809 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1811 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1813 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1814 ctrl->link->link_params.rate,
1815 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1817 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1818 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1820 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1825 if (!dp_ctrl_channel_eq_ok(ctrl))
1826 dp_ctrl_link_retrain(ctrl);
1828 /* stop txing train pattern to end link training */
1829 dp_ctrl_clear_training_pattern(ctrl);
1831 ret = dp_ctrl_enable_stream_clocks(ctrl);
1833 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1837 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1838 dp_ctrl_send_phy_test_pattern(ctrl);
1843 * Set up transfer unit values and set controller state to send
1846 reinit_completion(&ctrl->video_comp);
1848 dp_ctrl_configure_source_params(ctrl);
1850 dp_catalog_ctrl_config_msa(ctrl->catalog,
1851 ctrl->link->link_params.rate,
1852 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl));
1854 dp_ctrl_setup_tr_unit(ctrl);
1856 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1858 ret = dp_ctrl_wait4video_ready(ctrl);
1862 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1863 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1869 int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl)
1871 struct dp_ctrl_private *ctrl;
1872 struct dp_io *dp_io;
1876 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1877 dp_io = &ctrl->parser->io;
1880 /* set dongle to D3 (power off) mode */
1881 dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
1883 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1885 if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) {
1886 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1888 DRM_ERROR("Failed to disable pclk. ret=%d\n", ret);
1893 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1895 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1899 DRM_DEBUG_DP("Before, phy=%x init_count=%d power_on=%d\n",
1900 (u32)(uintptr_t)phy, phy->init_count, phy->power_count);
1904 /* aux channel down, reinit phy */
1908 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n",
1909 phy, phy->init_count, phy->power_count);
1913 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1915 struct dp_ctrl_private *ctrl;
1916 struct dp_io *dp_io;
1923 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1924 dp_io = &ctrl->parser->io;
1927 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1929 dp_catalog_ctrl_reset(ctrl->catalog);
1931 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1933 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
1935 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1937 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1941 DRM_DEBUG_DP("phy=%p init=%d power_on=%d\n",
1942 phy, phy->init_count, phy->power_count);
1947 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
1949 struct dp_ctrl_private *ctrl;
1955 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1957 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
1959 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
1960 DRM_DEBUG_DP("dp_video_ready\n");
1961 complete(&ctrl->video_comp);
1964 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
1965 DRM_DEBUG_DP("idle_patterns_sent\n");
1966 complete(&ctrl->idle_comp);
1970 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
1971 struct dp_panel *panel, struct drm_dp_aux *aux,
1972 struct dp_power *power, struct dp_catalog *catalog,
1973 struct dp_parser *parser)
1975 struct dp_ctrl_private *ctrl;
1978 if (!dev || !panel || !aux ||
1979 !link || !catalog) {
1980 DRM_ERROR("invalid input\n");
1981 return ERR_PTR(-EINVAL);
1984 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1986 DRM_ERROR("Mem allocation failure\n");
1987 return ERR_PTR(-ENOMEM);
1990 ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
1992 dev_err(dev, "invalid DP OPP table in device tree\n");
1993 /* caller do PTR_ERR(opp_table) */
1994 return (struct dp_ctrl *)ERR_PTR(ret);
1997 /* OPP table is optional */
1998 ret = devm_pm_opp_of_add_table(dev);
2000 dev_err(dev, "failed to add DP OPP table\n");
2002 init_completion(&ctrl->idle_comp);
2003 init_completion(&ctrl->video_comp);
2006 ctrl->parser = parser;
2007 ctrl->panel = panel;
2008 ctrl->power = power;
2011 ctrl->catalog = catalog;
2014 return &ctrl->dp_ctrl;