1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
6 #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__
8 #include <linux/types.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/phy/phy.h>
12 #include <linux/phy/phy-dp.h>
13 #include <linux/pm_opp.h>
14 #include <drm/drm_fixed.h>
15 #include <drm/drm_dp_helper.h>
16 #include <drm/drm_print.h>
22 #define DP_KHZ_TO_HZ 1000
23 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
24 #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
26 #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
27 #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
29 #define MR_LINK_TRAINING1 0x8
30 #define MR_LINK_SYMBOL_ERM 0x80
31 #define MR_LINK_PRBS7 0x100
32 #define MR_LINK_CUSTOM80 0x200
33 #define MR_LINK_TRAINING4 0x40
41 struct dp_tu_calc_input {
42 u64 lclk; /* 162, 270, 540 and 810 */
43 u64 pclk_khz; /* in KHz */
44 u64 hactive; /* active h-width */
45 u64 hporch; /* bp + fp + pulse */
46 int nlanes; /* no.of.lanes */
48 int pixel_enc; /* 444, 420, 422 */
49 int dsc_en; /* dsc on/off */
50 int async_en; /* async mode */
52 int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */
53 int num_of_dsc_slices; /* number of slices per line */
56 struct dp_vc_tu_mapping_table {
59 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
61 u8 valid_boundary_link;
63 bool boundary_moderation_en;
64 u8 valid_lower_boundary_link;
65 u8 upper_boundary_count;
66 u8 lower_boundary_count;
70 struct dp_ctrl_private {
71 struct dp_ctrl dp_ctrl;
73 struct drm_dp_aux *aux;
74 struct dp_panel *panel;
76 struct dp_power *power;
77 struct dp_parser *parser;
78 struct dp_catalog *catalog;
80 struct opp_table *opp_table;
82 struct completion idle_comp;
83 struct completion video_comp;
91 #define DP_LANE0_1_CR_DONE 0x11
93 static int dp_aux_link_configure(struct drm_dp_aux *aux,
94 struct dp_link_info *link)
99 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
100 values[1] = link->num_lanes;
102 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
103 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
105 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
112 void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl)
114 struct dp_ctrl_private *ctrl;
116 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
118 reinit_completion(&ctrl->idle_comp);
119 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE);
121 if (!wait_for_completion_timeout(&ctrl->idle_comp,
122 IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES))
123 pr_warn("PUSH_IDLE pattern timedout\n");
125 pr_debug("mainlink off done\n");
128 static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
131 u8 *dpcd = ctrl->panel->dpcd;
133 /* Default-> LSCLK DIV: 1/4 LCLK */
134 config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT);
136 /* Scrambler reset enable */
137 if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP)
138 config |= DP_CONFIGURATION_CTRL_ASSR;
140 tbd = dp_link_get_test_bits_depth(ctrl->link,
141 ctrl->panel->dp_mode.bpp);
143 if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN) {
144 pr_debug("BIT_DEPTH not set. Configure default\n");
145 tbd = DP_TEST_BIT_DEPTH_8;
148 config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT;
151 config |= ((ctrl->link->link_params.num_lanes - 1)
152 << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT);
154 if (drm_dp_enhanced_frame_cap(dpcd))
155 config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING;
157 config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */
159 /* sync clock & static Mvid */
160 config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
161 config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
163 dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
166 static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
170 dp_catalog_ctrl_lane_mapping(ctrl->catalog);
171 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
173 dp_ctrl_config_ctrl(ctrl);
175 tb = dp_link_get_test_bits_depth(ctrl->link,
176 ctrl->panel->dp_mode.bpp);
177 cc = dp_link_get_colorimetry_config(ctrl->link);
178 dp_catalog_ctrl_config_misc(ctrl->catalog, cc, tb);
179 dp_panel_timing_cfg(ctrl->panel);
183 * The structure and few functions present below are IP/Hardware
184 * specific implementation. Most of the implementation will not
185 * have coding comments
187 struct tu_algo_data {
192 s64 hbp_relative_to_pclk;
193 s64 hbp_relative_to_pclk_fp;
201 uint delay_start_link_extra_pixclk;
202 int extra_buffer_margin;
204 s64 original_ratio_fp;
213 int valid_boundary_link;
214 s64 resulting_valid_fp;
216 s64 effective_valid_fp;
217 s64 effective_valid_recorded_fp;
222 int remainder_tus_upper;
223 int remainder_tus_lower;
226 int delay_start_link;
228 int extra_pclk_cycles;
229 int extra_pclk_cycles_in_link_clk;
231 s64 average_valid2_fp;
232 int new_valid_boundary_link;
233 int remainder_symbols_exist;
235 s64 n_remainder_symbols_per_lane_fp;
236 s64 last_partial_tu_fp;
239 int n_tus_incl_last_incomplete_tu;
240 int extra_pclk_cycles_tmp;
241 int extra_pclk_cycles_in_link_clk_tmp;
242 int extra_required_bytes_new_tmp;
244 int lower_filler_size_tmp;
245 int delay_start_link_tmp;
247 bool boundary_moderation_en;
248 int boundary_mod_lower_err;
249 int upper_boundary_count;
250 int lower_boundary_count;
251 int i_upper_boundary_count;
252 int i_lower_boundary_count;
253 int valid_lower_boundary_link;
254 int even_distribution_BF;
255 int even_distribution_legacy;
256 int even_distribution;
257 int min_hblank_violated;
258 s64 delay_start_time_fp;
266 static int _tu_param_compare(s64 a, s64 b)
270 s64 a_temp, b_temp, minus_1;
275 minus_1 = drm_fixp_from_fraction(-1, 1);
277 a_sign = (a >> 32) & 0x80000000 ? 1 : 0;
279 b_sign = (b >> 32) & 0x80000000 ? 1 : 0;
283 else if (b_sign > a_sign)
286 if (!a_sign && !b_sign) { /* positive */
291 } else { /* negative */
292 a_temp = drm_fixp_mul(a, minus_1);
293 b_temp = drm_fixp_mul(b, minus_1);
302 static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
303 struct tu_algo_data *tu)
305 int nlanes = in->nlanes;
306 int dsc_num_slices = in->num_of_dsc_slices;
307 int dsc_num_bytes = 0;
313 int tot_num_eoc_symbols = 0;
314 int tot_num_hor_bytes = 0;
315 int tot_num_dummy_bytes = 0;
316 int dwidth_dsc_bytes = 0;
319 s64 temp1_fp, temp2_fp, temp3_fp;
321 tu->lclk_fp = drm_fixp_from_fraction(in->lclk, 1);
322 tu->pclk_fp = drm_fixp_from_fraction(in->pclk_khz, 1000);
323 tu->lwidth = in->hactive;
324 tu->hbp_relative_to_pclk = in->hporch;
325 tu->nlanes = in->nlanes;
327 tu->pixelEnc = in->pixel_enc;
328 tu->dsc_en = in->dsc_en;
329 tu->async_en = in->async_en;
330 tu->lwidth_fp = drm_fixp_from_fraction(in->hactive, 1);
331 tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(in->hporch, 1);
333 if (tu->pixelEnc == 420) {
334 temp1_fp = drm_fixp_from_fraction(2, 1);
335 tu->pclk_fp = drm_fixp_div(tu->pclk_fp, temp1_fp);
336 tu->lwidth_fp = drm_fixp_div(tu->lwidth_fp, temp1_fp);
337 tu->hbp_relative_to_pclk_fp =
338 drm_fixp_div(tu->hbp_relative_to_pclk_fp, 2);
341 if (tu->pixelEnc == 422) {
363 temp1_fp = drm_fixp_from_fraction(in->compress_ratio, 100);
364 temp2_fp = drm_fixp_from_fraction(in->bpp, 1);
365 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
366 temp2_fp = drm_fixp_mul(tu->lwidth_fp, temp3_fp);
368 temp1_fp = drm_fixp_from_fraction(8, 1);
369 temp3_fp = drm_fixp_div(temp2_fp, temp1_fp);
371 numerator = drm_fixp2int(temp3_fp);
373 dsc_num_bytes = numerator / dsc_num_slices;
374 eoc_bytes = dsc_num_bytes % nlanes;
375 tot_num_eoc_symbols = nlanes * dsc_num_slices;
376 tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices;
377 tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
379 if (dsc_num_bytes == 0)
380 pr_info("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
382 dwidth_dsc_bytes = (tot_num_hor_bytes +
383 tot_num_eoc_symbols +
384 (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes));
386 dwidth_dsc_fp = drm_fixp_from_fraction(dwidth_dsc_bytes, 3);
388 temp2_fp = drm_fixp_mul(tu->pclk_fp, dwidth_dsc_fp);
389 temp1_fp = drm_fixp_div(temp2_fp, tu->lwidth_fp);
390 pclk_dsc_fp = temp1_fp;
392 temp1_fp = drm_fixp_div(pclk_dsc_fp, tu->pclk_fp);
393 temp2_fp = drm_fixp_mul(tu->hbp_relative_to_pclk_fp, temp1_fp);
394 hbp_dsc_fp = temp2_fp;
397 tu->pclk_fp = pclk_dsc_fp;
398 tu->lwidth_fp = dwidth_dsc_fp;
399 tu->hbp_relative_to_pclk_fp = hbp_dsc_fp;
403 temp1_fp = drm_fixp_from_fraction(976, 1000); /* 0.976 */
404 tu->lclk_fp = drm_fixp_mul(tu->lclk_fp, temp1_fp);
408 static void _tu_valid_boundary_calc(struct tu_algo_data *tu)
410 s64 temp1_fp, temp2_fp, temp, temp1, temp2;
411 int compare_result_1, compare_result_2, compare_result_3;
413 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
414 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
416 tu->new_valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
418 temp = (tu->i_upper_boundary_count *
419 tu->new_valid_boundary_link +
420 tu->i_lower_boundary_count *
421 (tu->new_valid_boundary_link-1));
422 tu->average_valid2_fp = drm_fixp_from_fraction(temp,
423 (tu->i_upper_boundary_count +
424 tu->i_lower_boundary_count));
426 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
427 temp2_fp = tu->lwidth_fp;
428 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
429 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
430 tu->n_tus = drm_fixp2int(temp2_fp);
431 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
434 temp1_fp = drm_fixp_from_fraction(tu->n_tus, 1);
435 temp2_fp = drm_fixp_mul(temp1_fp, tu->average_valid2_fp);
436 temp1_fp = drm_fixp_from_fraction(tu->n_symbols, 1);
437 temp2_fp = temp1_fp - temp2_fp;
438 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
439 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
440 tu->n_remainder_symbols_per_lane_fp = temp2_fp;
442 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
443 tu->last_partial_tu_fp =
444 drm_fixp_div(tu->n_remainder_symbols_per_lane_fp,
447 if (tu->n_remainder_symbols_per_lane_fp != 0)
448 tu->remainder_symbols_exist = 1;
450 tu->remainder_symbols_exist = 0;
452 temp1_fp = drm_fixp_from_fraction(tu->n_tus, tu->nlanes);
453 tu->n_tus_per_lane = drm_fixp2int(temp1_fp);
455 tu->paired_tus = (int)((tu->n_tus_per_lane) /
456 (tu->i_upper_boundary_count +
457 tu->i_lower_boundary_count));
459 tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus *
460 (tu->i_upper_boundary_count +
461 tu->i_lower_boundary_count);
463 if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) {
464 tu->remainder_tus_upper = tu->i_upper_boundary_count;
465 tu->remainder_tus_lower = tu->remainder_tus -
466 tu->i_upper_boundary_count;
468 tu->remainder_tus_upper = tu->remainder_tus;
469 tu->remainder_tus_lower = 0;
472 temp = tu->paired_tus * (tu->i_upper_boundary_count *
473 tu->new_valid_boundary_link +
474 tu->i_lower_boundary_count *
475 (tu->new_valid_boundary_link - 1)) +
476 (tu->remainder_tus_upper *
477 tu->new_valid_boundary_link) +
478 (tu->remainder_tus_lower *
479 (tu->new_valid_boundary_link - 1));
480 tu->total_valid_fp = drm_fixp_from_fraction(temp, 1);
482 if (tu->remainder_symbols_exist) {
483 temp1_fp = tu->total_valid_fp +
484 tu->n_remainder_symbols_per_lane_fp;
485 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
486 temp2_fp = temp2_fp + tu->last_partial_tu_fp;
487 temp1_fp = drm_fixp_div(temp1_fp, temp2_fp);
489 temp2_fp = drm_fixp_from_fraction(tu->n_tus_per_lane, 1);
490 temp1_fp = drm_fixp_div(tu->total_valid_fp, temp2_fp);
492 tu->effective_valid_fp = temp1_fp;
494 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
495 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
496 tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp;
498 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
499 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
500 tu->n_err_fp = tu->average_valid2_fp - temp2_fp;
502 tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
504 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
505 temp2_fp = tu->lwidth_fp;
506 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
507 temp2_fp = drm_fixp_div(temp1_fp, tu->average_valid2_fp);
510 tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(temp2_fp);
512 tu->n_tus_incl_last_incomplete_tu = 0;
515 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
516 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
517 temp1_fp = tu->average_valid2_fp - temp2_fp;
518 temp2_fp = drm_fixp_from_fraction(tu->n_tus_incl_last_incomplete_tu, 1);
519 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
522 temp1 = drm_fixp2int_ceil(temp1_fp);
524 temp = tu->i_upper_boundary_count * tu->nlanes;
525 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
526 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
527 temp1_fp = drm_fixp_from_fraction(tu->new_valid_boundary_link, 1);
528 temp2_fp = temp1_fp - temp2_fp;
529 temp1_fp = drm_fixp_from_fraction(temp, 1);
530 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
533 temp2 = drm_fixp2int_ceil(temp2_fp);
536 tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2);
538 temp1_fp = drm_fixp_from_fraction(8, tu->bpp);
539 temp2_fp = drm_fixp_from_fraction(
540 tu->extra_required_bytes_new_tmp, 1);
541 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
544 tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(temp1_fp);
546 tu->extra_pclk_cycles_tmp = 0;
548 temp1_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles_tmp, 1);
549 temp2_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
550 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
553 tu->extra_pclk_cycles_in_link_clk_tmp =
554 drm_fixp2int_ceil(temp1_fp);
556 tu->extra_pclk_cycles_in_link_clk_tmp = 0;
558 tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link;
560 tu->lower_filler_size_tmp = tu->filler_size_tmp + 1;
562 tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp +
563 tu->lower_filler_size_tmp +
564 tu->extra_buffer_margin;
566 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link_tmp, 1);
567 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
569 compare_result_1 = _tu_param_compare(tu->n_n_err_fp, tu->diff_abs_fp);
570 if (compare_result_1 == 2)
571 compare_result_1 = 1;
573 compare_result_1 = 0;
575 compare_result_2 = _tu_param_compare(tu->n_n_err_fp, tu->err_fp);
576 if (compare_result_2 == 2)
577 compare_result_2 = 1;
579 compare_result_2 = 0;
581 compare_result_3 = _tu_param_compare(tu->hbp_time_fp,
582 tu->delay_start_time_fp);
583 if (compare_result_3 == 2)
584 compare_result_3 = 0;
586 compare_result_3 = 1;
588 if (((tu->even_distribution == 1) ||
589 ((tu->even_distribution_BF == 0) &&
590 (tu->even_distribution_legacy == 0))) &&
591 tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 &&
593 (compare_result_1 || (tu->min_hblank_violated == 1)) &&
594 (tu->new_valid_boundary_link - 1) > 0 &&
596 (tu->delay_start_link_tmp <= 1023)) {
597 tu->upper_boundary_count = tu->i_upper_boundary_count;
598 tu->lower_boundary_count = tu->i_lower_boundary_count;
599 tu->err_fp = tu->n_n_err_fp;
600 tu->boundary_moderation_en = true;
601 tu->tu_size_desired = tu->tu_size;
602 tu->valid_boundary_link = tu->new_valid_boundary_link;
603 tu->effective_valid_recorded_fp = tu->effective_valid_fp;
604 tu->even_distribution_BF = 1;
605 tu->delay_start_link = tu->delay_start_link_tmp;
606 } else if (tu->boundary_mod_lower_err == 0) {
607 compare_result_1 = _tu_param_compare(tu->n_n_err_fp,
609 if (compare_result_1 == 2)
610 tu->boundary_mod_lower_err = 1;
614 static void _dp_ctrl_calc_tu(struct dp_tu_calc_input *in,
615 struct dp_vc_tu_mapping_table *tu_table)
617 struct tu_algo_data *tu;
618 int compare_result_1, compare_result_2;
620 s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0;
622 s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(6, 10000); /* 0.0006 */
623 s64 const_p49_fp = drm_fixp_from_fraction(49, 100); /* 0.49 */
624 s64 const_p56_fp = drm_fixp_from_fraction(56, 100); /* 0.56 */
625 s64 RATIO_SCALE_fp = drm_fixp_from_fraction(1001, 1000);
627 u8 DP_BRUTE_FORCE = 1;
628 s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(1, 10); /* 0.1 */
629 uint EXTRA_PIXCLK_CYCLE_DELAY = 4;
630 uint HBLANK_MARGIN = 4;
632 tu = kzalloc(sizeof(*tu), GFP_KERNEL);
636 dp_panel_update_tu_timings(in, tu);
638 tu->err_fp = drm_fixp_from_fraction(1000, 1); /* 1000 */
640 temp1_fp = drm_fixp_from_fraction(4, 1);
641 temp2_fp = drm_fixp_mul(temp1_fp, tu->lclk_fp);
642 temp_fp = drm_fixp_div(temp2_fp, tu->pclk_fp);
643 tu->extra_buffer_margin = drm_fixp2int_ceil(temp_fp);
645 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
646 temp2_fp = drm_fixp_mul(tu->pclk_fp, temp1_fp);
647 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
648 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
649 tu->ratio_fp = drm_fixp_div(temp2_fp, tu->lclk_fp);
651 tu->original_ratio_fp = tu->ratio_fp;
652 tu->boundary_moderation_en = false;
653 tu->upper_boundary_count = 0;
654 tu->lower_boundary_count = 0;
655 tu->i_upper_boundary_count = 0;
656 tu->i_lower_boundary_count = 0;
657 tu->valid_lower_boundary_link = 0;
658 tu->even_distribution_BF = 0;
659 tu->even_distribution_legacy = 0;
660 tu->even_distribution = 0;
661 tu->delay_start_time_fp = 0;
663 tu->err_fp = drm_fixp_from_fraction(1000, 1);
667 tu->ratio = drm_fixp2int(tu->ratio_fp);
668 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
669 div64_u64_rem(tu->lwidth_fp, temp1_fp, &temp2_fp);
671 !tu->ratio && tu->dsc_en == 0) {
672 tu->ratio_fp = drm_fixp_mul(tu->ratio_fp, RATIO_SCALE_fp);
673 tu->ratio = drm_fixp2int(tu->ratio_fp);
675 tu->ratio_fp = drm_fixp_from_fraction(1, 1);
684 compare_result_1 = _tu_param_compare(tu->ratio_fp, const_p49_fp);
685 if (!compare_result_1 || compare_result_1 == 1)
686 compare_result_1 = 1;
688 compare_result_1 = 0;
690 compare_result_2 = _tu_param_compare(tu->ratio_fp, const_p56_fp);
691 if (!compare_result_2 || compare_result_2 == 2)
692 compare_result_2 = 1;
694 compare_result_2 = 0;
696 if (tu->dsc_en && compare_result_1 && compare_result_2) {
698 DRM_DEBUG_DP("Info: increase HBLANK_MARGIN to %d\n",
703 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
704 temp1_fp = drm_fixp_from_fraction(tu->tu_size, 1);
705 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
706 temp = drm_fixp2int_ceil(temp2_fp);
707 temp1_fp = drm_fixp_from_fraction(temp, 1);
708 tu->n_err_fp = temp1_fp - temp2_fp;
710 if (tu->n_err_fp < tu->err_fp) {
711 tu->err_fp = tu->n_err_fp;
712 tu->tu_size_desired = tu->tu_size;
716 tu->tu_size_minus1 = tu->tu_size_desired - 1;
718 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
719 temp2_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
720 tu->valid_boundary_link = drm_fixp2int_ceil(temp2_fp);
722 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
723 temp2_fp = tu->lwidth_fp;
724 temp2_fp = drm_fixp_mul(temp2_fp, temp1_fp);
726 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
727 temp2_fp = drm_fixp_div(temp2_fp, temp1_fp);
728 tu->n_tus = drm_fixp2int(temp2_fp);
729 if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000)
732 tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0;
733 DRM_DEBUG_DP("Info: n_sym = %d, num_of_tus = %d\n",
734 tu->valid_boundary_link, tu->n_tus);
736 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
737 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
738 temp1_fp = drm_fixp_from_fraction(tu->valid_boundary_link, 1);
739 temp2_fp = temp1_fp - temp2_fp;
740 temp1_fp = drm_fixp_from_fraction(tu->n_tus + 1, 1);
741 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
743 temp = drm_fixp2int(temp2_fp);
744 if (temp && temp2_fp)
745 tu->extra_bytes = drm_fixp2int_ceil(temp2_fp);
749 temp1_fp = drm_fixp_from_fraction(tu->extra_bytes, 1);
750 temp2_fp = drm_fixp_from_fraction(8, tu->bpp);
751 temp1_fp = drm_fixp_mul(temp1_fp, temp2_fp);
753 if (temp && temp1_fp)
754 tu->extra_pclk_cycles = drm_fixp2int_ceil(temp1_fp);
756 tu->extra_pclk_cycles = drm_fixp2int(temp1_fp);
758 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
759 temp2_fp = drm_fixp_from_fraction(tu->extra_pclk_cycles, 1);
760 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
763 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(temp1_fp);
765 tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(temp1_fp);
767 tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link;
769 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
770 tu->ratio_by_tu_fp = drm_fixp_mul(tu->ratio_fp, temp1_fp);
772 tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk +
773 tu->filler_size + tu->extra_buffer_margin;
775 tu->resulting_valid_fp =
776 drm_fixp_from_fraction(tu->valid_boundary_link, 1);
778 temp1_fp = drm_fixp_from_fraction(tu->tu_size_desired, 1);
779 temp2_fp = drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
780 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
782 temp1_fp = drm_fixp_from_fraction(HBLANK_MARGIN, 1);
783 temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp;
784 tu->hbp_time_fp = drm_fixp_div(temp1_fp, tu->pclk_fp);
786 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
787 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
789 compare_result_1 = _tu_param_compare(tu->hbp_time_fp,
790 tu->delay_start_time_fp);
791 if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */
792 tu->min_hblank_violated = 1;
794 tu->hactive_time_fp = drm_fixp_div(tu->lwidth_fp, tu->pclk_fp);
796 compare_result_2 = _tu_param_compare(tu->hactive_time_fp,
797 tu->delay_start_time_fp);
798 if (compare_result_2 == 2)
799 tu->min_hblank_violated = 1;
801 tu->delay_start_time_fp = 0;
805 tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY;
806 tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp;
808 temp = drm_fixp2int(tu->diff_abs_fp);
809 if (!temp && tu->diff_abs_fp <= 0xffff)
812 /* if(diff_abs < 0) diff_abs *= -1 */
813 if (tu->diff_abs_fp < 0)
814 tu->diff_abs_fp = drm_fixp_mul(tu->diff_abs_fp, -1);
816 tu->boundary_mod_lower_err = 0;
817 if ((tu->diff_abs_fp != 0 &&
818 ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) ||
819 (tu->even_distribution_legacy == 0) ||
820 (DP_BRUTE_FORCE == 1))) ||
821 (tu->min_hblank_violated == 1)) {
823 tu->err_fp = drm_fixp_from_fraction(1000, 1);
825 temp1_fp = drm_fixp_div(tu->lclk_fp, tu->pclk_fp);
826 temp2_fp = drm_fixp_from_fraction(
827 tu->delay_start_link_extra_pixclk, 1);
828 temp1_fp = drm_fixp_mul(temp2_fp, temp1_fp);
831 tu->extra_buffer_margin =
832 drm_fixp2int_ceil(temp1_fp);
834 tu->extra_buffer_margin = 0;
836 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
837 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
840 tu->n_symbols = drm_fixp2int_ceil(temp1_fp);
844 for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) {
845 for (tu->i_upper_boundary_count = 1;
846 tu->i_upper_boundary_count <= 15;
847 tu->i_upper_boundary_count++) {
848 for (tu->i_lower_boundary_count = 1;
849 tu->i_lower_boundary_count <= 15;
850 tu->i_lower_boundary_count++) {
851 _tu_valid_boundary_calc(tu);
855 tu->delay_start_link_extra_pixclk--;
856 } while (tu->boundary_moderation_en != true &&
857 tu->boundary_mod_lower_err == 1 &&
858 tu->delay_start_link_extra_pixclk != 0);
860 if (tu->boundary_moderation_en == true) {
861 temp1_fp = drm_fixp_from_fraction(
862 (tu->upper_boundary_count *
863 tu->valid_boundary_link +
864 tu->lower_boundary_count *
865 (tu->valid_boundary_link - 1)), 1);
866 temp2_fp = drm_fixp_from_fraction(
867 (tu->upper_boundary_count +
868 tu->lower_boundary_count), 1);
869 tu->resulting_valid_fp =
870 drm_fixp_div(temp1_fp, temp2_fp);
872 temp1_fp = drm_fixp_from_fraction(
873 tu->tu_size_desired, 1);
875 drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
877 tu->valid_lower_boundary_link =
878 tu->valid_boundary_link - 1;
880 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
881 temp1_fp = drm_fixp_mul(tu->lwidth_fp, temp1_fp);
882 temp2_fp = drm_fixp_div(temp1_fp,
883 tu->resulting_valid_fp);
884 tu->n_tus = drm_fixp2int(temp2_fp);
886 tu->tu_size_minus1 = tu->tu_size_desired - 1;
887 tu->even_distribution_BF = 1;
890 drm_fixp_from_fraction(tu->tu_size_desired, 1);
892 drm_fixp_div(tu->resulting_valid_fp, temp1_fp);
893 tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp;
897 temp2_fp = drm_fixp_mul(LCLK_FAST_SKEW_fp, tu->lwidth_fp);
900 temp = drm_fixp2int_ceil(temp2_fp);
904 temp1_fp = drm_fixp_from_fraction(tu->nlanes, 1);
905 temp2_fp = drm_fixp_mul(tu->original_ratio_fp, temp1_fp);
906 temp1_fp = drm_fixp_from_fraction(tu->bpp, 8);
907 temp2_fp = drm_fixp_div(temp1_fp, temp2_fp);
908 temp1_fp = drm_fixp_from_fraction(temp, 1);
909 temp2_fp = drm_fixp_mul(temp1_fp, temp2_fp);
910 temp = drm_fixp2int(temp2_fp);
913 tu->delay_start_link += (int)temp;
915 temp1_fp = drm_fixp_from_fraction(tu->delay_start_link, 1);
916 tu->delay_start_time_fp = drm_fixp_div(temp1_fp, tu->lclk_fp);
919 tu_table->valid_boundary_link = tu->valid_boundary_link;
920 tu_table->delay_start_link = tu->delay_start_link;
921 tu_table->boundary_moderation_en = tu->boundary_moderation_en;
922 tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link;
923 tu_table->upper_boundary_count = tu->upper_boundary_count;
924 tu_table->lower_boundary_count = tu->lower_boundary_count;
925 tu_table->tu_size_minus1 = tu->tu_size_minus1;
927 DRM_DEBUG_DP("TU: valid_boundary_link: %d\n",
928 tu_table->valid_boundary_link);
929 DRM_DEBUG_DP("TU: delay_start_link: %d\n",
930 tu_table->delay_start_link);
931 DRM_DEBUG_DP("TU: boundary_moderation_en: %d\n",
932 tu_table->boundary_moderation_en);
933 DRM_DEBUG_DP("TU: valid_lower_boundary_link: %d\n",
934 tu_table->valid_lower_boundary_link);
935 DRM_DEBUG_DP("TU: upper_boundary_count: %d\n",
936 tu_table->upper_boundary_count);
937 DRM_DEBUG_DP("TU: lower_boundary_count: %d\n",
938 tu_table->lower_boundary_count);
939 DRM_DEBUG_DP("TU: tu_size_minus1: %d\n", tu_table->tu_size_minus1);
944 static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl,
945 struct dp_vc_tu_mapping_table *tu_table)
947 struct dp_tu_calc_input in;
948 struct drm_display_mode *drm_mode;
950 drm_mode = &ctrl->panel->dp_mode.drm_mode;
952 in.lclk = ctrl->link->link_params.rate / 1000;
953 in.pclk_khz = drm_mode->clock;
954 in.hactive = drm_mode->hdisplay;
955 in.hporch = drm_mode->htotal - drm_mode->hdisplay;
956 in.nlanes = ctrl->link->link_params.num_lanes;
957 in.bpp = ctrl->panel->dp_mode.bpp;
962 in.num_of_dsc_slices = 0;
963 in.compress_ratio = 100;
965 _dp_ctrl_calc_tu(&in, tu_table);
968 static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl)
971 u32 valid_boundary = 0x0;
972 u32 valid_boundary2 = 0x0;
973 struct dp_vc_tu_mapping_table tu_calc_table;
975 dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
977 dp_tu |= tu_calc_table.tu_size_minus1;
978 valid_boundary |= tu_calc_table.valid_boundary_link;
979 valid_boundary |= (tu_calc_table.delay_start_link << 16);
981 valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1);
982 valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16);
983 valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20);
985 if (tu_calc_table.boundary_moderation_en)
986 valid_boundary2 |= BIT(0);
988 pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n",
989 dp_tu, valid_boundary, valid_boundary2);
991 dp_catalog_ctrl_update_transfer_unit(ctrl->catalog,
992 dp_tu, valid_boundary, valid_boundary2);
995 static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
999 if (!wait_for_completion_timeout(&ctrl->video_comp,
1000 WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) {
1001 DRM_ERROR("wait4video timedout\n");
1007 static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1009 struct dp_link *link = ctrl->link;
1010 int ret = 0, lane, lane_cnt;
1012 u32 max_level_reached = 0;
1013 u32 voltage_swing_level = link->phy_params.v_level;
1014 u32 pre_emphasis_level = link->phy_params.p_level;
1016 ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1017 voltage_swing_level, pre_emphasis_level);
1022 if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
1023 DRM_DEBUG_DP("max. voltage swing level reached %d\n",
1024 voltage_swing_level);
1025 max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
1028 if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
1029 DRM_DEBUG_DP("max. pre-emphasis level reached %d\n",
1030 pre_emphasis_level);
1031 max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1034 pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
1036 lane_cnt = ctrl->link->link_params.num_lanes;
1037 for (lane = 0; lane < lane_cnt; lane++)
1038 buf[lane] = voltage_swing_level | pre_emphasis_level
1039 | max_level_reached;
1041 DRM_DEBUG_DP("sink: p|v=0x%x\n", voltage_swing_level
1042 | pre_emphasis_level);
1043 ret = drm_dp_dpcd_write(ctrl->aux, DP_TRAINING_LANE0_SET,
1045 if (ret == lane_cnt)
1051 static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl,
1057 DRM_DEBUG_DP("sink: pattern=%x\n", pattern);
1061 if (pattern && pattern != DP_TRAINING_PATTERN_4)
1062 buf |= DP_LINK_SCRAMBLING_DISABLE;
1064 ret = drm_dp_dpcd_writeb(ctrl->aux, DP_TRAINING_PATTERN_SET, buf);
1068 static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
1073 len = drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
1074 if (len != DP_LINK_STATUS_SIZE) {
1075 DRM_ERROR("DP link status read failed, err: %d\n", len);
1082 static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
1083 struct dp_cr_status *cr, int *training_step)
1085 int tries, old_v_level, ret = 0;
1086 u8 link_status[DP_LINK_STATUS_SIZE];
1087 int const maximum_retries = 4;
1089 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1091 *training_step = DP_TRAINING_1;
1093 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1);
1096 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1097 DP_LINK_SCRAMBLING_DISABLE);
1099 ret = dp_ctrl_update_vx_px(ctrl);
1104 old_v_level = ctrl->link->phy_params.v_level;
1105 for (tries = 0; tries < maximum_retries; tries++) {
1106 drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd);
1108 ret = dp_ctrl_read_link_status(ctrl, link_status);
1112 cr->lane_0_1 = link_status[0];
1113 cr->lane_2_3 = link_status[1];
1115 if (drm_dp_clock_recovery_ok(link_status,
1116 ctrl->link->link_params.num_lanes)) {
1120 if (ctrl->link->phy_params.v_level >=
1121 DP_TRAIN_VOLTAGE_SWING_MAX) {
1122 DRM_ERROR_RATELIMITED("max v_level reached\n");
1126 if (old_v_level != ctrl->link->phy_params.v_level) {
1128 old_v_level = ctrl->link->phy_params.v_level;
1131 DRM_DEBUG_DP("clock recovery not done, adjusting vx px\n");
1133 dp_link_adjust_levels(ctrl->link, link_status);
1134 ret = dp_ctrl_update_vx_px(ctrl);
1139 DRM_ERROR("max tries reached\n");
1143 static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
1147 switch (ctrl->link->link_params.rate) {
1149 ctrl->link->link_params.rate = 540000;
1152 ctrl->link->link_params.rate = 270000;
1155 ctrl->link->link_params.rate = 162000;
1164 DRM_DEBUG_DP("new rate=0x%x\n", ctrl->link->link_params.rate);
1169 static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl)
1172 if (ctrl->link->link_params.num_lanes == 1)
1175 ctrl->link->link_params.num_lanes /= 2;
1176 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1178 ctrl->link->phy_params.p_level = 0;
1179 ctrl->link->phy_params.v_level = 0;
1184 static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
1186 dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE);
1187 drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
1190 static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,
1191 struct dp_cr_status *cr, int *training_step)
1193 int tries = 0, ret = 0;
1195 int const maximum_retries = 5;
1196 u8 link_status[DP_LINK_STATUS_SIZE];
1198 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1200 *training_step = DP_TRAINING_2;
1202 if (drm_dp_tps3_supported(ctrl->panel->dpcd))
1203 pattern = DP_TRAINING_PATTERN_3;
1205 pattern = DP_TRAINING_PATTERN_2;
1207 ret = dp_ctrl_update_vx_px(ctrl);
1211 ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern);
1215 dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN);
1217 for (tries = 0; tries <= maximum_retries; tries++) {
1218 drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
1220 ret = dp_ctrl_read_link_status(ctrl, link_status);
1223 cr->lane_0_1 = link_status[0];
1224 cr->lane_2_3 = link_status[1];
1226 if (drm_dp_channel_eq_ok(link_status,
1227 ctrl->link->link_params.num_lanes)) {
1231 dp_link_adjust_levels(ctrl->link, link_status);
1232 ret = dp_ctrl_update_vx_px(ctrl);
1241 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);
1243 static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
1244 struct dp_cr_status *cr, int *training_step)
1247 u8 encoding = DP_SET_ANSI_8B10B;
1248 struct dp_link_info link_info = {0};
1250 dp_ctrl_config_ctrl(ctrl);
1252 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1253 link_info.rate = ctrl->link->link_params.rate;
1254 link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING;
1256 dp_aux_link_configure(ctrl->aux, &link_info);
1257 drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
1260 ret = dp_ctrl_link_train_1(ctrl, cr, training_step);
1262 DRM_ERROR("link training #1 failed. ret=%d\n", ret);
1266 /* print success info as this is a result of user initiated action */
1267 DRM_DEBUG_DP("link training #1 successful\n");
1269 ret = dp_ctrl_link_train_2(ctrl, cr, training_step);
1271 DRM_ERROR("link training #2 failed. ret=%d\n", ret);
1275 /* print success info as this is a result of user initiated action */
1276 DRM_DEBUG_DP("link training #2 successful\n");
1279 dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
1284 static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
1285 struct dp_cr_status *cr, int *training_step)
1289 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
1291 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1295 * As part of previous calls, DP controller state might have
1296 * transitioned to PUSH_IDLE. In order to start transmitting
1297 * a link training pattern, we have to first do soft reset.
1300 ret = dp_ctrl_link_train(ctrl, cr, training_step);
1305 static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
1306 enum dp_pm_type module, char *name, unsigned long rate)
1308 u32 num = ctrl->parser->mp[module].num_clk;
1309 struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
1311 while (num && strcmp(cfg->clk_name, name)) {
1316 DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
1321 DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
1325 static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1328 struct dp_io *dp_io = &ctrl->parser->io;
1329 struct phy *phy = dp_io->phy;
1330 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1332 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1333 opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1334 dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
1335 ctrl->link->link_params.rate * 1000);
1337 phy_configure(phy, &dp_io->phy_opts);
1340 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
1342 DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
1344 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1345 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1350 static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
1354 dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
1355 ctrl->dp_ctrl.pixel_rate * 1000);
1357 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
1359 DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
1361 DRM_DEBUG_DP("link rate=%d pixel_clk=%d\n",
1362 ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
1367 int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
1369 struct dp_ctrl_private *ctrl;
1370 struct dp_io *dp_io;
1374 DRM_ERROR("Invalid input data\n");
1378 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1379 dp_io = &ctrl->parser->io;
1382 ctrl->dp_ctrl.orientation = flip;
1385 dp_catalog_ctrl_reset(ctrl->catalog);
1387 dp_catalog_ctrl_phy_reset(ctrl->catalog);
1389 dp_catalog_ctrl_enable_irq(ctrl->catalog, true);
1395 * dp_ctrl_host_deinit() - Uninitialize DP controller
1396 * @dp_ctrl: Display Port Driver data
1398 * Perform required steps to uninitialize DP controller
1399 * and its resources.
1401 void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
1403 struct dp_ctrl_private *ctrl;
1404 struct dp_io *dp_io;
1408 DRM_ERROR("Invalid input data\n");
1412 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1413 dp_io = &ctrl->parser->io;
1416 dp_catalog_ctrl_enable_irq(ctrl->catalog, false);
1419 DRM_DEBUG_DP("Host deinitialized successfully\n");
1422 static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
1424 u8 *dpcd = ctrl->panel->dpcd;
1427 * For better interop experience, used a fixed NVID=0x8000
1428 * whenever connected to a VGA dongle downstream.
1430 if (drm_dp_is_branch(dpcd))
1431 return (drm_dp_has_quirk(&ctrl->panel->desc,
1432 DP_DPCD_QUIRK_CONSTANT_N));
1437 static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1440 struct dp_io *dp_io = &ctrl->parser->io;
1441 struct phy *phy = dp_io->phy;
1442 struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1444 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1445 opts_dp->lanes = ctrl->link->link_params.num_lanes;
1446 phy_configure(phy, &dp_io->phy_opts);
1448 * Disable and re-enable the mainlink clock since the
1449 * link clock might have been adjusted as part of the
1452 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1454 DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
1458 /* hw recommended delay before re-enabling clocks */
1461 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1463 DRM_ERROR("Failed to enable mainlink clks. ret=%d\n", ret);
1470 static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl)
1472 struct dp_io *dp_io;
1476 dp_io = &ctrl->parser->io;
1479 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1481 dp_catalog_ctrl_reset(ctrl->catalog);
1483 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1485 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1494 static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
1497 struct dp_cr_status cr;
1498 int training_step = DP_TRAINING_NONE;
1500 dp_ctrl_push_idle(&ctrl->dp_ctrl);
1502 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1504 ret = dp_ctrl_setup_main_link(ctrl, &cr, &training_step);
1508 dp_ctrl_clear_training_pattern(ctrl);
1510 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1512 ret = dp_ctrl_wait4video_ready(ctrl);
1517 static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl)
1521 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
1522 DRM_DEBUG_DP("no test pattern selected by sink\n");
1527 * The global reset will need DP link related clocks to be
1528 * running. Add the global reset just before disabling the
1529 * link clocks and core clocks.
1531 ret = dp_ctrl_off(&ctrl->dp_ctrl);
1533 DRM_ERROR("failed to disable DP controller\n");
1537 ret = dp_ctrl_on_link(&ctrl->dp_ctrl);
1539 ret = dp_ctrl_on_stream(&ctrl->dp_ctrl);
1541 DRM_ERROR("failed to enable DP link controller\n");
1546 static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
1548 bool success = false;
1549 u32 pattern_sent = 0x0;
1550 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
1552 DRM_DEBUG_DP("request: 0x%x\n", pattern_requested);
1554 if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1555 ctrl->link->phy_params.v_level,
1556 ctrl->link->phy_params.p_level)) {
1557 DRM_ERROR("Failed to set v/p levels\n");
1560 dp_catalog_ctrl_send_phy_pattern(ctrl->catalog, pattern_requested);
1561 dp_ctrl_update_vx_px(ctrl);
1562 dp_link_send_test_response(ctrl->link);
1564 pattern_sent = dp_catalog_ctrl_read_phy_pattern(ctrl->catalog);
1566 switch (pattern_sent) {
1567 case MR_LINK_TRAINING1:
1568 success = (pattern_requested ==
1569 DP_PHY_TEST_PATTERN_D10_2);
1571 case MR_LINK_SYMBOL_ERM:
1572 success = ((pattern_requested ==
1573 DP_PHY_TEST_PATTERN_ERROR_COUNT) ||
1574 (pattern_requested ==
1575 DP_PHY_TEST_PATTERN_CP2520));
1578 success = (pattern_requested ==
1579 DP_PHY_TEST_PATTERN_PRBS7);
1581 case MR_LINK_CUSTOM80:
1582 success = (pattern_requested ==
1583 DP_PHY_TEST_PATTERN_80BIT_CUSTOM);
1585 case MR_LINK_TRAINING4:
1586 success = (pattern_requested ==
1587 DP_PHY_TEST_PATTERN_SEL_MASK);
1593 DRM_DEBUG_DP("%s: test->0x%x\n", success ? "success" : "failed",
1598 void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl)
1600 struct dp_ctrl_private *ctrl;
1601 u32 sink_request = 0x0;
1604 DRM_ERROR("invalid input\n");
1608 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1609 sink_request = ctrl->link->sink_request;
1611 if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1612 DRM_DEBUG_DP("PHY_TEST_PATTERN request\n");
1613 if (dp_ctrl_process_phy_test_request(ctrl)) {
1614 DRM_ERROR("process phy_test_req failed\n");
1619 if (sink_request & DP_LINK_STATUS_UPDATED) {
1620 if (dp_ctrl_link_maintenance(ctrl)) {
1621 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1626 if (sink_request & DP_TEST_LINK_TRAINING) {
1627 dp_link_send_test_response(ctrl->link);
1628 if (dp_ctrl_link_maintenance(ctrl)) {
1629 DRM_ERROR("LM failed: TEST_LINK_TRAINING\n");
1635 int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
1638 struct dp_ctrl_private *ctrl;
1640 int link_train_max_retries = 5;
1641 u32 const phy_cts_pixel_clk_khz = 148500;
1642 struct dp_cr_status cr;
1643 unsigned int training_step;
1648 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1650 rate = ctrl->panel->link_info.rate;
1652 dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
1654 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1655 DRM_DEBUG_DP("using phy test link parameters\n");
1656 if (!ctrl->panel->dp_mode.drm_mode.clock)
1657 ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
1659 ctrl->link->link_params.rate = rate;
1660 ctrl->link->link_params.num_lanes =
1661 ctrl->panel->link_info.num_lanes;
1662 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1665 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1666 ctrl->link->link_params.rate,
1667 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1669 rc = dp_ctrl_enable_mainlink_clocks(ctrl);
1673 while (--link_train_max_retries) {
1674 rc = dp_ctrl_reinitialize_mainlink(ctrl);
1676 DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n",
1681 training_step = DP_TRAINING_NONE;
1682 rc = dp_ctrl_setup_main_link(ctrl, &cr, &training_step);
1684 /* training completed successfully */
1686 } else if (training_step == DP_TRAINING_1) {
1687 /* link train_1 failed */
1688 if (!dp_catalog_link_is_connected(ctrl->catalog)) {
1692 rc = dp_ctrl_link_rate_down_shift(ctrl);
1693 if (rc < 0) { /* already in RBR = 1.6G */
1694 if (cr.lane_0_1 & DP_LANE0_1_CR_DONE) {
1696 * some lanes are ready,
1697 * reduce lane number
1699 rc = dp_ctrl_link_lane_down_shift(ctrl);
1700 if (rc < 0) { /* lane == 1 already */
1701 /* end with failure */
1705 /* end with failure */
1706 break; /* lane == 1 already */
1709 } else if (training_step == DP_TRAINING_2) {
1710 /* link train_2 failed, lower lane rate */
1711 if (!dp_catalog_link_is_connected(ctrl->catalog)) {
1715 rc = dp_ctrl_link_lane_down_shift(ctrl);
1717 /* end with failure */
1718 break; /* lane == 1 already */
1723 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1726 /* stop txing train pattern */
1727 dp_ctrl_clear_training_pattern(ctrl);
1730 * keep transmitting idle pattern until video ready
1731 * to avoid main link from loss of sync
1733 if (rc == 0) /* link train successfully */
1734 dp_ctrl_push_idle(dp_ctrl);
1736 /* link training failed */
1737 dp_ctrl_deinitialize_mainlink(ctrl);
1744 int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl)
1748 bool mainlink_ready = false;
1749 struct dp_ctrl_private *ctrl;
1754 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1756 rate = ctrl->panel->link_info.rate;
1758 ctrl->link->link_params.rate = rate;
1759 ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes;
1760 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
1762 DRM_DEBUG_DP("rate=%d, num_lanes=%d, pixel_rate=%d\n",
1763 ctrl->link->link_params.rate,
1764 ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
1766 if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
1767 ret = dp_ctrl_enable_mainlink_clocks(ctrl);
1769 DRM_ERROR("Failed to start link clocks. ret=%d\n", ret);
1774 ret = dp_ctrl_enable_stream_clocks(ctrl);
1776 DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
1780 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
1781 dp_ctrl_send_phy_test_pattern(ctrl);
1786 * Set up transfer unit values and set controller state to send
1789 reinit_completion(&ctrl->video_comp);
1791 dp_ctrl_configure_source_params(ctrl);
1793 dp_catalog_ctrl_config_msa(ctrl->catalog,
1794 ctrl->link->link_params.rate,
1795 ctrl->dp_ctrl.pixel_rate, dp_ctrl_use_fixed_nvid(ctrl));
1797 dp_ctrl_setup_tr_unit(ctrl);
1799 dp_catalog_ctrl_state_ctrl(ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO);
1801 ret = dp_ctrl_wait4video_ready(ctrl);
1805 mainlink_ready = dp_catalog_ctrl_mainlink_ready(ctrl->catalog);
1806 DRM_DEBUG_DP("mainlink %s\n", mainlink_ready ? "READY" : "NOT READY");
1812 int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
1814 struct dp_ctrl_private *ctrl;
1815 struct dp_io *dp_io;
1822 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1823 dp_io = &ctrl->parser->io;
1826 dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1828 dp_catalog_ctrl_reset(ctrl->catalog);
1830 ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false);
1832 DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret);
1834 ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false);
1836 DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
1842 DRM_DEBUG_DP("DP off done\n");
1846 void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
1848 struct dp_ctrl_private *ctrl;
1854 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1856 isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
1858 if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
1859 DRM_DEBUG_DP("dp_video_ready\n");
1860 complete(&ctrl->video_comp);
1863 if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) {
1864 DRM_DEBUG_DP("idle_patterns_sent\n");
1865 complete(&ctrl->idle_comp);
1869 struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
1870 struct dp_panel *panel, struct drm_dp_aux *aux,
1871 struct dp_power *power, struct dp_catalog *catalog,
1872 struct dp_parser *parser)
1874 struct dp_ctrl_private *ctrl;
1877 if (!dev || !panel || !aux ||
1878 !link || !catalog) {
1879 DRM_ERROR("invalid input\n");
1880 return ERR_PTR(-EINVAL);
1883 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1885 DRM_ERROR("Mem allocation failure\n");
1886 return ERR_PTR(-ENOMEM);
1889 ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");
1890 if (IS_ERR(ctrl->opp_table)) {
1891 dev_err(dev, "invalid DP OPP table in device tree\n");
1892 /* caller do PTR_ERR(ctrl->opp_table) */
1893 return (struct dp_ctrl *)ctrl->opp_table;
1896 /* OPP table is optional */
1897 ret = dev_pm_opp_of_add_table(dev);
1899 dev_err(dev, "failed to add DP OPP table\n");
1900 dev_pm_opp_put_clkname(ctrl->opp_table);
1901 ctrl->opp_table = NULL;
1904 init_completion(&ctrl->idle_comp);
1905 init_completion(&ctrl->video_comp);
1908 ctrl->parser = parser;
1909 ctrl->panel = panel;
1910 ctrl->power = power;
1913 ctrl->catalog = catalog;
1916 return &ctrl->dp_ctrl;
1919 void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
1921 struct dp_ctrl_private *ctrl;
1923 ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
1925 if (ctrl->opp_table) {
1926 dev_pm_opp_of_remove_table(ctrl->dev);
1927 dev_pm_opp_put_clkname(ctrl->opp_table);
1928 ctrl->opp_table = NULL;