1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_damage_helper.h>
10 #include <drm/drm_fourcc.h>
11 #include <drm/drm_print.h>
16 struct drm_plane base;
21 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
23 static int mdp5_plane_mode_set(struct drm_plane *plane,
24 struct drm_crtc *crtc, struct drm_framebuffer *fb,
25 struct drm_rect *src, struct drm_rect *dest);
27 static struct mdp5_kms *get_kms(struct drm_plane *plane)
29 struct msm_drm_private *priv = plane->dev->dev_private;
30 return to_mdp5_kms(to_mdp_kms(priv->kms));
33 static bool plane_enabled(struct drm_plane_state *state)
35 return state->visible;
38 static void mdp5_plane_destroy(struct drm_plane *plane)
40 struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
42 drm_plane_cleanup(plane);
47 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
48 struct drm_plane *plane)
50 drm_plane_create_rotation_property(plane,
58 /* helper to install properties which are common to planes and crtcs */
59 static void mdp5_plane_install_properties(struct drm_plane *plane,
60 struct drm_mode_object *obj)
62 struct drm_device *dev = plane->dev;
63 struct msm_drm_private *dev_priv = dev->dev_private;
64 struct drm_property *prop;
66 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
67 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
69 prop = drm_property_##fnc(dev, 0, #name, \
73 "Create property %s failed\n", \
77 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
79 drm_object_attach_property(&plane->base, prop, init_val); \
82 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
83 INSTALL_PROPERTY(name, NAME, init_val, \
84 create_range, min, max)
86 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
87 INSTALL_PROPERTY(name, NAME, init_val, \
88 create_enum, name##_prop_enum_list, \
89 ARRAY_SIZE(name##_prop_enum_list))
91 INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
93 mdp5_plane_install_rotation_property(dev, plane);
95 #undef INSTALL_RANGE_PROPERTY
96 #undef INSTALL_ENUM_PROPERTY
97 #undef INSTALL_PROPERTY
100 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
101 struct drm_plane_state *state, struct drm_property *property,
104 struct drm_device *dev = plane->dev;
105 struct mdp5_plane_state *pstate;
106 struct msm_drm_private *dev_priv = dev->dev_private;
109 pstate = to_mdp5_plane_state(state);
111 #define SET_PROPERTY(name, NAME, type) do { \
112 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
113 pstate->name = (type)val; \
114 DBG("Set property %s %d", #name, (type)val); \
119 SET_PROPERTY(zpos, ZPOS, uint8_t);
121 DRM_DEV_ERROR(dev->dev, "Invalid property\n");
128 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
129 const struct drm_plane_state *state,
130 struct drm_property *property, uint64_t *val)
132 struct drm_device *dev = plane->dev;
133 struct mdp5_plane_state *pstate;
134 struct msm_drm_private *dev_priv = dev->dev_private;
137 pstate = to_mdp5_plane_state(state);
139 #define GET_PROPERTY(name, NAME, type) do { \
140 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
141 *val = pstate->name; \
142 DBG("Get property %s %lld", #name, *val); \
147 GET_PROPERTY(zpos, ZPOS, uint8_t);
149 DRM_DEV_ERROR(dev->dev, "Invalid property\n");
157 mdp5_plane_atomic_print_state(struct drm_printer *p,
158 const struct drm_plane_state *state)
160 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
161 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
163 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
164 pstate->hwpipe->name : "(null)");
165 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
166 drm_printf(p, "\tright-hwpipe=%s\n",
167 pstate->r_hwpipe ? pstate->r_hwpipe->name :
169 drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
170 drm_printf(p, "\tzpos=%u\n", pstate->zpos);
171 drm_printf(p, "\talpha=%u\n", pstate->alpha);
172 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
175 static void mdp5_plane_reset(struct drm_plane *plane)
177 struct mdp5_plane_state *mdp5_state;
179 if (plane->state && plane->state->fb)
180 drm_framebuffer_put(plane->state->fb);
182 kfree(to_mdp5_plane_state(plane->state));
183 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
185 /* assign default blend parameters */
186 mdp5_state->alpha = 255;
187 mdp5_state->premultiplied = 0;
189 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
190 mdp5_state->zpos = STAGE_BASE;
192 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
194 mdp5_state->base.plane = plane;
196 plane->state = &mdp5_state->base;
199 static struct drm_plane_state *
200 mdp5_plane_duplicate_state(struct drm_plane *plane)
202 struct mdp5_plane_state *mdp5_state;
204 if (WARN_ON(!plane->state))
207 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
208 sizeof(*mdp5_state), GFP_KERNEL);
212 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
214 return &mdp5_state->base;
217 static void mdp5_plane_destroy_state(struct drm_plane *plane,
218 struct drm_plane_state *state)
220 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
223 drm_framebuffer_put(state->fb);
228 static const struct drm_plane_funcs mdp5_plane_funcs = {
229 .update_plane = drm_atomic_helper_update_plane,
230 .disable_plane = drm_atomic_helper_disable_plane,
231 .destroy = mdp5_plane_destroy,
232 .atomic_set_property = mdp5_plane_atomic_set_property,
233 .atomic_get_property = mdp5_plane_atomic_get_property,
234 .reset = mdp5_plane_reset,
235 .atomic_duplicate_state = mdp5_plane_duplicate_state,
236 .atomic_destroy_state = mdp5_plane_destroy_state,
237 .atomic_print_state = mdp5_plane_atomic_print_state,
240 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
241 struct drm_plane_state *old_state)
243 struct mdp5_kms *mdp5_kms = get_kms(plane);
244 struct msm_kms *kms = &mdp5_kms->base.base;
245 struct drm_framebuffer *fb = old_state->fb;
250 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
251 msm_framebuffer_cleanup(fb, kms->aspace);
254 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
255 struct drm_plane_state *state)
257 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
258 struct drm_plane *plane = state->plane;
259 struct drm_plane_state *old_state = plane->state;
260 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
261 bool new_hwpipe = false;
262 bool need_right_hwpipe = false;
263 uint32_t max_width, max_height;
264 bool out_of_bounds = false;
266 int min_scale, max_scale;
269 DBG("%s: check (%d -> %d)", plane->name,
270 plane_enabled(old_state), plane_enabled(state));
272 max_width = config->hw->lm.max_width << 16;
273 max_height = config->hw->lm.max_height << 16;
275 /* Make sure source dimensions are within bounds. */
276 if (state->src_h > max_height)
277 out_of_bounds = true;
279 if (state->src_w > max_width) {
280 /* If source split is supported, we can go up to 2x
281 * the max LM width, but we'd need to stage another
282 * hwpipe to the right LM. So, the drm_plane would
283 * consist of 2 hwpipes.
285 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
286 (state->src_w <= 2 * max_width))
287 need_right_hwpipe = true;
289 out_of_bounds = true;
293 struct drm_rect src = drm_plane_state_src(state);
294 DBG("Invalid source size "DRM_RECT_FP_FMT,
295 DRM_RECT_FP_ARG(&src));
299 min_scale = FRAC_16_16(1, 8);
300 max_scale = FRAC_16_16(8, 1);
302 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
303 min_scale, max_scale,
308 if (plane_enabled(state)) {
309 unsigned int rotation;
310 const struct mdp_format *format;
311 struct mdp5_kms *mdp5_kms = get_kms(plane);
314 format = to_mdp_format(msm_framebuffer_format(state->fb));
315 if (MDP_FORMAT_IS_YUV(format))
316 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
318 if (((state->src_w >> 16) != state->crtc_w) ||
319 ((state->src_h >> 16) != state->crtc_h))
320 caps |= MDP_PIPE_CAP_SCALE;
322 rotation = drm_rotation_simplify(state->rotation,
327 if (rotation & DRM_MODE_REFLECT_X)
328 caps |= MDP_PIPE_CAP_HFLIP;
330 if (rotation & DRM_MODE_REFLECT_Y)
331 caps |= MDP_PIPE_CAP_VFLIP;
333 if (plane->type == DRM_PLANE_TYPE_CURSOR)
334 caps |= MDP_PIPE_CAP_CURSOR;
336 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
337 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
341 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
342 * or we're switching from 2 hw pipes to 1 hw pipe because the
343 * new src_w can be supported by 1 hw pipe itself.
345 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
346 (!need_right_hwpipe && mdp5_state->r_hwpipe))
350 const struct mdp_format *format =
351 to_mdp_format(msm_framebuffer_format(state->fb));
353 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
354 state->src_w >> 16, false);
356 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
360 /* (re)assign hwpipe if needed, otherwise keep old one: */
362 /* TODO maybe we want to re-assign hwpipe sometimes
363 * in cases when we no-longer need some caps to make
364 * it available for other planes?
366 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
367 struct mdp5_hw_pipe *old_right_hwpipe =
368 mdp5_state->r_hwpipe;
369 struct mdp5_hw_pipe *new_hwpipe = NULL;
370 struct mdp5_hw_pipe *new_right_hwpipe = NULL;
372 ret = mdp5_pipe_assign(state->state, plane, caps,
375 &new_right_hwpipe : NULL);
377 DBG("%s: failed to assign hwpipe(s)!",
382 mdp5_state->hwpipe = new_hwpipe;
383 if (need_right_hwpipe)
384 mdp5_state->r_hwpipe = new_right_hwpipe;
387 * set it to NULL so that the driver knows we
388 * don't have a right hwpipe when committing a
391 mdp5_state->r_hwpipe = NULL;
394 mdp5_pipe_release(state->state, old_hwpipe);
395 mdp5_pipe_release(state->state, old_right_hwpipe);
398 mdp5_pipe_release(state->state, mdp5_state->hwpipe);
399 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
400 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
406 static int mdp5_plane_atomic_check(struct drm_plane *plane,
407 struct drm_atomic_state *state)
409 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
411 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
413 struct drm_crtc *crtc;
414 struct drm_crtc_state *crtc_state;
416 crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc;
420 crtc_state = drm_atomic_get_existing_crtc_state(state,
422 if (WARN_ON(!crtc_state))
425 return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
428 static void mdp5_plane_atomic_update(struct drm_plane *plane,
429 struct drm_atomic_state *state)
431 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
434 DBG("%s: update", plane->name);
436 if (plane_enabled(new_state)) {
439 ret = mdp5_plane_mode_set(plane,
440 new_state->crtc, new_state->fb,
441 &new_state->src, &new_state->dst);
442 /* atomic_check should have ensured that this doesn't fail */
447 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
448 struct drm_atomic_state *state)
450 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
452 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state);
453 struct drm_crtc_state *crtc_state;
454 int min_scale, max_scale;
457 crtc_state = drm_atomic_get_existing_crtc_state(state,
458 new_plane_state->crtc);
459 if (WARN_ON(!crtc_state))
462 if (!crtc_state->active)
465 mdp5_state = to_mdp5_plane_state(new_plane_state);
467 /* don't use fast path if we don't have a hwpipe allocated yet */
468 if (!mdp5_state->hwpipe)
471 /* only allow changing of position(crtc x/y or src x/y) in fast path */
472 if (plane->state->crtc != new_plane_state->crtc ||
473 plane->state->src_w != new_plane_state->src_w ||
474 plane->state->src_h != new_plane_state->src_h ||
475 plane->state->crtc_w != new_plane_state->crtc_w ||
476 plane->state->crtc_h != new_plane_state->crtc_h ||
478 plane->state->fb != new_plane_state->fb)
481 min_scale = FRAC_16_16(1, 8);
482 max_scale = FRAC_16_16(8, 1);
484 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
485 min_scale, max_scale,
491 * if the visibility of the plane changes (i.e, if the cursor is
492 * clipped out completely, we can't take the async path because
493 * we need to stage/unstage the plane from the Layer Mixer(s). We
494 * also assign/unassign the hwpipe(s) tied to the plane. We avoid
495 * taking the fast path for both these reasons.
497 if (new_plane_state->visible != plane->state->visible)
503 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
504 struct drm_atomic_state *state)
506 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
508 struct drm_framebuffer *old_fb = plane->state->fb;
510 plane->state->src_x = new_state->src_x;
511 plane->state->src_y = new_state->src_y;
512 plane->state->crtc_x = new_state->crtc_x;
513 plane->state->crtc_y = new_state->crtc_y;
515 if (plane_enabled(new_state)) {
516 struct mdp5_ctl *ctl;
517 struct mdp5_pipeline *pipeline =
518 mdp5_crtc_get_pipeline(new_state->crtc);
521 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
522 &new_state->src, &new_state->dst);
525 ctl = mdp5_crtc_get_ctl(new_state->crtc);
527 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
530 *to_mdp5_plane_state(plane->state) =
531 *to_mdp5_plane_state(new_state);
533 new_state->fb = old_fb;
536 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
537 .prepare_fb = msm_atomic_prepare_fb,
538 .cleanup_fb = mdp5_plane_cleanup_fb,
539 .atomic_check = mdp5_plane_atomic_check,
540 .atomic_update = mdp5_plane_atomic_update,
541 .atomic_async_check = mdp5_plane_atomic_async_check,
542 .atomic_async_update = mdp5_plane_atomic_async_update,
545 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
547 struct drm_framebuffer *fb)
549 struct msm_kms *kms = &mdp5_kms->base.base;
551 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
552 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
553 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
555 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
556 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
557 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
559 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
560 msm_framebuffer_iova(fb, kms->aspace, 0));
561 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
562 msm_framebuffer_iova(fb, kms->aspace, 1));
563 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
564 msm_framebuffer_iova(fb, kms->aspace, 2));
565 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
566 msm_framebuffer_iova(fb, kms->aspace, 3));
569 /* Note: mdp5_plane->pipe_lock must be locked */
570 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
572 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
573 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
575 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
578 /* Note: mdp5_plane->pipe_lock must be locked */
579 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
582 uint32_t i, mode = 0; /* RGB, no CSC */
588 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
589 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
590 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
591 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
592 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
593 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
595 matrix = csc->matrix;
596 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
597 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
598 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
599 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
600 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
601 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
602 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
603 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
604 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
605 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
606 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
607 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
608 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
609 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
611 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
612 uint32_t *pre_clamp = csc->pre_clamp;
613 uint32_t *post_clamp = csc->post_clamp;
615 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
616 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
617 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
619 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
620 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
621 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
623 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
624 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
626 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
627 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
631 #define PHASE_STEP_SHIFT 21
632 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
634 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
638 if (src == 0 || dst == 0)
642 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
643 * where 2^21 represents the unity "1" in fixed-point hardware design.
644 * This leaves 5 bits for the integer part (downscale case):
645 * -> maximum downscale ratio = 0b1_1111 = 31
647 if (src > (dst * DOWN_SCALE_RATIO_MAX))
650 unit = 1 << PHASE_STEP_SHIFT;
651 *out_phase = mult_frac(unit, src, dst);
656 static int calc_scalex_steps(struct drm_plane *plane,
657 uint32_t pixel_format, uint32_t src, uint32_t dest,
658 uint32_t phasex_steps[COMP_MAX])
660 const struct drm_format_info *info = drm_format_info(pixel_format);
661 struct mdp5_kms *mdp5_kms = get_kms(plane);
662 struct device *dev = mdp5_kms->dev->dev;
663 uint32_t phasex_step;
666 ret = calc_phase_step(src, dest, &phasex_step);
668 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
672 phasex_steps[COMP_0] = phasex_step;
673 phasex_steps[COMP_3] = phasex_step;
674 phasex_steps[COMP_1_2] = phasex_step / info->hsub;
679 static int calc_scaley_steps(struct drm_plane *plane,
680 uint32_t pixel_format, uint32_t src, uint32_t dest,
681 uint32_t phasey_steps[COMP_MAX])
683 const struct drm_format_info *info = drm_format_info(pixel_format);
684 struct mdp5_kms *mdp5_kms = get_kms(plane);
685 struct device *dev = mdp5_kms->dev->dev;
686 uint32_t phasey_step;
689 ret = calc_phase_step(src, dest, &phasey_step);
691 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
695 phasey_steps[COMP_0] = phasey_step;
696 phasey_steps[COMP_3] = phasey_step;
697 phasey_steps[COMP_1_2] = phasey_step / info->vsub;
702 static uint32_t get_scale_config(const struct mdp_format *format,
703 uint32_t src, uint32_t dst, bool horz)
705 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
706 bool scaling = format->is_yuv ? true : (src != dst);
708 uint32_t ya_filter, uv_filter;
709 bool yuv = format->is_yuv;
715 sub = horz ? info->hsub : info->vsub;
716 uv_filter = ((src / sub) <= dst) ?
717 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
719 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
722 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
723 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
724 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
725 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
727 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
728 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
729 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
730 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
733 static void calc_pixel_ext(const struct mdp_format *format,
734 uint32_t src, uint32_t dst, uint32_t phase_step[2],
735 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
738 bool scaling = format->is_yuv ? true : (src != dst);
743 * We assume here that:
744 * 1. PCMN filter is used for downscale
745 * 2. bilinear filter is used for upscale
746 * 3. we are in a single pipe configuration
749 for (i = 0; i < COMP_MAX; i++) {
750 pix_ext_edge1[i] = 0;
751 pix_ext_edge2[i] = scaling ? 1 : 0;
755 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
756 const struct mdp_format *format,
757 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
758 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
760 const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
761 uint32_t lr, tb, req;
764 for (i = 0; i < COMP_MAX; i++) {
765 uint32_t roi_w = src_w;
766 uint32_t roi_h = src_h;
768 if (format->is_yuv && i == COMP_1_2) {
773 lr = (pe_left[i] >= 0) ?
774 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
775 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
777 lr |= (pe_right[i] >= 0) ?
778 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
779 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
781 tb = (pe_top[i] >= 0) ?
782 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
783 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
785 tb |= (pe_bottom[i] >= 0) ?
786 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
787 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
789 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
790 pe_left[i] + pe_right[i]);
792 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
793 pe_top[i] + pe_bottom[i]);
795 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
796 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
797 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
799 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
800 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
801 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
802 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
803 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
804 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
806 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
807 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
808 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
809 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
810 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
811 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
819 int bottom[COMP_MAX];
827 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
828 struct mdp5_hw_pipe *hwpipe,
829 struct drm_framebuffer *fb,
830 struct phase_step *step,
831 struct pixel_ext *pe,
832 u32 scale_config, u32 hdecm, u32 vdecm,
833 bool hflip, bool vflip,
834 int crtc_x, int crtc_y,
835 unsigned int crtc_w, unsigned int crtc_h,
836 u32 src_img_w, u32 src_img_h,
837 u32 src_x, u32 src_y,
838 u32 src_w, u32 src_h)
840 enum mdp5_pipe pipe = hwpipe->pipe;
841 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
842 const struct mdp_format *format =
843 to_mdp_format(msm_framebuffer_format(fb));
845 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
846 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
847 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
849 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
850 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
851 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
853 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
854 MDP5_PIPE_SRC_XY_X(src_x) |
855 MDP5_PIPE_SRC_XY_Y(src_y));
857 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
858 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
859 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
861 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
862 MDP5_PIPE_OUT_XY_X(crtc_x) |
863 MDP5_PIPE_OUT_XY_Y(crtc_y));
865 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
866 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
867 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
868 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
869 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
870 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
871 MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
872 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
873 COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
874 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
875 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
877 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
878 MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
879 MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
880 MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
881 MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
883 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
884 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
885 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
886 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
887 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
889 /* not using secure mode: */
890 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
892 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
893 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
894 src_w, pe->left, pe->right,
895 src_h, pe->top, pe->bottom);
897 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
898 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
900 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
902 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
904 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
906 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
907 MDP5_PIPE_DECIMATION_VERT(vdecm) |
908 MDP5_PIPE_DECIMATION_HORZ(hdecm));
909 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
913 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
914 if (MDP_FORMAT_IS_YUV(format))
915 csc_enable(mdp5_kms, pipe,
916 mdp_get_default_csc_cfg(CSC_YUV2RGB));
918 csc_disable(mdp5_kms, pipe);
921 set_scanout_locked(mdp5_kms, pipe, fb);
924 static int mdp5_plane_mode_set(struct drm_plane *plane,
925 struct drm_crtc *crtc, struct drm_framebuffer *fb,
926 struct drm_rect *src, struct drm_rect *dest)
928 struct drm_plane_state *pstate = plane->state;
929 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
930 struct mdp5_kms *mdp5_kms = get_kms(plane);
931 enum mdp5_pipe pipe = hwpipe->pipe;
932 struct mdp5_hw_pipe *right_hwpipe;
933 const struct mdp_format *format;
934 uint32_t nplanes, config = 0;
935 struct phase_step step = { { 0 } };
936 struct pixel_ext pe = { { 0 } };
937 uint32_t hdecm = 0, vdecm = 0;
939 unsigned int rotation;
942 unsigned int crtc_w, crtc_h;
943 uint32_t src_x, src_y;
944 uint32_t src_w, src_h;
945 uint32_t src_img_w, src_img_h;
948 nplanes = fb->format->num_planes;
950 /* bad formats should already be rejected: */
951 if (WARN_ON(nplanes > pipe2nclients(pipe)))
954 format = to_mdp_format(msm_framebuffer_format(fb));
955 pix_format = format->base.pixel_format;
959 src_w = drm_rect_width(src);
960 src_h = drm_rect_height(src);
964 crtc_w = drm_rect_width(dest);
965 crtc_h = drm_rect_height(dest);
967 /* src values are in Q16 fixed point, convert to integer: */
973 src_img_w = min(fb->width, src_w);
974 src_img_h = min(fb->height, src_h);
976 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
977 fb->base.id, src_x, src_y, src_w, src_h,
978 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
980 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
983 * if the plane comprises of 2 hw pipes, assume that the width
984 * is split equally across them. The only parameters that varies
985 * between the 2 pipes are src_x and crtc_x
992 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
996 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
1000 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1001 calc_pixel_ext(format, src_w, crtc_w, step.x,
1002 pe.left, pe.right, true);
1003 calc_pixel_ext(format, src_h, crtc_h, step.y,
1004 pe.top, pe.bottom, false);
1007 /* TODO calc hdecm, vdecm */
1009 /* SCALE is used to both scale and up-sample chroma components */
1010 config |= get_scale_config(format, src_w, crtc_w, true);
1011 config |= get_scale_config(format, src_h, crtc_h, false);
1012 DBG("scale config = %x", config);
1014 rotation = drm_rotation_simplify(pstate->rotation,
1016 DRM_MODE_REFLECT_X |
1017 DRM_MODE_REFLECT_Y);
1018 hflip = !!(rotation & DRM_MODE_REFLECT_X);
1019 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1021 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1022 config, hdecm, vdecm, hflip, vflip,
1023 crtc_x, crtc_y, crtc_w, crtc_h,
1024 src_img_w, src_img_h,
1025 src_x, src_y, src_w, src_h);
1027 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1028 config, hdecm, vdecm, hflip, vflip,
1029 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1030 src_img_w, src_img_h,
1031 src_x + src_w, src_y, src_w, src_h);
1037 * Use this func and the one below only after the atomic state has been
1038 * successfully swapped
1040 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1042 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1044 if (WARN_ON(!pstate->hwpipe))
1047 return pstate->hwpipe->pipe;
1050 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1052 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1054 if (!pstate->r_hwpipe)
1057 return pstate->r_hwpipe->pipe;
1060 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1062 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1065 if (WARN_ON(!pstate->hwpipe))
1068 mask = pstate->hwpipe->flush_mask;
1070 if (pstate->r_hwpipe)
1071 mask |= pstate->r_hwpipe->flush_mask;
1076 /* initialize plane */
1077 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1078 enum drm_plane_type type)
1080 struct drm_plane *plane = NULL;
1081 struct mdp5_plane *mdp5_plane;
1084 mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1090 plane = &mdp5_plane->base;
1092 mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1093 ARRAY_SIZE(mdp5_plane->formats), false);
1095 ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1096 mdp5_plane->formats, mdp5_plane->nformats,
1101 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1103 mdp5_plane_install_properties(plane, &plane->base);
1105 drm_plane_enable_fb_damage_clips(plane);
1111 mdp5_plane_destroy(plane);
1113 return ERR_PTR(ret);