drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  */
   7
   8 #include <drm/drm_atomic.h>
   9 #include <drm/drm_damage_helper.h>
  10 #include <drm/drm_fourcc.h>
  11 #include <drm/drm_print.h>
  12
  13 #include "mdp5_kms.h"
  14
  15 struct mdp5_plane {
  16         struct drm_plane base;
  17
  18         uint32_t nformats;
  19         uint32_t formats[32];
  20 };
  21 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  22
  23 static int mdp5_plane_mode_set(struct drm_plane *plane,
  24                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  25                 struct drm_rect *src, struct drm_rect *dest);
  26
  27 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  28 {
  29         struct msm_drm_private *priv = plane->dev->dev_private;
  30         return to_mdp5_kms(to_mdp_kms(priv->kms));
  31 }
  32
  33 static bool plane_enabled(struct drm_plane_state *state)
  34 {
  35         return state->visible;
  36 }
  37
  38 static void mdp5_plane_destroy(struct drm_plane *plane)
  39 {
  40         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  41
  42         drm_plane_cleanup(plane);
  43
  44         kfree(mdp5_plane);
  45 }
  46
  47 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  48                 struct drm_plane *plane)
  49 {
  50         drm_plane_create_rotation_property(plane,
  51                                            DRM_MODE_ROTATE_0,
  52                                            DRM_MODE_ROTATE_0 |
  53                                            DRM_MODE_ROTATE_180 |
  54                                            DRM_MODE_REFLECT_X |
  55                                            DRM_MODE_REFLECT_Y);
  56 }
  57
  58 /* helper to install properties which are common to planes and crtcs */
  59 static void mdp5_plane_install_properties(struct drm_plane *plane,
  60                 struct drm_mode_object *obj)
  61 {
  62         struct drm_device *dev = plane->dev;
  63         struct msm_drm_private *dev_priv = dev->dev_private;
  64         struct drm_property *prop;
  65
  66 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  67                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  68                 if (!prop) { \
  69                         prop = drm_property_##fnc(dev, 0, #name, \
  70                                 ##__VA_ARGS__); \
  71                         if (!prop) { \
  72                                 dev_warn(dev->dev, \
  73                                         "Create property %s failed\n", \
  74                                         #name); \
  75                                 return; \
  76                         } \
  77                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  78                 } \
  79                 drm_object_attach_property(&plane->base, prop, init_val); \
  80         } while (0)
  81
  82 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
  83                 INSTALL_PROPERTY(name, NAME, init_val, \
  84                                 create_range, min, max)
  85
  86 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
  87                 INSTALL_PROPERTY(name, NAME, init_val, \
  88                                 create_enum, name##_prop_enum_list, \
  89                                 ARRAY_SIZE(name##_prop_enum_list))
  90
  91         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
  92
  93         mdp5_plane_install_rotation_property(dev, plane);
  94
  95 #undef INSTALL_RANGE_PROPERTY
  96 #undef INSTALL_ENUM_PROPERTY
  97 #undef INSTALL_PROPERTY
  98 }
  99
 100 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 101                 struct drm_plane_state *state, struct drm_property *property,
 102                 uint64_t val)
 103 {
 104         struct drm_device *dev = plane->dev;
 105         struct mdp5_plane_state *pstate;
 106         struct msm_drm_private *dev_priv = dev->dev_private;
 107         int ret = 0;
 108
 109         pstate = to_mdp5_plane_state(state);
 110
 111 #define SET_PROPERTY(name, NAME, type) do { \
 112                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 113                         pstate->name = (type)val; \
 114                         DBG("Set property %s %d", #name, (type)val); \
 115                         goto done; \
 116                 } \
 117         } while (0)
 118
 119         SET_PROPERTY(zpos, ZPOS, uint8_t);
 120
 121         DRM_DEV_ERROR(dev->dev, "Invalid property\n");
 122         ret = -EINVAL;
 123 done:
 124         return ret;
 125 #undef SET_PROPERTY
 126 }
 127
 128 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 129                 const struct drm_plane_state *state,
 130                 struct drm_property *property, uint64_t *val)
 131 {
 132         struct drm_device *dev = plane->dev;
 133         struct mdp5_plane_state *pstate;
 134         struct msm_drm_private *dev_priv = dev->dev_private;
 135         int ret = 0;
 136
 137         pstate = to_mdp5_plane_state(state);
 138
 139 #define GET_PROPERTY(name, NAME, type) do { \
 140                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 141                         *val = pstate->name; \
 142                         DBG("Get property %s %lld", #name, *val); \
 143                         goto done; \
 144                 } \
 145         } while (0)
 146
 147         GET_PROPERTY(zpos, ZPOS, uint8_t);
 148
 149         DRM_DEV_ERROR(dev->dev, "Invalid property\n");
 150         ret = -EINVAL;
 151 done:
 152         return ret;
 153 #undef SET_PROPERTY
 154 }
 155
 156 static void
 157 mdp5_plane_atomic_print_state(struct drm_printer *p,
 158                 const struct drm_plane_state *state)
 159 {
 160         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 161         struct mdp5_kms *mdp5_kms = get_kms(state->plane);
 162
 163         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 164                         pstate->hwpipe->name : "(null)");
 165         if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
 166                 drm_printf(p, "\tright-hwpipe=%s\n",
 167                            pstate->r_hwpipe ? pstate->r_hwpipe->name :
 168                                               "(null)");
 169         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 170         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 171         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 172         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 173 }
 174
 175 static void mdp5_plane_reset(struct drm_plane *plane)
 176 {
 177         struct mdp5_plane_state *mdp5_state;
 178
 179         if (plane->state && plane->state->fb)
 180                 drm_framebuffer_put(plane->state->fb);
 181
 182         kfree(to_mdp5_plane_state(plane->state));
 183         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 184
 185         /* assign default blend parameters */
 186         mdp5_state->alpha = 255;
 187         mdp5_state->premultiplied = 0;
 188
 189         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 190                 mdp5_state->zpos = STAGE_BASE;
 191         else
 192                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 193
 194         mdp5_state->base.plane = plane;
 195
 196         plane->state = &mdp5_state->base;
 197 }
 198
 199 static struct drm_plane_state *
 200 mdp5_plane_duplicate_state(struct drm_plane *plane)
 201 {
 202         struct mdp5_plane_state *mdp5_state;
 203
 204         if (WARN_ON(!plane->state))
 205                 return NULL;
 206
 207         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 208                         sizeof(*mdp5_state), GFP_KERNEL);
 209         if (!mdp5_state)
 210                 return NULL;
 211
 212         __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
 213
 214         return &mdp5_state->base;
 215 }
 216
 217 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 218                 struct drm_plane_state *state)
 219 {
 220         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 221
 222         if (state->fb)
 223                 drm_framebuffer_put(state->fb);
 224
 225         kfree(pstate);
 226 }
 227
 228 static const struct drm_plane_funcs mdp5_plane_funcs = {
 229                 .update_plane = drm_atomic_helper_update_plane,
 230                 .disable_plane = drm_atomic_helper_disable_plane,
 231                 .destroy = mdp5_plane_destroy,
 232                 .atomic_set_property = mdp5_plane_atomic_set_property,
 233                 .atomic_get_property = mdp5_plane_atomic_get_property,
 234                 .reset = mdp5_plane_reset,
 235                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 236                 .atomic_destroy_state = mdp5_plane_destroy_state,
 237                 .atomic_print_state = mdp5_plane_atomic_print_state,
 238 };
 239
 240 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 241                                   struct drm_plane_state *old_state)
 242 {
 243         struct mdp5_kms *mdp5_kms = get_kms(plane);
 244         struct msm_kms *kms = &mdp5_kms->base.base;
 245         struct drm_framebuffer *fb = old_state->fb;
 246
 247         if (!fb)
 248                 return;
 249
 250         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 251         msm_framebuffer_cleanup(fb, kms->aspace);
 252 }
 253
 254 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
 255                                               struct drm_plane_state *state)
 256 {
 257         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 258         struct drm_plane *plane = state->plane;
 259         struct drm_plane_state *old_state = plane->state;
 260         struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
 261         bool new_hwpipe = false;
 262         bool need_right_hwpipe = false;
 263         uint32_t max_width, max_height;
 264         bool out_of_bounds = false;
 265         uint32_t caps = 0;
 266         int min_scale, max_scale;
 267         int ret;
 268
 269         DBG("%s: check (%d -> %d)", plane->name,
 270                         plane_enabled(old_state), plane_enabled(state));
 271
 272         max_width = config->hw->lm.max_width << 16;
 273         max_height = config->hw->lm.max_height << 16;
 274
 275         /* Make sure source dimensions are within bounds. */
 276         if (state->src_h > max_height)
 277                 out_of_bounds = true;
 278
 279         if (state->src_w > max_width) {
 280                 /* If source split is supported, we can go up to 2x
 281                  * the max LM width, but we'd need to stage another
 282                  * hwpipe to the right LM. So, the drm_plane would
 283                  * consist of 2 hwpipes.
 284                  */
 285                 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
 286                     (state->src_w <= 2 * max_width))
 287                         need_right_hwpipe = true;
 288                 else
 289                         out_of_bounds = true;
 290         }
 291
 292         if (out_of_bounds) {
 293                 struct drm_rect src = drm_plane_state_src(state);
 294                 DBG("Invalid source size "DRM_RECT_FP_FMT,
 295                                 DRM_RECT_FP_ARG(&src));
 296                 return -ERANGE;
 297         }
 298
 299         min_scale = FRAC_16_16(1, 8);
 300         max_scale = FRAC_16_16(8, 1);
 301
 302         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 303                                                   min_scale, max_scale,
 304                                                   true, true);
 305         if (ret)
 306                 return ret;
 307
 308         if (plane_enabled(state)) {
 309                 unsigned int rotation;
 310                 const struct mdp_format *format;
 311                 struct mdp5_kms *mdp5_kms = get_kms(plane);
 312                 uint32_t blkcfg = 0;
 313
 314                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 315                 if (MDP_FORMAT_IS_YUV(format))
 316                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 317
 318                 if (((state->src_w >> 16) != state->crtc_w) ||
 319                                 ((state->src_h >> 16) != state->crtc_h))
 320                         caps |= MDP_PIPE_CAP_SCALE;
 321
 322                 rotation = drm_rotation_simplify(state->rotation,
 323                                                  DRM_MODE_ROTATE_0 |
 324                                                  DRM_MODE_REFLECT_X |
 325                                                  DRM_MODE_REFLECT_Y);
 326
 327                 if (rotation & DRM_MODE_REFLECT_X)
 328                         caps |= MDP_PIPE_CAP_HFLIP;
 329
 330                 if (rotation & DRM_MODE_REFLECT_Y)
 331                         caps |= MDP_PIPE_CAP_VFLIP;
 332
 333                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 334                         caps |= MDP_PIPE_CAP_CURSOR;
 335
 336                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 337                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 338                         new_hwpipe = true;
 339
 340                 /*
 341                  * (re)allocte hw pipe if we're either requesting for 2 hw pipes
 342                  * or we're switching from 2 hw pipes to 1 hw pipe because the
 343                  * new src_w can be supported by 1 hw pipe itself.
 344                  */
 345                 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
 346                     (!need_right_hwpipe && mdp5_state->r_hwpipe))
 347                         new_hwpipe = true;
 348
 349                 if (mdp5_kms->smp) {
 350                         const struct mdp_format *format =
 351                                 to_mdp_format(msm_framebuffer_format(state->fb));
 352
 353                         blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
 354                                         state->src_w >> 16, false);
 355
 356                         if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
 357                                 new_hwpipe = true;
 358                 }
 359
 360                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 361                 if (new_hwpipe) {
 362                         /* TODO maybe we want to re-assign hwpipe sometimes
 363                          * in cases when we no-longer need some caps to make
 364                          * it available for other planes?
 365                          */
 366                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 367                         struct mdp5_hw_pipe *old_right_hwpipe =
 368                                                           mdp5_state->r_hwpipe;
 369                         struct mdp5_hw_pipe *new_hwpipe = NULL;
 370                         struct mdp5_hw_pipe *new_right_hwpipe = NULL;
 371
 372                         ret = mdp5_pipe_assign(state->state, plane, caps,
 373                                                blkcfg, &new_hwpipe,
 374                                                need_right_hwpipe ?
 375                                                &new_right_hwpipe : NULL);
 376                         if (ret) {
 377                                 DBG("%s: failed to assign hwpipe(s)!",
 378                                     plane->name);
 379                                 return ret;
 380                         }
 381
 382                         mdp5_state->hwpipe = new_hwpipe;
 383                         if (need_right_hwpipe)
 384                                 mdp5_state->r_hwpipe = new_right_hwpipe;
 385                         else
 386                                 /*
 387                                  * set it to NULL so that the driver knows we
 388                                  * don't have a right hwpipe when committing a
 389                                  * new state
 390                                  */
 391                                 mdp5_state->r_hwpipe = NULL;
 392
 393
 394                         mdp5_pipe_release(state->state, old_hwpipe);
 395                         mdp5_pipe_release(state->state, old_right_hwpipe);
 396                 }
 397         } else {
 398                 mdp5_pipe_release(state->state, mdp5_state->hwpipe);
 399                 mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
 400                 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 407                                    struct drm_atomic_state *state)
 408 {
 409         struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
 410                                                                                  plane);
 411         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 412                                                                                  plane);
 413         struct drm_crtc *crtc;
 414         struct drm_crtc_state *crtc_state;
 415
 416         crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc;
 417         if (!crtc)
 418                 return 0;
 419
 420         crtc_state = drm_atomic_get_existing_crtc_state(state,
 421                                                         crtc);
 422         if (WARN_ON(!crtc_state))
 423                 return -EINVAL;
 424
 425         return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
 426 }
 427
 428 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 429                                      struct drm_atomic_state *state)
 430 {
 431         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 432                                                                            plane);
 433
 434         DBG("%s: update", plane->name);
 435
 436         if (plane_enabled(new_state)) {
 437                 int ret;
 438
 439                 ret = mdp5_plane_mode_set(plane,
 440                                 new_state->crtc, new_state->fb,
 441                                 &new_state->src, &new_state->dst);
 442                 /* atomic_check should have ensured that this doesn't fail */
 443                 WARN_ON(ret < 0);
 444         }
 445 }
 446
 447 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
 448                                          struct drm_atomic_state *state)
 449 {
 450         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 451                                                                                  plane);
 452         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state);
 453         struct drm_crtc_state *crtc_state;
 454         int min_scale, max_scale;
 455         int ret;
 456
 457         crtc_state = drm_atomic_get_existing_crtc_state(state,
 458                                                         new_plane_state->crtc);
 459         if (WARN_ON(!crtc_state))
 460                 return -EINVAL;
 461
 462         if (!crtc_state->active)
 463                 return -EINVAL;
 464
 465         mdp5_state = to_mdp5_plane_state(new_plane_state);
 466
 467         /* don't use fast path if we don't have a hwpipe allocated yet */
 468         if (!mdp5_state->hwpipe)
 469                 return -EINVAL;
 470
 471         /* only allow changing of position(crtc x/y or src x/y) in fast path */
 472         if (plane->state->crtc != new_plane_state->crtc ||
 473             plane->state->src_w != new_plane_state->src_w ||
 474             plane->state->src_h != new_plane_state->src_h ||
 475             plane->state->crtc_w != new_plane_state->crtc_w ||
 476             plane->state->crtc_h != new_plane_state->crtc_h ||
 477             !plane->state->fb ||
 478             plane->state->fb != new_plane_state->fb)
 479                 return -EINVAL;
 480
 481         min_scale = FRAC_16_16(1, 8);
 482         max_scale = FRAC_16_16(8, 1);
 483
 484         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 485                                                   min_scale, max_scale,
 486                                                   true, true);
 487         if (ret)
 488                 return ret;
 489
 490         /*
 491          * if the visibility of the plane changes (i.e, if the cursor is
 492          * clipped out completely, we can't take the async path because
 493          * we need to stage/unstage the plane from the Layer Mixer(s). We
 494          * also assign/unassign the hwpipe(s) tied to the plane. We avoid
 495          * taking the fast path for both these reasons.
 496          */
 497         if (new_plane_state->visible != plane->state->visible)
 498                 return -EINVAL;
 499
 500         return 0;
 501 }
 502
 503 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
 504                                            struct drm_atomic_state *state)
 505 {
 506         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 507                                                                            plane);
 508         struct drm_framebuffer *old_fb = plane->state->fb;
 509
 510         plane->state->src_x = new_state->src_x;
 511         plane->state->src_y = new_state->src_y;
 512         plane->state->crtc_x = new_state->crtc_x;
 513         plane->state->crtc_y = new_state->crtc_y;
 514
 515         if (plane_enabled(new_state)) {
 516                 struct mdp5_ctl *ctl;
 517                 struct mdp5_pipeline *pipeline =
 518                                         mdp5_crtc_get_pipeline(new_state->crtc);
 519                 int ret;
 520
 521                 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
 522                                 &new_state->src, &new_state->dst);
 523                 WARN_ON(ret < 0);
 524
 525                 ctl = mdp5_crtc_get_ctl(new_state->crtc);
 526
 527                 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
 528         }
 529
 530         *to_mdp5_plane_state(plane->state) =
 531                 *to_mdp5_plane_state(new_state);
 532
 533         new_state->fb = old_fb;
 534 }
 535
 536 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 537                 .prepare_fb = msm_atomic_prepare_fb,
 538                 .cleanup_fb = mdp5_plane_cleanup_fb,
 539                 .atomic_check = mdp5_plane_atomic_check,
 540                 .atomic_update = mdp5_plane_atomic_update,
 541                 .atomic_async_check = mdp5_plane_atomic_async_check,
 542                 .atomic_async_update = mdp5_plane_atomic_async_update,
 543 };
 544
 545 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
 546                                enum mdp5_pipe pipe,
 547                                struct drm_framebuffer *fb)
 548 {
 549         struct msm_kms *kms = &mdp5_kms->base.base;
 550
 551         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 552                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 553                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 554
 555         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 556                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 557                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 558
 559         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 560                         msm_framebuffer_iova(fb, kms->aspace, 0));
 561         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 562                         msm_framebuffer_iova(fb, kms->aspace, 1));
 563         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 564                         msm_framebuffer_iova(fb, kms->aspace, 2));
 565         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 566                         msm_framebuffer_iova(fb, kms->aspace, 3));
 567 }
 568
 569 /* Note: mdp5_plane->pipe_lock must be locked */
 570 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 571 {
 572         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 573                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 574
 575         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 576 }
 577
 578 /* Note: mdp5_plane->pipe_lock must be locked */
 579 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 580                 struct csc_cfg *csc)
 581 {
 582         uint32_t  i, mode = 0; /* RGB, no CSC */
 583         uint32_t *matrix;
 584
 585         if (unlikely(!csc))
 586                 return;
 587
 588         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 589                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 590         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 591                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 592         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 593         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 594
 595         matrix = csc->matrix;
 596         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 597                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 598                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 599         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 600                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 601                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 602         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 603                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 604                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 605         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 606                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 607                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 608         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 609                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 610
 611         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 612                 uint32_t *pre_clamp = csc->pre_clamp;
 613                 uint32_t *post_clamp = csc->post_clamp;
 614
 615                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 616                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 617                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 618
 619                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 620                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 621                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 622
 623                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 624                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 625
 626                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 627                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 628         }
 629 }
 630
 631 #define PHASE_STEP_SHIFT        21
 632 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 633
 634 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 635 {
 636         uint32_t unit;
 637
 638         if (src == 0 || dst == 0)
 639                 return -EINVAL;
 640
 641         /*
 642          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 643          * where 2^21 represents the unity "1" in fixed-point hardware design.
 644          * This leaves 5 bits for the integer part (downscale case):
 645          *      -> maximum downscale ratio = 0b1_1111 = 31
 646          */
 647         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 648                 return -EOVERFLOW;
 649
 650         unit = 1 << PHASE_STEP_SHIFT;
 651         *out_phase = mult_frac(unit, src, dst);
 652
 653         return 0;
 654 }
 655
 656 static int calc_scalex_steps(struct drm_plane *plane,
 657                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 658                 uint32_t phasex_steps[COMP_MAX])
 659 {
 660         const struct drm_format_info *info = drm_format_info(pixel_format);
 661         struct mdp5_kms *mdp5_kms = get_kms(plane);
 662         struct device *dev = mdp5_kms->dev->dev;
 663         uint32_t phasex_step;
 664         int ret;
 665
 666         ret = calc_phase_step(src, dest, &phasex_step);
 667         if (ret) {
 668                 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 669                 return ret;
 670         }
 671
 672         phasex_steps[COMP_0]   = phasex_step;
 673         phasex_steps[COMP_3]   = phasex_step;
 674         phasex_steps[COMP_1_2] = phasex_step / info->hsub;
 675
 676         return 0;
 677 }
 678
 679 static int calc_scaley_steps(struct drm_plane *plane,
 680                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 681                 uint32_t phasey_steps[COMP_MAX])
 682 {
 683         const struct drm_format_info *info = drm_format_info(pixel_format);
 684         struct mdp5_kms *mdp5_kms = get_kms(plane);
 685         struct device *dev = mdp5_kms->dev->dev;
 686         uint32_t phasey_step;
 687         int ret;
 688
 689         ret = calc_phase_step(src, dest, &phasey_step);
 690         if (ret) {
 691                 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 692                 return ret;
 693         }
 694
 695         phasey_steps[COMP_0]   = phasey_step;
 696         phasey_steps[COMP_3]   = phasey_step;
 697         phasey_steps[COMP_1_2] = phasey_step / info->vsub;
 698
 699         return 0;
 700 }
 701
 702 static uint32_t get_scale_config(const struct mdp_format *format,
 703                 uint32_t src, uint32_t dst, bool horz)
 704 {
 705         const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
 706         bool scaling = format->is_yuv ? true : (src != dst);
 707         uint32_t sub;
 708         uint32_t ya_filter, uv_filter;
 709         bool yuv = format->is_yuv;
 710
 711         if (!scaling)
 712                 return 0;
 713
 714         if (yuv) {
 715                 sub = horz ? info->hsub : info->vsub;
 716                 uv_filter = ((src / sub) <= dst) ?
 717                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 718         }
 719         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 720
 721         if (horz)
 722                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 723                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 724                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 725                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 726         else
 727                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 728                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 729                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 730                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 731 }
 732
 733 static void calc_pixel_ext(const struct mdp_format *format,
 734                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 735                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 736                 bool horz)
 737 {
 738         bool scaling = format->is_yuv ? true : (src != dst);
 739         int i;
 740
 741         /*
 742          * Note:
 743          * We assume here that:
 744          *     1. PCMN filter is used for downscale
 745          *     2. bilinear filter is used for upscale
 746          *     3. we are in a single pipe configuration
 747          */
 748
 749         for (i = 0; i < COMP_MAX; i++) {
 750                 pix_ext_edge1[i] = 0;
 751                 pix_ext_edge2[i] = scaling ? 1 : 0;
 752         }
 753 }
 754
 755 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 756         const struct mdp_format *format,
 757         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 758         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 759 {
 760         const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
 761         uint32_t lr, tb, req;
 762         int i;
 763
 764         for (i = 0; i < COMP_MAX; i++) {
 765                 uint32_t roi_w = src_w;
 766                 uint32_t roi_h = src_h;
 767
 768                 if (format->is_yuv && i == COMP_1_2) {
 769                         roi_w /= info->hsub;
 770                         roi_h /= info->vsub;
 771                 }
 772
 773                 lr  = (pe_left[i] >= 0) ?
 774                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 775                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 776
 777                 lr |= (pe_right[i] >= 0) ?
 778                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 779                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 780
 781                 tb  = (pe_top[i] >= 0) ?
 782                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 783                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 784
 785                 tb |= (pe_bottom[i] >= 0) ?
 786                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 787                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 788
 789                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 790                                 pe_left[i] + pe_right[i]);
 791
 792                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 793                                 pe_top[i] + pe_bottom[i]);
 794
 795                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 796                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 797                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 798
 799                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 800                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 801                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 802                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 803                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 804                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 805
 806                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 807                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 808                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 809                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 810                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 811                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 812         }
 813 }
 814
 815 struct pixel_ext {
 816         int left[COMP_MAX];
 817         int right[COMP_MAX];
 818         int top[COMP_MAX];
 819         int bottom[COMP_MAX];
 820 };
 821
 822 struct phase_step {
 823         u32 x[COMP_MAX];
 824         u32 y[COMP_MAX];
 825 };
 826
 827 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
 828                                  struct mdp5_hw_pipe *hwpipe,
 829                                  struct drm_framebuffer *fb,
 830                                  struct phase_step *step,
 831                                  struct pixel_ext *pe,
 832                                  u32 scale_config, u32 hdecm, u32 vdecm,
 833                                  bool hflip, bool vflip,
 834                                  int crtc_x, int crtc_y,
 835                                  unsigned int crtc_w, unsigned int crtc_h,
 836                                  u32 src_img_w, u32 src_img_h,
 837                                  u32 src_x, u32 src_y,
 838                                  u32 src_w, u32 src_h)
 839 {
 840         enum mdp5_pipe pipe = hwpipe->pipe;
 841         bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 842         const struct mdp_format *format =
 843                         to_mdp_format(msm_framebuffer_format(fb));
 844
 845         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 846                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
 847                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
 848
 849         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 850                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 851                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 852
 853         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 854                         MDP5_PIPE_SRC_XY_X(src_x) |
 855                         MDP5_PIPE_SRC_XY_Y(src_y));
 856
 857         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 858                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 859                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 860
 861         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 862                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 863                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 864
 865         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 866                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 867                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 868                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 869                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 870                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 871                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 872                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 873                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 874                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 875                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 876
 877         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 878                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 879                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 880                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 881                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 882
 883         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 884                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 885                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 886                         COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 887                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 888
 889         /* not using secure mode: */
 890         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 891
 892         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 893                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 894                                 src_w, pe->left, pe->right,
 895                                 src_h, pe->top, pe->bottom);
 896
 897         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 898                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 899                                 step->x[COMP_0]);
 900                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 901                                 step->y[COMP_0]);
 902                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 903                                 step->x[COMP_1_2]);
 904                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 905                                 step->y[COMP_1_2]);
 906                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 907                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 908                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 909                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
 910                            scale_config);
 911         }
 912
 913         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 914                 if (MDP_FORMAT_IS_YUV(format))
 915                         csc_enable(mdp5_kms, pipe,
 916                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 917                 else
 918                         csc_disable(mdp5_kms, pipe);
 919         }
 920
 921         set_scanout_locked(mdp5_kms, pipe, fb);
 922 }
 923
 924 static int mdp5_plane_mode_set(struct drm_plane *plane,
 925                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 926                 struct drm_rect *src, struct drm_rect *dest)
 927 {
 928         struct drm_plane_state *pstate = plane->state;
 929         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 930         struct mdp5_kms *mdp5_kms = get_kms(plane);
 931         enum mdp5_pipe pipe = hwpipe->pipe;
 932         struct mdp5_hw_pipe *right_hwpipe;
 933         const struct mdp_format *format;
 934         uint32_t nplanes, config = 0;
 935         struct phase_step step = { { 0 } };
 936         struct pixel_ext pe = { { 0 } };
 937         uint32_t hdecm = 0, vdecm = 0;
 938         uint32_t pix_format;
 939         unsigned int rotation;
 940         bool vflip, hflip;
 941         int crtc_x, crtc_y;
 942         unsigned int crtc_w, crtc_h;
 943         uint32_t src_x, src_y;
 944         uint32_t src_w, src_h;
 945         uint32_t src_img_w, src_img_h;
 946         int ret;
 947
 948         nplanes = fb->format->num_planes;
 949
 950         /* bad formats should already be rejected: */
 951         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 952                 return -EINVAL;
 953
 954         format = to_mdp_format(msm_framebuffer_format(fb));
 955         pix_format = format->base.pixel_format;
 956
 957         src_x = src->x1;
 958         src_y = src->y1;
 959         src_w = drm_rect_width(src);
 960         src_h = drm_rect_height(src);
 961
 962         crtc_x = dest->x1;
 963         crtc_y = dest->y1;
 964         crtc_w = drm_rect_width(dest);
 965         crtc_h = drm_rect_height(dest);
 966
 967         /* src values are in Q16 fixed point, convert to integer: */
 968         src_x = src_x >> 16;
 969         src_y = src_y >> 16;
 970         src_w = src_w >> 16;
 971         src_h = src_h >> 16;
 972
 973         src_img_w = min(fb->width, src_w);
 974         src_img_h = min(fb->height, src_h);
 975
 976         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
 977                         fb->base.id, src_x, src_y, src_w, src_h,
 978                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 979
 980         right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
 981         if (right_hwpipe) {
 982                 /*
 983                  * if the plane comprises of 2 hw pipes, assume that the width
 984                  * is split equally across them. The only parameters that varies
 985                  * between the 2 pipes are src_x and crtc_x
 986                  */
 987                 crtc_w /= 2;
 988                 src_w /= 2;
 989                 src_img_w /= 2;
 990         }
 991
 992         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
 993         if (ret)
 994                 return ret;
 995
 996         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
 997         if (ret)
 998                 return ret;
 999
1000         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
1001                 calc_pixel_ext(format, src_w, crtc_w, step.x,
1002                                pe.left, pe.right, true);
1003                 calc_pixel_ext(format, src_h, crtc_h, step.y,
1004                                pe.top, pe.bottom, false);
1005         }
1006
1007         /* TODO calc hdecm, vdecm */
1008
1009         /* SCALE is used to both scale and up-sample chroma components */
1010         config |= get_scale_config(format, src_w, crtc_w, true);
1011         config |= get_scale_config(format, src_h, crtc_h, false);
1012         DBG("scale config = %x", config);
1013
1014         rotation = drm_rotation_simplify(pstate->rotation,
1015                                          DRM_MODE_ROTATE_0 |
1016                                          DRM_MODE_REFLECT_X |
1017                                          DRM_MODE_REFLECT_Y);
1018         hflip = !!(rotation & DRM_MODE_REFLECT_X);
1019         vflip = !!(rotation & DRM_MODE_REFLECT_Y);
1020
1021         mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
1022                              config, hdecm, vdecm, hflip, vflip,
1023                              crtc_x, crtc_y, crtc_w, crtc_h,
1024                              src_img_w, src_img_h,
1025                              src_x, src_y, src_w, src_h);
1026         if (right_hwpipe)
1027                 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
1028                                      config, hdecm, vdecm, hflip, vflip,
1029                                      crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
1030                                      src_img_w, src_img_h,
1031                                      src_x + src_w, src_y, src_w, src_h);
1032
1033         return ret;
1034 }
1035
1036 /*
1037  * Use this func and the one below only after the atomic state has been
1038  * successfully swapped
1039  */
1040 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
1041 {
1042         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1043
1044         if (WARN_ON(!pstate->hwpipe))
1045                 return SSPP_NONE;
1046
1047         return pstate->hwpipe->pipe;
1048 }
1049
1050 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
1051 {
1052         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1053
1054         if (!pstate->r_hwpipe)
1055                 return SSPP_NONE;
1056
1057         return pstate->r_hwpipe->pipe;
1058 }
1059
1060 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
1061 {
1062         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
1063         u32 mask;
1064
1065         if (WARN_ON(!pstate->hwpipe))
1066                 return 0;
1067
1068         mask = pstate->hwpipe->flush_mask;
1069
1070         if (pstate->r_hwpipe)
1071                 mask |= pstate->r_hwpipe->flush_mask;
1072
1073         return mask;
1074 }
1075
1076 /* initialize plane */
1077 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1078                                   enum drm_plane_type type)
1079 {
1080         struct drm_plane *plane = NULL;
1081         struct mdp5_plane *mdp5_plane;
1082         int ret;
1083
1084         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
1085         if (!mdp5_plane) {
1086                 ret = -ENOMEM;
1087                 goto fail;
1088         }
1089
1090         plane = &mdp5_plane->base;
1091
1092         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
1093                 ARRAY_SIZE(mdp5_plane->formats), false);
1094
1095         ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
1096                         mdp5_plane->formats, mdp5_plane->nformats,
1097                         NULL, type, NULL);
1098         if (ret)
1099                 goto fail;
1100
1101         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1102
1103         mdp5_plane_install_properties(plane, &plane->base);
1104
1105         drm_plane_enable_fb_damage_clips(plane);
1106
1107         return plane;
1108
1109 fail:
1110         if (plane)
1111                 mdp5_plane_destroy(plane);
1112
1113         return ERR_PTR(ret);
1114 }