1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
9 struct mdp5_cfg_handler {
11 struct mdp5_cfg config;
14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
15 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
17 static const struct mdp5_cfg_hw msm8x74v1_config = {
28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
41 .caps = MDP_PIPE_CAP_HFLIP |
49 .base = { 0x01d00, 0x02100, 0x02500 },
50 .caps = MDP_PIPE_CAP_HFLIP |
57 .base = { 0x02900, 0x02d00 },
58 .caps = MDP_PIPE_CAP_HFLIP |
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
66 { .id = 0, .pp = 0, .dspp = 0,
67 .caps = MDP_LM_CAP_DISPLAY, },
68 { .id = 1, .pp = 1, .dspp = 1,
69 .caps = MDP_LM_CAP_DISPLAY, },
70 { .id = 2, .pp = 2, .dspp = 2,
71 .caps = MDP_LM_CAP_DISPLAY, },
72 { .id = 3, .pp = -1, .dspp = -1,
73 .caps = MDP_LM_CAP_WB },
74 { .id = 4, .pp = -1, .dspp = -1,
75 .caps = MDP_LM_CAP_WB },
83 .base = { 0x04500, 0x04900, 0x04d00 },
87 .base = { 0x21a00, 0x21b00, 0x21c00 },
90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
101 static const struct mdp5_cfg_hw msm8x74v2_config = {
105 .caps = MDP_CAP_SMP |
112 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
113 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
114 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
119 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
120 .flush_hw_mask = 0x0003ffff,
124 .base = { 0x01100, 0x01500, 0x01900 },
125 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
126 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
127 MDP_PIPE_CAP_DECIMATION,
131 .base = { 0x01d00, 0x02100, 0x02500 },
132 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
133 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
137 .base = { 0x02900, 0x02d00 },
138 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
142 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
144 { .id = 0, .pp = 0, .dspp = 0,
145 .caps = MDP_LM_CAP_DISPLAY, },
146 { .id = 1, .pp = 1, .dspp = 1,
147 .caps = MDP_LM_CAP_DISPLAY, },
148 { .id = 2, .pp = 2, .dspp = 2,
149 .caps = MDP_LM_CAP_DISPLAY, },
150 { .id = 3, .pp = -1, .dspp = -1,
151 .caps = MDP_LM_CAP_WB, },
152 { .id = 4, .pp = -1, .dspp = -1,
153 .caps = MDP_LM_CAP_WB, },
157 .max_height = 0xFFFF,
161 .base = { 0x04500, 0x04900, 0x04d00 },
165 .base = { 0x13000, 0x13200 },
169 .base = { 0x12c00, 0x12d00, 0x12e00 },
172 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
180 .max_clk = 320000000,
183 static const struct mdp5_cfg_hw apq8084_config = {
187 .caps = MDP_CAP_SMP |
195 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
196 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
197 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
198 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
199 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
201 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
203 /* Two SMP blocks are statically tied to RGB pipes: */
204 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
209 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
210 .flush_hw_mask = 0x003fffff,
214 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
215 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
216 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
217 MDP_PIPE_CAP_DECIMATION,
221 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
222 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
223 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
227 .base = { 0x03100, 0x03500 },
228 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
232 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
234 { .id = 0, .pp = 0, .dspp = 0,
235 .caps = MDP_LM_CAP_DISPLAY |
237 { .id = 1, .pp = 1, .dspp = 1,
238 .caps = MDP_LM_CAP_DISPLAY, },
239 { .id = 2, .pp = 2, .dspp = 2,
240 .caps = MDP_LM_CAP_DISPLAY |
242 { .id = 3, .pp = -1, .dspp = -1,
243 .caps = MDP_LM_CAP_WB, },
244 { .id = 4, .pp = -1, .dspp = -1,
245 .caps = MDP_LM_CAP_WB, },
246 { .id = 5, .pp = 3, .dspp = 3,
247 .caps = MDP_LM_CAP_DISPLAY, },
251 .max_height = 0xFFFF,
255 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
260 .base = { 0x13400, 0x13600, 0x13800 },
264 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
267 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
275 .max_clk = 320000000,
278 static const struct mdp5_cfg_hw msm8x16_config = {
283 .caps = MDP_CAP_SMP |
290 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
291 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
296 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
297 .flush_hw_mask = 0x4003ffff,
302 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
303 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
304 MDP_PIPE_CAP_DECIMATION,
308 .base = { 0x14000, 0x16000 },
309 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
310 MDP_PIPE_CAP_DECIMATION,
315 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
318 .count = 2, /* LM0 and LM3 */
319 .base = { 0x44000, 0x47000 },
321 { .id = 0, .pp = 0, .dspp = 0,
322 .caps = MDP_LM_CAP_DISPLAY, },
323 { .id = 3, .pp = -1, .dspp = -1,
324 .caps = MDP_LM_CAP_WB },
328 .max_height = 0xFFFF,
336 .base = { 0x00000, 0x6a800 },
342 .max_clk = 320000000,
345 static const struct mdp5_cfg_hw msm8x36_config = {
350 .caps = MDP_CAP_SMP |
357 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
358 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
363 .base = { 0x01000, 0x01200, 0x01400 },
364 .flush_hw_mask = 0x4003ffff,
369 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
370 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
371 MDP_PIPE_CAP_DECIMATION,
375 .base = { 0x14000, 0x16000 },
376 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
377 MDP_PIPE_CAP_DECIMATION,
382 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
386 .base = { 0x44000, 0x47000 },
388 { .id = 0, .pp = 0, .dspp = 0,
389 .caps = MDP_LM_CAP_DISPLAY, },
390 { .id = 1, .pp = -1, .dspp = -1,
391 .caps = MDP_LM_CAP_WB, },
395 .max_height = 0xFFFF,
410 .base = { 0x00000, 0x6a800, 0x6b000 },
417 .max_clk = 366670000,
420 static const struct mdp5_cfg_hw msm8x94_config = {
424 .caps = MDP_CAP_SMP |
432 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
433 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
434 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
435 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
436 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
438 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
440 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
441 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
446 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
447 .flush_hw_mask = 0xf0ffffff,
451 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
452 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
453 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
454 MDP_PIPE_CAP_DECIMATION,
458 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
459 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
460 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
464 .base = { 0x24000, 0x26000 },
465 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
469 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
471 { .id = 0, .pp = 0, .dspp = 0,
472 .caps = MDP_LM_CAP_DISPLAY |
474 { .id = 1, .pp = 1, .dspp = 1,
475 .caps = MDP_LM_CAP_DISPLAY, },
476 { .id = 2, .pp = 2, .dspp = 2,
477 .caps = MDP_LM_CAP_DISPLAY |
479 { .id = 3, .pp = -1, .dspp = -1,
480 .caps = MDP_LM_CAP_WB, },
481 { .id = 4, .pp = -1, .dspp = -1,
482 .caps = MDP_LM_CAP_WB, },
483 { .id = 5, .pp = 3, .dspp = 3,
484 .caps = MDP_LM_CAP_DISPLAY, },
488 .max_height = 0xFFFF,
492 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
497 .base = { 0x78000, 0x78800, 0x79000 },
501 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
504 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
512 .max_clk = 400000000,
515 static const struct mdp5_cfg_hw msm8x96_config = {
519 .caps = MDP_CAP_DSC |
526 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
527 .flush_hw_mask = 0xf4ffffff,
531 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
532 .caps = MDP_PIPE_CAP_HFLIP |
536 MDP_PIPE_CAP_DECIMATION |
537 MDP_PIPE_CAP_SW_PIX_EXT |
542 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
543 .caps = MDP_PIPE_CAP_HFLIP |
546 MDP_PIPE_CAP_DECIMATION |
547 MDP_PIPE_CAP_SW_PIX_EXT |
552 .base = { 0x24000, 0x26000 },
553 .caps = MDP_PIPE_CAP_HFLIP |
555 MDP_PIPE_CAP_SW_PIX_EXT |
560 .base = { 0x34000, 0x36000 },
561 .caps = MDP_PIPE_CAP_HFLIP |
563 MDP_PIPE_CAP_SW_PIX_EXT |
564 MDP_PIPE_CAP_CURSOR |
570 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
572 { .id = 0, .pp = 0, .dspp = 0,
573 .caps = MDP_LM_CAP_DISPLAY |
575 { .id = 1, .pp = 1, .dspp = 1,
576 .caps = MDP_LM_CAP_DISPLAY, },
577 { .id = 2, .pp = 2, .dspp = -1,
578 .caps = MDP_LM_CAP_DISPLAY |
580 { .id = 3, .pp = -1, .dspp = -1,
581 .caps = MDP_LM_CAP_WB, },
582 { .id = 4, .pp = -1, .dspp = -1,
583 .caps = MDP_LM_CAP_WB, },
584 { .id = 5, .pp = 3, .dspp = -1,
585 .caps = MDP_LM_CAP_DISPLAY, },
589 .max_height = 0xFFFF,
593 .base = { 0x54000, 0x56000 },
597 .base = { 0x78000, 0x78800, 0x79000 },
601 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
609 .base = { 0x80000, 0x80400 },
612 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
620 .max_clk = 412500000,
623 const struct mdp5_cfg_hw msm8x76_config = {
627 .caps = MDP_CAP_SMP |
634 .base = { 0x01000, 0x01200, 0x01400 },
635 .flush_hw_mask = 0xffffffff,
641 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
643 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
648 .base = { 0x04000, 0x06000 },
649 .caps = MDP_PIPE_CAP_HFLIP |
653 MDP_PIPE_CAP_DECIMATION |
654 MDP_PIPE_CAP_SW_PIX_EXT |
659 .base = { 0x14000, 0x16000 },
660 .caps = MDP_PIPE_CAP_HFLIP |
662 MDP_PIPE_CAP_DECIMATION |
663 MDP_PIPE_CAP_SW_PIX_EXT |
669 .caps = MDP_PIPE_CAP_HFLIP |
671 MDP_PIPE_CAP_SW_PIX_EXT |
677 .caps = MDP_PIPE_CAP_HFLIP |
679 MDP_PIPE_CAP_SW_PIX_EXT |
680 MDP_PIPE_CAP_CURSOR |
685 .base = { 0x44000, 0x45000 },
687 { .id = 0, .pp = 0, .dspp = 0,
688 .caps = MDP_LM_CAP_DISPLAY, },
689 { .id = 1, .pp = -1, .dspp = -1,
690 .caps = MDP_LM_CAP_WB },
694 .max_height = 0xFFFF,
703 .base = { 0x70000, 0x70800, 0x72000 },
707 .base = { 0x80000, 0x80400 },
710 .base = { 0x6a000, 0x6a800, 0x6b000 },
717 .max_clk = 360000000,
720 static const struct mdp5_cfg_hw msm8917_config = {
728 .base = { 0x01000, 0x01200, 0x01400 },
729 .flush_hw_mask = 0xffffffff,
734 .caps = MDP_PIPE_CAP_HFLIP |
738 MDP_PIPE_CAP_DECIMATION |
739 MDP_PIPE_CAP_SW_PIX_EXT |
744 .base = { 0x14000, 0x16000 },
745 .caps = MDP_PIPE_CAP_HFLIP |
747 MDP_PIPE_CAP_DECIMATION |
748 MDP_PIPE_CAP_SW_PIX_EXT |
754 .caps = MDP_PIPE_CAP_HFLIP |
756 MDP_PIPE_CAP_SW_PIX_EXT |
762 .caps = MDP_PIPE_CAP_HFLIP |
764 MDP_PIPE_CAP_SW_PIX_EXT |
765 MDP_PIPE_CAP_CURSOR |
771 .base = { 0x44000, 0x45000 },
773 { .id = 0, .pp = 0, .dspp = 0,
774 .caps = MDP_LM_CAP_DISPLAY, },
775 { .id = 1, .pp = -1, .dspp = -1,
776 .caps = MDP_LM_CAP_WB },
780 .max_height = 0xFFFF,
796 .base = { 0x6a000, 0x6a800 },
802 .max_clk = 320000000,
805 static const struct mdp5_cfg_hw msm8998_config = {
809 .caps = MDP_CAP_DSC |
816 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
817 .flush_hw_mask = 0xf7ffffff,
821 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
822 .caps = MDP_PIPE_CAP_HFLIP |
826 MDP_PIPE_CAP_DECIMATION |
827 MDP_PIPE_CAP_SW_PIX_EXT |
832 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
833 .caps = MDP_PIPE_CAP_HFLIP |
836 MDP_PIPE_CAP_DECIMATION |
837 MDP_PIPE_CAP_SW_PIX_EXT |
841 .count = 2, /* driver supports max of 2 currently */
842 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
843 .caps = MDP_PIPE_CAP_HFLIP |
845 MDP_PIPE_CAP_SW_PIX_EXT |
850 .base = { 0x34000, 0x36000 },
851 .caps = MDP_PIPE_CAP_HFLIP |
853 MDP_PIPE_CAP_SW_PIX_EXT |
854 MDP_PIPE_CAP_CURSOR |
860 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
862 { .id = 0, .pp = 0, .dspp = 0,
863 .caps = MDP_LM_CAP_DISPLAY |
865 { .id = 1, .pp = 1, .dspp = 1,
866 .caps = MDP_LM_CAP_DISPLAY, },
867 { .id = 2, .pp = 2, .dspp = -1,
868 .caps = MDP_LM_CAP_DISPLAY |
870 { .id = 3, .pp = -1, .dspp = -1,
871 .caps = MDP_LM_CAP_WB, },
872 { .id = 4, .pp = -1, .dspp = -1,
873 .caps = MDP_LM_CAP_WB, },
874 { .id = 5, .pp = 3, .dspp = -1,
875 .caps = MDP_LM_CAP_DISPLAY, },
879 .max_height = 0xFFFF,
883 .base = { 0x54000, 0x56000 },
887 .base = { 0x78000, 0x78800, 0x79000 },
891 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
899 .base = { 0x80000, 0x80400 },
902 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
910 .max_clk = 412500000,
913 static const struct mdp5_cfg_hw sdm630_config = {
917 .caps = MDP_CAP_CDM |
923 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
924 .flush_hw_mask = 0xf4ffffff,
929 .caps = MDP_PIPE_CAP_HFLIP |
933 MDP_PIPE_CAP_DECIMATION |
934 MDP_PIPE_CAP_SW_PIX_EXT |
939 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
940 .caps = MDP_PIPE_CAP_HFLIP |
943 MDP_PIPE_CAP_DECIMATION |
944 MDP_PIPE_CAP_SW_PIX_EXT |
948 .count = 2, /* driver supports max of 2 currently */
949 .base = { 0x24000, 0x26000, 0x28000 },
950 .caps = MDP_PIPE_CAP_HFLIP |
952 MDP_PIPE_CAP_SW_PIX_EXT |
958 .caps = MDP_PIPE_CAP_HFLIP |
960 MDP_PIPE_CAP_SW_PIX_EXT |
961 MDP_PIPE_CAP_CURSOR |
967 .base = { 0x44000, 0x46000 },
969 { .id = 0, .pp = 0, .dspp = 0,
970 .caps = MDP_LM_CAP_DISPLAY |
972 { .id = 1, .pp = 1, .dspp = -1,
973 .caps = MDP_LM_CAP_WB, },
977 .max_height = 0xFFFF,
985 .base = { 0x78000, 0x78800 },
989 .base = { 0x70000, 0x71000, 0x72000 },
996 .base = { 0x6a000, 0x6a800 },
1002 .max_clk = 412500000,
1005 static const struct mdp5_cfg_hw sdm660_config = {
1009 .caps = MDP_CAP_DSC |
1016 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1017 .flush_hw_mask = 0xf4ffffff,
1021 .base = { 0x04000, 0x6000 },
1022 .caps = MDP_PIPE_CAP_HFLIP |
1023 MDP_PIPE_CAP_VFLIP |
1024 MDP_PIPE_CAP_SCALE |
1026 MDP_PIPE_CAP_DECIMATION |
1027 MDP_PIPE_CAP_SW_PIX_EXT |
1032 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1033 .caps = MDP_PIPE_CAP_HFLIP |
1034 MDP_PIPE_CAP_VFLIP |
1035 MDP_PIPE_CAP_SCALE |
1036 MDP_PIPE_CAP_DECIMATION |
1037 MDP_PIPE_CAP_SW_PIX_EXT |
1041 .count = 2, /* driver supports max of 2 currently */
1042 .base = { 0x24000, 0x26000, 0x28000 },
1043 .caps = MDP_PIPE_CAP_HFLIP |
1044 MDP_PIPE_CAP_VFLIP |
1045 MDP_PIPE_CAP_SW_PIX_EXT |
1050 .base = { 0x34000 },
1051 .caps = MDP_PIPE_CAP_HFLIP |
1052 MDP_PIPE_CAP_VFLIP |
1053 MDP_PIPE_CAP_SW_PIX_EXT |
1054 MDP_PIPE_CAP_CURSOR |
1060 .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1062 { .id = 0, .pp = 0, .dspp = 0,
1063 .caps = MDP_LM_CAP_DISPLAY |
1065 { .id = 1, .pp = 1, .dspp = 1,
1066 .caps = MDP_LM_CAP_DISPLAY, },
1067 { .id = 2, .pp = 2, .dspp = -1,
1068 .caps = MDP_LM_CAP_DISPLAY |
1070 { .id = 3, .pp = 3, .dspp = -1,
1071 .caps = MDP_LM_CAP_WB, },
1075 .max_height = 0xFFFF,
1079 .base = { 0x54000, 0x56000 },
1083 .base = { 0x78000, 0x78800 },
1087 .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1091 .base = { 0x79200 },
1095 .base = { 0x80000, 0x80400 },
1098 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1100 [0] = INTF_DISABLED,
1106 .max_clk = 412500000,
1109 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1110 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
1111 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
1112 { .revision = 3, .config = { .hw = &apq8084_config } },
1113 { .revision = 6, .config = { .hw = &msm8x16_config } },
1114 { .revision = 8, .config = { .hw = &msm8x36_config } },
1115 { .revision = 9, .config = { .hw = &msm8x94_config } },
1116 { .revision = 7, .config = { .hw = &msm8x96_config } },
1117 { .revision = 11, .config = { .hw = &msm8x76_config } },
1118 { .revision = 15, .config = { .hw = &msm8917_config } },
1121 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1122 { .revision = 0, .config = { .hw = &msm8998_config } },
1123 { .revision = 2, .config = { .hw = &sdm660_config } },
1124 { .revision = 3, .config = { .hw = &sdm630_config } },
1127 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
1129 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1131 return cfg_handler->config.hw;
1134 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1136 return &cfg_handler->config;
1139 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1141 return cfg_handler->revision;
1144 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
1149 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1150 uint32_t major, uint32_t minor)
1152 struct drm_device *dev = mdp5_kms->dev;
1153 struct platform_device *pdev = to_platform_device(dev->dev);
1154 struct mdp5_cfg_handler *cfg_handler;
1155 const struct mdp5_cfg_handler *cfg_handlers;
1156 struct mdp5_cfg_platform *pconfig;
1157 int i, ret = 0, num_handlers;
1159 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
1160 if (unlikely(!cfg_handler)) {
1167 cfg_handlers = cfg_handlers_v1;
1168 num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1171 cfg_handlers = cfg_handlers_v3;
1172 num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1175 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1181 /* only after mdp5_cfg global pointer's init can we access the hw */
1182 for (i = 0; i < num_handlers; i++) {
1183 if (cfg_handlers[i].revision != minor)
1185 mdp5_cfg = cfg_handlers[i].config.hw;
1189 if (unlikely(!mdp5_cfg)) {
1190 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1196 cfg_handler->revision = minor;
1197 cfg_handler->config.hw = mdp5_cfg;
1199 pconfig = mdp5_get_config(pdev);
1200 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
1202 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1208 mdp5_cfg_destroy(cfg_handler);
1210 return ERR_PTR(ret);
1213 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
1215 static struct mdp5_cfg_platform config = {};
1217 config.iommu = iommu_domain_alloc(&platform_bus_type);