drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include "mdp5_kms.h"
   7 #include "mdp5_cfg.h"
   8
   9 struct mdp5_cfg_handler {
  10         int revision;
  11         struct mdp5_cfg config;
  12 };
  13
  14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
  15 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
  16
  17 static const struct mdp5_cfg_hw msm8x74v1_config = {
  18         .name = "msm8x74v1",
  19         .mdp = {
  20                 .count = 1,
  21                 .caps = MDP_CAP_SMP |
  22                         0,
  23         },
  24         .smp = {
  25                 .mmb_count = 22,
  26                 .mmb_size = 4096,
  27                 .clients = {
  28                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
  29                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
  30                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
  31                 },
  32         },
  33         .ctl = {
  34                 .count = 5,
  35                 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
  36                 .flush_hw_mask = 0x0003ffff,
  37         },
  38         .pipe_vig = {
  39                 .count = 3,
  40                 .base = { 0x01100, 0x01500, 0x01900 },
  41                 .caps = MDP_PIPE_CAP_HFLIP |
  42                         MDP_PIPE_CAP_VFLIP |
  43                         MDP_PIPE_CAP_SCALE |
  44                         MDP_PIPE_CAP_CSC   |
  45                         0,
  46         },
  47         .pipe_rgb = {
  48                 .count = 3,
  49                 .base = { 0x01d00, 0x02100, 0x02500 },
  50                 .caps = MDP_PIPE_CAP_HFLIP |
  51                         MDP_PIPE_CAP_VFLIP |
  52                         MDP_PIPE_CAP_SCALE |
  53                         0,
  54         },
  55         .pipe_dma = {
  56                 .count = 2,
  57                 .base = { 0x02900, 0x02d00 },
  58                 .caps = MDP_PIPE_CAP_HFLIP |
  59                         MDP_PIPE_CAP_VFLIP |
  60                         0,
  61         },
  62         .lm = {
  63                 .count = 5,
  64                 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
  65                 .instances = {
  66                                 { .id = 0, .pp = 0, .dspp = 0,
  67                                   .caps = MDP_LM_CAP_DISPLAY, },
  68                                 { .id = 1, .pp = 1, .dspp = 1,
  69                                   .caps = MDP_LM_CAP_DISPLAY, },
  70                                 { .id = 2, .pp = 2, .dspp = 2,
  71                                   .caps = MDP_LM_CAP_DISPLAY, },
  72                                 { .id = 3, .pp = -1, .dspp = -1,
  73                                   .caps = MDP_LM_CAP_WB },
  74                                 { .id = 4, .pp = -1, .dspp = -1,
  75                                   .caps = MDP_LM_CAP_WB },
  76                              },
  77                 .nb_stages = 5,
  78                 .max_width = 2048,
  79                 .max_height = 0xFFFF,
  80         },
  81         .dspp = {
  82                 .count = 3,
  83                 .base = { 0x04500, 0x04900, 0x04d00 },
  84         },
  85         .pp = {
  86                 .count = 3,
  87                 .base = { 0x21a00, 0x21b00, 0x21c00 },
  88         },
  89         .intf = {
  90                 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
  91                 .connect = {
  92                         [0] = INTF_eDP,
  93                         [1] = INTF_DSI,
  94                         [2] = INTF_DSI,
  95                         [3] = INTF_HDMI,
  96                 },
  97         },
  98         .perf = {
  99                 .ab_inefficiency = 200,
 100                 .ib_inefficiency = 120,
 101                 .clk_inefficiency = 125
 102         },
 103         .max_clk = 200000000,
 104 };
 105
 106 static const struct mdp5_cfg_hw msm8x74v2_config = {
 107         .name = "msm8x74",
 108         .mdp = {
 109                 .count = 1,
 110                 .caps = MDP_CAP_SMP |
 111                         0,
 112         },
 113         .smp = {
 114                 .mmb_count = 22,
 115                 .mmb_size = 4096,
 116                 .clients = {
 117                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
 118                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 119                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
 120                 },
 121         },
 122         .ctl = {
 123                 .count = 5,
 124                 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
 125                 .flush_hw_mask = 0x0003ffff,
 126         },
 127         .pipe_vig = {
 128                 .count = 3,
 129                 .base = { 0x01100, 0x01500, 0x01900 },
 130                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 131                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 132                                 MDP_PIPE_CAP_DECIMATION,
 133         },
 134         .pipe_rgb = {
 135                 .count = 3,
 136                 .base = { 0x01d00, 0x02100, 0x02500 },
 137                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 138                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 139         },
 140         .pipe_dma = {
 141                 .count = 2,
 142                 .base = { 0x02900, 0x02d00 },
 143                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 144         },
 145         .lm = {
 146                 .count = 5,
 147                 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
 148                 .instances = {
 149                                 { .id = 0, .pp = 0, .dspp = 0,
 150                                   .caps = MDP_LM_CAP_DISPLAY, },
 151                                 { .id = 1, .pp = 1, .dspp = 1,
 152                                   .caps = MDP_LM_CAP_DISPLAY, },
 153                                 { .id = 2, .pp = 2, .dspp = 2,
 154                                   .caps = MDP_LM_CAP_DISPLAY, },
 155                                 { .id = 3, .pp = -1, .dspp = -1,
 156                                   .caps = MDP_LM_CAP_WB, },
 157                                 { .id = 4, .pp = -1, .dspp = -1,
 158                                   .caps = MDP_LM_CAP_WB, },
 159                              },
 160                 .nb_stages = 5,
 161                 .max_width = 2048,
 162                 .max_height = 0xFFFF,
 163         },
 164         .dspp = {
 165                 .count = 3,
 166                 .base = { 0x04500, 0x04900, 0x04d00 },
 167         },
 168         .ad = {
 169                 .count = 2,
 170                 .base = { 0x13000, 0x13200 },
 171         },
 172         .pp = {
 173                 .count = 3,
 174                 .base = { 0x12c00, 0x12d00, 0x12e00 },
 175         },
 176         .intf = {
 177                 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
 178                 .connect = {
 179                         [0] = INTF_eDP,
 180                         [1] = INTF_DSI,
 181                         [2] = INTF_DSI,
 182                         [3] = INTF_HDMI,
 183                 },
 184         },
 185         .perf = {
 186                 .ab_inefficiency = 200,
 187                 .ib_inefficiency = 120,
 188                 .clk_inefficiency = 125
 189         },
 190         .max_clk = 320000000,
 191 };
 192
 193 static const struct mdp5_cfg_hw apq8084_config = {
 194         .name = "apq8084",
 195         .mdp = {
 196                 .count = 1,
 197                 .caps = MDP_CAP_SMP |
 198                         MDP_CAP_SRC_SPLIT |
 199                         0,
 200         },
 201         .smp = {
 202                 .mmb_count = 44,
 203                 .mmb_size = 8192,
 204                 .clients = {
 205                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
 206                         [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
 207                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 208                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 209                         [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 210                 },
 211                 .reserved_state[0] = GENMASK(7, 0),     /* first 8 MMBs */
 212                 .reserved = {
 213                         /* Two SMP blocks are statically tied to RGB pipes: */
 214                         [16] = 2, [17] = 2, [18] = 2, [22] = 2,
 215                 },
 216         },
 217         .ctl = {
 218                 .count = 5,
 219                 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
 220                 .flush_hw_mask = 0x003fffff,
 221         },
 222         .pipe_vig = {
 223                 .count = 4,
 224                 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
 225                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 226                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 227                                 MDP_PIPE_CAP_DECIMATION,
 228         },
 229         .pipe_rgb = {
 230                 .count = 4,
 231                 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
 232                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 233                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 234         },
 235         .pipe_dma = {
 236                 .count = 2,
 237                 .base = { 0x03100, 0x03500 },
 238                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 239         },
 240         .lm = {
 241                 .count = 6,
 242                 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
 243                 .instances = {
 244                                 { .id = 0, .pp = 0, .dspp = 0,
 245                                   .caps = MDP_LM_CAP_DISPLAY |
 246                                           MDP_LM_CAP_PAIR, },
 247                                 { .id = 1, .pp = 1, .dspp = 1,
 248                                   .caps = MDP_LM_CAP_DISPLAY, },
 249                                 { .id = 2, .pp = 2, .dspp = 2,
 250                                   .caps = MDP_LM_CAP_DISPLAY |
 251                                           MDP_LM_CAP_PAIR, },
 252                                 { .id = 3, .pp = -1, .dspp = -1,
 253                                   .caps = MDP_LM_CAP_WB, },
 254                                 { .id = 4, .pp = -1, .dspp = -1,
 255                                   .caps = MDP_LM_CAP_WB, },
 256                                 { .id = 5, .pp = 3, .dspp = 3,
 257                                   .caps = MDP_LM_CAP_DISPLAY, },
 258                              },
 259                 .nb_stages = 5,
 260                 .max_width = 2048,
 261                 .max_height = 0xFFFF,
 262         },
 263         .dspp = {
 264                 .count = 4,
 265                 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
 266
 267         },
 268         .ad = {
 269                 .count = 3,
 270                 .base = { 0x13400, 0x13600, 0x13800 },
 271         },
 272         .pp = {
 273                 .count = 4,
 274                 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
 275         },
 276         .intf = {
 277                 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
 278                 .connect = {
 279                         [0] = INTF_eDP,
 280                         [1] = INTF_DSI,
 281                         [2] = INTF_DSI,
 282                         [3] = INTF_HDMI,
 283                 },
 284         },
 285         .perf = {
 286                 .ab_inefficiency = 200,
 287                 .ib_inefficiency = 120,
 288                 .clk_inefficiency = 105
 289         },
 290         .max_clk = 320000000,
 291 };
 292
 293 static const struct mdp5_cfg_hw msm8x16_config = {
 294         .name = "msm8x16",
 295         .mdp = {
 296                 .count = 1,
 297                 .base = { 0x0 },
 298                 .caps = MDP_CAP_SMP |
 299                         0,
 300         },
 301         .smp = {
 302                 .mmb_count = 8,
 303                 .mmb_size = 8192,
 304                 .clients = {
 305                         [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
 306                         [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 307                 },
 308         },
 309         .ctl = {
 310                 .count = 5,
 311                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 312                 .flush_hw_mask = 0x4003ffff,
 313         },
 314         .pipe_vig = {
 315                 .count = 1,
 316                 .base = { 0x04000 },
 317                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 318                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 319                                 MDP_PIPE_CAP_DECIMATION,
 320         },
 321         .pipe_rgb = {
 322                 .count = 2,
 323                 .base = { 0x14000, 0x16000 },
 324                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 325                                 MDP_PIPE_CAP_DECIMATION,
 326         },
 327         .pipe_dma = {
 328                 .count = 1,
 329                 .base = { 0x24000 },
 330                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 331         },
 332         .lm = {
 333                 .count = 2, /* LM0 and LM3 */
 334                 .base = { 0x44000, 0x47000 },
 335                 .instances = {
 336                                 { .id = 0, .pp = 0, .dspp = 0,
 337                                   .caps = MDP_LM_CAP_DISPLAY, },
 338                                 { .id = 3, .pp = -1, .dspp = -1,
 339                                   .caps = MDP_LM_CAP_WB },
 340                              },
 341                 .nb_stages = 8,
 342                 .max_width = 2048,
 343                 .max_height = 0xFFFF,
 344         },
 345         .dspp = {
 346                 .count = 1,
 347                 .base = { 0x54000 },
 348
 349         },
 350         .intf = {
 351                 .base = { 0x00000, 0x6a800 },
 352                 .connect = {
 353                         [0] = INTF_DISABLED,
 354                         [1] = INTF_DSI,
 355                 },
 356         },
 357         .perf = {
 358                 .ab_inefficiency = 100,
 359                 .ib_inefficiency = 200,
 360                 .clk_inefficiency = 105
 361         },
 362         .max_clk = 320000000,
 363 };
 364
 365 static const struct mdp5_cfg_hw msm8x36_config = {
 366         .name = "msm8x36",
 367         .mdp = {
 368                 .count = 1,
 369                 .base = { 0x0 },
 370                 .caps = MDP_CAP_SMP |
 371                         0,
 372         },
 373         .smp = {
 374                 .mmb_count = 8,
 375                 .mmb_size = 10240,
 376                 .clients = {
 377                         [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
 378                         [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 379                 },
 380         },
 381         .ctl = {
 382                 .count = 3,
 383                 .base = { 0x01000, 0x01200, 0x01400 },
 384                 .flush_hw_mask = 0x4003ffff,
 385         },
 386         .pipe_vig = {
 387                 .count = 1,
 388                 .base = { 0x04000 },
 389                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 390                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 391                                 MDP_PIPE_CAP_DECIMATION,
 392         },
 393         .pipe_rgb = {
 394                 .count = 2,
 395                 .base = { 0x14000, 0x16000 },
 396                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 397                                 MDP_PIPE_CAP_DECIMATION,
 398         },
 399         .pipe_dma = {
 400                 .count = 1,
 401                 .base = { 0x24000 },
 402                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 403         },
 404         .lm = {
 405                 .count = 2,
 406                 .base = { 0x44000, 0x47000 },
 407                 .instances = {
 408                                 { .id = 0, .pp = 0, .dspp = 0,
 409                                   .caps = MDP_LM_CAP_DISPLAY, },
 410                                 { .id = 1, .pp = -1, .dspp = -1,
 411                                   .caps = MDP_LM_CAP_WB, },
 412                                 },
 413                 .nb_stages = 8,
 414                 .max_width = 2560,
 415                 .max_height = 0xFFFF,
 416         },
 417         .pp = {
 418                 .count = 1,
 419                 .base = { 0x70000 },
 420         },
 421         .ad = {
 422                 .count = 1,
 423                 .base = { 0x78000 },
 424         },
 425         .dspp = {
 426                 .count = 1,
 427                 .base = { 0x54000 },
 428         },
 429         .intf = {
 430                 .base = { 0x00000, 0x6a800, 0x6b000 },
 431                 .connect = {
 432                         [0] = INTF_DISABLED,
 433                         [1] = INTF_DSI,
 434                         [2] = INTF_DSI,
 435                 },
 436         },
 437         .perf = {
 438                 .ab_inefficiency = 100,
 439                 .ib_inefficiency = 200,
 440                 .clk_inefficiency = 105
 441         },
 442         .max_clk = 366670000,
 443 };
 444
 445 static const struct mdp5_cfg_hw msm8x94_config = {
 446         .name = "msm8x94",
 447         .mdp = {
 448                 .count = 1,
 449                 .caps = MDP_CAP_SMP |
 450                         MDP_CAP_SRC_SPLIT |
 451                         0,
 452         },
 453         .smp = {
 454                 .mmb_count = 44,
 455                 .mmb_size = 8192,
 456                 .clients = {
 457                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
 458                         [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
 459                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 460                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 461                         [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 462                 },
 463                 .reserved_state[0] = GENMASK(23, 0),    /* first 24 MMBs */
 464                 .reserved = {
 465                          [1] = 1,  [4] = 1,  [7] = 1, [19] = 1,
 466                         [16] = 5, [17] = 5, [18] = 5, [22] = 5,
 467                 },
 468         },
 469         .ctl = {
 470                 .count = 5,
 471                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 472                 .flush_hw_mask = 0xf0ffffff,
 473         },
 474         .pipe_vig = {
 475                 .count = 4,
 476                 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 477                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 478                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
 479                                 MDP_PIPE_CAP_DECIMATION,
 480         },
 481         .pipe_rgb = {
 482                 .count = 4,
 483                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 484                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
 485                                 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
 486         },
 487         .pipe_dma = {
 488                 .count = 2,
 489                 .base = { 0x24000, 0x26000 },
 490                 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
 491         },
 492         .lm = {
 493                 .count = 6,
 494                 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 495                 .instances = {
 496                                 { .id = 0, .pp = 0, .dspp = 0,
 497                                   .caps = MDP_LM_CAP_DISPLAY |
 498                                           MDP_LM_CAP_PAIR, },
 499                                 { .id = 1, .pp = 1, .dspp = 1,
 500                                   .caps = MDP_LM_CAP_DISPLAY, },
 501                                 { .id = 2, .pp = 2, .dspp = 2,
 502                                   .caps = MDP_LM_CAP_DISPLAY |
 503                                           MDP_LM_CAP_PAIR, },
 504                                 { .id = 3, .pp = -1, .dspp = -1,
 505                                   .caps = MDP_LM_CAP_WB, },
 506                                 { .id = 4, .pp = -1, .dspp = -1,
 507                                   .caps = MDP_LM_CAP_WB, },
 508                                 { .id = 5, .pp = 3, .dspp = 3,
 509                                   .caps = MDP_LM_CAP_DISPLAY, },
 510                              },
 511                 .nb_stages = 8,
 512                 .max_width = 2048,
 513                 .max_height = 0xFFFF,
 514         },
 515         .dspp = {
 516                 .count = 4,
 517                 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
 518
 519         },
 520         .ad = {
 521                 .count = 3,
 522                 .base = { 0x78000, 0x78800, 0x79000 },
 523         },
 524         .pp = {
 525                 .count = 4,
 526                 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
 527         },
 528         .intf = {
 529                 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
 530                 .connect = {
 531                         [0] = INTF_DISABLED,
 532                         [1] = INTF_DSI,
 533                         [2] = INTF_DSI,
 534                         [3] = INTF_HDMI,
 535                 },
 536         },
 537         .perf = {
 538                 .ab_inefficiency = 100,
 539                 .ib_inefficiency = 100,
 540                 .clk_inefficiency = 105
 541         },
 542         .max_clk = 400000000,
 543 };
 544
 545 static const struct mdp5_cfg_hw msm8x96_config = {
 546         .name = "msm8x96",
 547         .mdp = {
 548                 .count = 1,
 549                 .caps = MDP_CAP_DSC |
 550                         MDP_CAP_CDM |
 551                         MDP_CAP_SRC_SPLIT |
 552                         0,
 553         },
 554         .ctl = {
 555                 .count = 5,
 556                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 557                 .flush_hw_mask = 0xf4ffffff,
 558         },
 559         .pipe_vig = {
 560                 .count = 4,
 561                 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 562                 .caps = MDP_PIPE_CAP_HFLIP      |
 563                         MDP_PIPE_CAP_VFLIP      |
 564                         MDP_PIPE_CAP_SCALE      |
 565                         MDP_PIPE_CAP_CSC        |
 566                         MDP_PIPE_CAP_DECIMATION |
 567                         MDP_PIPE_CAP_SW_PIX_EXT |
 568                         0,
 569         },
 570         .pipe_rgb = {
 571                 .count = 4,
 572                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 573                 .caps = MDP_PIPE_CAP_HFLIP      |
 574                         MDP_PIPE_CAP_VFLIP      |
 575                         MDP_PIPE_CAP_SCALE      |
 576                         MDP_PIPE_CAP_DECIMATION |
 577                         MDP_PIPE_CAP_SW_PIX_EXT |
 578                         0,
 579         },
 580         .pipe_dma = {
 581                 .count = 2,
 582                 .base = { 0x24000, 0x26000 },
 583                 .caps = MDP_PIPE_CAP_HFLIP      |
 584                         MDP_PIPE_CAP_VFLIP      |
 585                         MDP_PIPE_CAP_SW_PIX_EXT |
 586                         0,
 587         },
 588         .pipe_cursor = {
 589                 .count = 2,
 590                 .base = { 0x34000, 0x36000 },
 591                 .caps = MDP_PIPE_CAP_HFLIP      |
 592                         MDP_PIPE_CAP_VFLIP      |
 593                         MDP_PIPE_CAP_SW_PIX_EXT |
 594                         MDP_PIPE_CAP_CURSOR     |
 595                         0,
 596         },
 597
 598         .lm = {
 599                 .count = 6,
 600                 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 601                 .instances = {
 602                                 { .id = 0, .pp = 0, .dspp = 0,
 603                                   .caps = MDP_LM_CAP_DISPLAY |
 604                                           MDP_LM_CAP_PAIR, },
 605                                 { .id = 1, .pp = 1, .dspp = 1,
 606                                   .caps = MDP_LM_CAP_DISPLAY, },
 607                                 { .id = 2, .pp = 2, .dspp = -1,
 608                                   .caps = MDP_LM_CAP_DISPLAY |
 609                                           MDP_LM_CAP_PAIR, },
 610                                 { .id = 3, .pp = -1, .dspp = -1,
 611                                   .caps = MDP_LM_CAP_WB, },
 612                                 { .id = 4, .pp = -1, .dspp = -1,
 613                                   .caps = MDP_LM_CAP_WB, },
 614                                 { .id = 5, .pp = 3, .dspp = -1,
 615                                   .caps = MDP_LM_CAP_DISPLAY, },
 616                              },
 617                 .nb_stages = 8,
 618                 .max_width = 2560,
 619                 .max_height = 0xFFFF,
 620         },
 621         .dspp = {
 622                 .count = 2,
 623                 .base = { 0x54000, 0x56000 },
 624         },
 625         .ad = {
 626                 .count = 3,
 627                 .base = { 0x78000, 0x78800, 0x79000 },
 628         },
 629         .pp = {
 630                 .count = 4,
 631                 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
 632         },
 633         .cdm = {
 634                 .count = 1,
 635                 .base = { 0x79200 },
 636         },
 637         .dsc = {
 638                 .count = 2,
 639                 .base = { 0x80000, 0x80400 },
 640         },
 641         .intf = {
 642                 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
 643                 .connect = {
 644                         [0] = INTF_DISABLED,
 645                         [1] = INTF_DSI,
 646                         [2] = INTF_DSI,
 647                         [3] = INTF_HDMI,
 648                 },
 649         },
 650         .perf = {
 651                 .ab_inefficiency = 100,
 652                 .ib_inefficiency = 200,
 653                 .clk_inefficiency = 105
 654         },
 655         .max_clk = 412500000,
 656 };
 657
 658 const struct mdp5_cfg_hw msm8x76_config = {
 659         .name = "msm8x76",
 660         .mdp = {
 661                 .count = 1,
 662                 .caps = MDP_CAP_SMP |
 663                         MDP_CAP_DSC |
 664                         MDP_CAP_SRC_SPLIT |
 665                         0,
 666         },
 667         .ctl = {
 668                 .count = 3,
 669                 .base = { 0x01000, 0x01200, 0x01400 },
 670                 .flush_hw_mask = 0xffffffff,
 671         },
 672         .smp = {
 673                 .mmb_count = 10,
 674                 .mmb_size = 10240,
 675                 .clients = {
 676                         [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
 677                         [SSPP_DMA0] = 4,
 678                         [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 679                 },
 680         },
 681         .pipe_vig = {
 682                 .count = 2,
 683                 .base = { 0x04000, 0x06000 },
 684                 .caps = MDP_PIPE_CAP_HFLIP      |
 685                         MDP_PIPE_CAP_VFLIP      |
 686                         MDP_PIPE_CAP_SCALE      |
 687                         MDP_PIPE_CAP_CSC        |
 688                         MDP_PIPE_CAP_DECIMATION |
 689                         MDP_PIPE_CAP_SW_PIX_EXT |
 690                         0,
 691         },
 692         .pipe_rgb = {
 693                 .count = 2,
 694                 .base = { 0x14000, 0x16000 },
 695                 .caps = MDP_PIPE_CAP_HFLIP      |
 696                         MDP_PIPE_CAP_VFLIP      |
 697                         MDP_PIPE_CAP_DECIMATION |
 698                         MDP_PIPE_CAP_SW_PIX_EXT |
 699                         0,
 700         },
 701         .pipe_dma = {
 702                 .count = 1,
 703                 .base = { 0x24000 },
 704                 .caps = MDP_PIPE_CAP_HFLIP      |
 705                         MDP_PIPE_CAP_VFLIP      |
 706                         MDP_PIPE_CAP_SW_PIX_EXT |
 707                         0,
 708         },
 709         .pipe_cursor = {
 710                 .count = 1,
 711                 .base = { 0x440DC },
 712                 .caps = MDP_PIPE_CAP_HFLIP      |
 713                         MDP_PIPE_CAP_VFLIP      |
 714                         MDP_PIPE_CAP_SW_PIX_EXT |
 715                         MDP_PIPE_CAP_CURSOR     |
 716                         0,
 717         },
 718         .lm = {
 719                 .count = 2,
 720                 .base = { 0x44000, 0x45000 },
 721                 .instances = {
 722                                 { .id = 0, .pp = 0, .dspp = 0,
 723                                   .caps = MDP_LM_CAP_DISPLAY, },
 724                                 { .id = 1, .pp = -1, .dspp = -1,
 725                                   .caps = MDP_LM_CAP_WB },
 726                              },
 727                 .nb_stages = 8,
 728                 .max_width = 2560,
 729                 .max_height = 0xFFFF,
 730         },
 731         .dspp = {
 732                 .count = 1,
 733                 .base = { 0x54000 },
 734
 735         },
 736         .pp = {
 737                 .count = 3,
 738                 .base = { 0x70000, 0x70800, 0x72000 },
 739         },
 740         .dsc = {
 741                 .count = 2,
 742                 .base = { 0x80000, 0x80400 },
 743         },
 744         .intf = {
 745                 .base = { 0x6a000, 0x6a800, 0x6b000 },
 746                 .connect = {
 747                         [0] = INTF_DISABLED,
 748                         [1] = INTF_DSI,
 749                         [2] = INTF_DSI,
 750                 },
 751         },
 752         .max_clk = 360000000,
 753 };
 754
 755 static const struct mdp5_cfg_hw msm8x53_config = {
 756         .name = "msm8x53",
 757         .mdp = {
 758                 .count = 1,
 759                 .caps = MDP_CAP_CDM |
 760                         MDP_CAP_SRC_SPLIT,
 761         },
 762         .ctl = {
 763                 .count = 3,
 764                 .base = { 0x01000, 0x01200, 0x01400 },
 765                 .flush_hw_mask = 0xffffffff,
 766         },
 767         .pipe_vig = {
 768                 .count = 1,
 769                 .base = { 0x04000 },
 770                 .caps = MDP_PIPE_CAP_HFLIP      |
 771                         MDP_PIPE_CAP_VFLIP      |
 772                         MDP_PIPE_CAP_SCALE      |
 773                         MDP_PIPE_CAP_CSC        |
 774                         MDP_PIPE_CAP_DECIMATION |
 775                         MDP_PIPE_CAP_SW_PIX_EXT |
 776                         0,
 777         },
 778         .pipe_rgb = {
 779                 .count = 2,
 780                 .base = { 0x14000, 0x16000 },
 781                 .caps = MDP_PIPE_CAP_HFLIP      |
 782                         MDP_PIPE_CAP_VFLIP      |
 783                         MDP_PIPE_CAP_DECIMATION |
 784                         MDP_PIPE_CAP_SW_PIX_EXT |
 785                         0,
 786         },
 787         .pipe_dma = {
 788                 .count = 1,
 789                 .base = { 0x24000 },
 790                 .caps = MDP_PIPE_CAP_HFLIP      |
 791                         MDP_PIPE_CAP_VFLIP      |
 792                         MDP_PIPE_CAP_SW_PIX_EXT |
 793                         0,
 794         },
 795         .pipe_cursor = {
 796                 .count = 1,
 797                 .base = { 0x34000 },
 798                 .caps = MDP_PIPE_CAP_HFLIP      |
 799                         MDP_PIPE_CAP_VFLIP      |
 800                         MDP_PIPE_CAP_SW_PIX_EXT |
 801                         MDP_PIPE_CAP_CURSOR     |
 802                         0,
 803         },
 804
 805         .lm = {
 806                 .count = 3,
 807                 .base = { 0x44000, 0x45000 },
 808                 .instances = {
 809                                 { .id = 0, .pp = 0, .dspp = 0,
 810                                   .caps = MDP_LM_CAP_DISPLAY |
 811                                           MDP_LM_CAP_PAIR },
 812                                 { .id = 1, .pp = 1, .dspp = -1,
 813                                   .caps = MDP_LM_CAP_DISPLAY },
 814                              },
 815                 .nb_stages = 5,
 816                 .max_width = 2048,
 817                 .max_height = 0xFFFF,
 818         },
 819         .dspp = {
 820                 .count = 1,
 821                 .base = { 0x54000 },
 822
 823         },
 824         .pp = {
 825                 .count = 2,
 826                 .base = { 0x70000, 0x70800 },
 827         },
 828         .cdm = {
 829                 .count = 1,
 830                 .base = { 0x79200 },
 831         },
 832         .intf = {
 833                 .base = { 0x6a000, 0x6a800, 0x6b000 },
 834                 .connect = {
 835                         [0] = INTF_DISABLED,
 836                         [1] = INTF_DSI,
 837                         [2] = INTF_DSI,
 838                 },
 839         },
 840         .perf = {
 841                 .ab_inefficiency = 100,
 842                 .ib_inefficiency = 200,
 843                 .clk_inefficiency = 105
 844         },
 845         .max_clk = 400000000,
 846 };
 847
 848 static const struct mdp5_cfg_hw msm8917_config = {
 849         .name = "msm8917",
 850         .mdp = {
 851                 .count = 1,
 852                 .caps = MDP_CAP_CDM,
 853         },
 854         .ctl = {
 855                 .count = 3,
 856                 .base = { 0x01000, 0x01200, 0x01400 },
 857                 .flush_hw_mask = 0xffffffff,
 858         },
 859         .pipe_vig = {
 860                 .count = 1,
 861                 .base = { 0x04000 },
 862                 .caps = MDP_PIPE_CAP_HFLIP      |
 863                         MDP_PIPE_CAP_VFLIP      |
 864                         MDP_PIPE_CAP_SCALE      |
 865                         MDP_PIPE_CAP_CSC        |
 866                         MDP_PIPE_CAP_DECIMATION |
 867                         MDP_PIPE_CAP_SW_PIX_EXT |
 868                         0,
 869         },
 870         .pipe_rgb = {
 871                 .count = 2,
 872                 .base = { 0x14000, 0x16000 },
 873                 .caps = MDP_PIPE_CAP_HFLIP      |
 874                         MDP_PIPE_CAP_VFLIP      |
 875                         MDP_PIPE_CAP_DECIMATION |
 876                         MDP_PIPE_CAP_SW_PIX_EXT |
 877                         0,
 878         },
 879         .pipe_dma = {
 880                 .count = 1,
 881                 .base = { 0x24000 },
 882                 .caps = MDP_PIPE_CAP_HFLIP      |
 883                         MDP_PIPE_CAP_VFLIP      |
 884                         MDP_PIPE_CAP_SW_PIX_EXT |
 885                         0,
 886         },
 887         .pipe_cursor = {
 888                 .count = 1,
 889                 .base = { 0x34000 },
 890                 .caps = MDP_PIPE_CAP_HFLIP      |
 891                         MDP_PIPE_CAP_VFLIP      |
 892                         MDP_PIPE_CAP_SW_PIX_EXT |
 893                         MDP_PIPE_CAP_CURSOR     |
 894                         0,
 895         },
 896
 897         .lm = {
 898                 .count = 2,
 899                 .base = { 0x44000, 0x45000 },
 900                 .instances = {
 901                                 { .id = 0, .pp = 0, .dspp = 0,
 902                                   .caps = MDP_LM_CAP_DISPLAY, },
 903                                 { .id = 1, .pp = -1, .dspp = -1,
 904                                   .caps = MDP_LM_CAP_WB },
 905                              },
 906                 .nb_stages = 8,
 907                 .max_width = 2048,
 908                 .max_height = 0xFFFF,
 909         },
 910         .dspp = {
 911                 .count = 1,
 912                 .base = { 0x54000 },
 913
 914         },
 915         .pp = {
 916                 .count = 1,
 917                 .base = { 0x70000 },
 918         },
 919         .cdm = {
 920                 .count = 1,
 921                 .base = { 0x79200 },
 922         },
 923         .intf = {
 924                 .base = { 0x6a000, 0x6a800 },
 925                 .connect = {
 926                         [0] = INTF_DISABLED,
 927                         [1] = INTF_DSI,
 928                 },
 929         },
 930         .max_clk = 320000000,
 931 };
 932
 933 static const struct mdp5_cfg_hw msm8998_config = {
 934         .name = "msm8998",
 935         .mdp = {
 936                 .count = 1,
 937                 .caps = MDP_CAP_DSC |
 938                         MDP_CAP_CDM |
 939                         MDP_CAP_SRC_SPLIT |
 940                         0,
 941         },
 942         .ctl = {
 943                 .count = 5,
 944                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
 945                 .flush_hw_mask = 0xf7ffffff,
 946         },
 947         .pipe_vig = {
 948                 .count = 4,
 949                 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
 950                 .caps = MDP_PIPE_CAP_HFLIP      |
 951                         MDP_PIPE_CAP_VFLIP      |
 952                         MDP_PIPE_CAP_SCALE      |
 953                         MDP_PIPE_CAP_CSC        |
 954                         MDP_PIPE_CAP_DECIMATION |
 955                         MDP_PIPE_CAP_SW_PIX_EXT |
 956                         0,
 957         },
 958         .pipe_rgb = {
 959                 .count = 4,
 960                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
 961                 .caps = MDP_PIPE_CAP_HFLIP      |
 962                         MDP_PIPE_CAP_VFLIP      |
 963                         MDP_PIPE_CAP_SCALE      |
 964                         MDP_PIPE_CAP_DECIMATION |
 965                         MDP_PIPE_CAP_SW_PIX_EXT |
 966                         0,
 967         },
 968         .pipe_dma = {
 969                 .count = 2, /* driver supports max of 2 currently */
 970                 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
 971                 .caps = MDP_PIPE_CAP_HFLIP      |
 972                         MDP_PIPE_CAP_VFLIP      |
 973                         MDP_PIPE_CAP_SW_PIX_EXT |
 974                         0,
 975         },
 976         .pipe_cursor = {
 977                 .count = 2,
 978                 .base = { 0x34000, 0x36000 },
 979                 .caps = MDP_PIPE_CAP_HFLIP      |
 980                         MDP_PIPE_CAP_VFLIP      |
 981                         MDP_PIPE_CAP_SW_PIX_EXT |
 982                         MDP_PIPE_CAP_CURSOR     |
 983                         0,
 984         },
 985
 986         .lm = {
 987                 .count = 6,
 988                 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
 989                 .instances = {
 990                                 { .id = 0, .pp = 0, .dspp = 0,
 991                                   .caps = MDP_LM_CAP_DISPLAY |
 992                                           MDP_LM_CAP_PAIR, },
 993                                 { .id = 1, .pp = 1, .dspp = 1,
 994                                   .caps = MDP_LM_CAP_DISPLAY, },
 995                                 { .id = 2, .pp = 2, .dspp = -1,
 996                                   .caps = MDP_LM_CAP_DISPLAY |
 997                                           MDP_LM_CAP_PAIR, },
 998                                 { .id = 3, .pp = -1, .dspp = -1,
 999                                   .caps = MDP_LM_CAP_WB, },
1000                                 { .id = 4, .pp = -1, .dspp = -1,
1001                                   .caps = MDP_LM_CAP_WB, },
1002                                 { .id = 5, .pp = 3, .dspp = -1,
1003                                   .caps = MDP_LM_CAP_DISPLAY, },
1004                              },
1005                 .nb_stages = 8,
1006                 .max_width = 2560,
1007                 .max_height = 0xFFFF,
1008         },
1009         .dspp = {
1010                 .count = 2,
1011                 .base = { 0x54000, 0x56000 },
1012         },
1013         .ad = {
1014                 .count = 3,
1015                 .base = { 0x78000, 0x78800, 0x79000 },
1016         },
1017         .pp = {
1018                 .count = 4,
1019                 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
1020         },
1021         .cdm = {
1022                 .count = 1,
1023                 .base = { 0x79200 },
1024         },
1025         .dsc = {
1026                 .count = 2,
1027                 .base = { 0x80000, 0x80400 },
1028         },
1029         .intf = {
1030                 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
1031                 .connect = {
1032                         [0] = INTF_eDP,
1033                         [1] = INTF_DSI,
1034                         [2] = INTF_DSI,
1035                         [3] = INTF_HDMI,
1036                 },
1037         },
1038         .max_clk = 412500000,
1039 };
1040
1041 static const struct mdp5_cfg_hw sdm630_config = {
1042         .name = "sdm630",
1043         .mdp = {
1044                 .count = 1,
1045                 .caps = MDP_CAP_CDM |
1046                         MDP_CAP_SRC_SPLIT |
1047                         0,
1048         },
1049         .ctl = {
1050                 .count = 5,
1051                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1052                 .flush_hw_mask = 0xf4ffffff,
1053         },
1054         .pipe_vig = {
1055                 .count = 1,
1056                 .base = { 0x04000 },
1057                 .caps = MDP_PIPE_CAP_HFLIP      |
1058                         MDP_PIPE_CAP_VFLIP      |
1059                         MDP_PIPE_CAP_SCALE      |
1060                         MDP_PIPE_CAP_CSC        |
1061                         MDP_PIPE_CAP_DECIMATION |
1062                         MDP_PIPE_CAP_SW_PIX_EXT |
1063                         0,
1064         },
1065         .pipe_rgb = {
1066                 .count = 4,
1067                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1068                 .caps = MDP_PIPE_CAP_HFLIP      |
1069                         MDP_PIPE_CAP_VFLIP      |
1070                         MDP_PIPE_CAP_SCALE      |
1071                         MDP_PIPE_CAP_DECIMATION |
1072                         MDP_PIPE_CAP_SW_PIX_EXT |
1073                         0,
1074         },
1075         .pipe_dma = {
1076                 .count = 2, /* driver supports max of 2 currently */
1077                 .base = { 0x24000, 0x26000, 0x28000 },
1078                 .caps = MDP_PIPE_CAP_HFLIP      |
1079                         MDP_PIPE_CAP_VFLIP      |
1080                         MDP_PIPE_CAP_SW_PIX_EXT |
1081                         0,
1082         },
1083         .pipe_cursor = {
1084                 .count = 1,
1085                 .base = { 0x34000 },
1086                 .caps = MDP_PIPE_CAP_HFLIP      |
1087                         MDP_PIPE_CAP_VFLIP      |
1088                         MDP_PIPE_CAP_SW_PIX_EXT |
1089                         MDP_PIPE_CAP_CURSOR     |
1090                         0,
1091         },
1092
1093         .lm = {
1094                 .count = 2,
1095                 .base = { 0x44000, 0x46000 },
1096                 .instances = {
1097                                 { .id = 0, .pp = 0, .dspp = 0,
1098                                   .caps = MDP_LM_CAP_DISPLAY |
1099                                           MDP_LM_CAP_PAIR, },
1100                                 { .id = 1, .pp = 1, .dspp = -1,
1101                                   .caps = MDP_LM_CAP_WB, },
1102                                 },
1103                 .nb_stages = 8,
1104                 .max_width = 2048,
1105                 .max_height = 0xFFFF,
1106         },
1107         .dspp = {
1108                 .count = 1,
1109                 .base = { 0x54000 },
1110         },
1111         .ad = {
1112                 .count = 2,
1113                 .base = { 0x78000, 0x78800 },
1114         },
1115         .pp = {
1116                 .count = 3,
1117                 .base = { 0x70000, 0x71000, 0x72000 },
1118         },
1119         .cdm = {
1120                 .count = 1,
1121                 .base = { 0x79200 },
1122         },
1123         .intf = {
1124                 .base = { 0x6a000, 0x6a800 },
1125                 .connect = {
1126                         [0] = INTF_DISABLED,
1127                         [1] = INTF_DSI,
1128                 },
1129         },
1130         .max_clk = 412500000,
1131 };
1132
1133 static const struct mdp5_cfg_hw sdm660_config = {
1134         .name = "sdm660",
1135         .mdp = {
1136                 .count = 1,
1137                 .caps = MDP_CAP_DSC |
1138                         MDP_CAP_CDM |
1139                         MDP_CAP_SRC_SPLIT |
1140                         0,
1141         },
1142         .ctl = {
1143                 .count = 5,
1144                 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1145                 .flush_hw_mask = 0xf4ffffff,
1146         },
1147         .pipe_vig = {
1148                 .count = 2,
1149                 .base = { 0x04000, 0x6000 },
1150                 .caps = MDP_PIPE_CAP_HFLIP      |
1151                         MDP_PIPE_CAP_VFLIP      |
1152                         MDP_PIPE_CAP_SCALE      |
1153                         MDP_PIPE_CAP_CSC        |
1154                         MDP_PIPE_CAP_DECIMATION |
1155                         MDP_PIPE_CAP_SW_PIX_EXT |
1156                         0,
1157         },
1158         .pipe_rgb = {
1159                 .count = 4,
1160                 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1161                 .caps = MDP_PIPE_CAP_HFLIP      |
1162                         MDP_PIPE_CAP_VFLIP      |
1163                         MDP_PIPE_CAP_SCALE      |
1164                         MDP_PIPE_CAP_DECIMATION |
1165                         MDP_PIPE_CAP_SW_PIX_EXT |
1166                         0,
1167         },
1168         .pipe_dma = {
1169                 .count = 2, /* driver supports max of 2 currently */
1170                 .base = { 0x24000, 0x26000, 0x28000 },
1171                 .caps = MDP_PIPE_CAP_HFLIP      |
1172                         MDP_PIPE_CAP_VFLIP      |
1173                         MDP_PIPE_CAP_SW_PIX_EXT |
1174                         0,
1175         },
1176         .pipe_cursor = {
1177                 .count = 1,
1178                 .base = { 0x34000 },
1179                 .caps = MDP_PIPE_CAP_HFLIP      |
1180                         MDP_PIPE_CAP_VFLIP      |
1181                         MDP_PIPE_CAP_SW_PIX_EXT |
1182                         MDP_PIPE_CAP_CURSOR     |
1183                         0,
1184         },
1185
1186         .lm = {
1187                 .count = 4,
1188                 .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1189                 .instances = {
1190                                 { .id = 0, .pp = 0, .dspp = 0,
1191                                   .caps = MDP_LM_CAP_DISPLAY |
1192                                           MDP_LM_CAP_PAIR, },
1193                                 { .id = 1, .pp = 1, .dspp = 1,
1194                                   .caps = MDP_LM_CAP_DISPLAY, },
1195                                 { .id = 2, .pp = 2, .dspp = -1,
1196                                   .caps = MDP_LM_CAP_DISPLAY |
1197                                           MDP_LM_CAP_PAIR, },
1198                                 { .id = 3, .pp = 3, .dspp = -1,
1199                                   .caps = MDP_LM_CAP_WB, },
1200                                 },
1201                 .nb_stages = 8,
1202                 .max_width = 2560,
1203                 .max_height = 0xFFFF,
1204         },
1205         .dspp = {
1206                 .count = 2,
1207                 .base = { 0x54000, 0x56000 },
1208         },
1209         .ad = {
1210                 .count = 2,
1211                 .base = { 0x78000, 0x78800 },
1212         },
1213         .pp = {
1214                 .count = 5,
1215                 .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1216         },
1217         .cdm = {
1218                 .count = 1,
1219                 .base = { 0x79200 },
1220         },
1221         .dsc = {
1222                 .count = 2,
1223                 .base = { 0x80000, 0x80400 },
1224         },
1225         .intf = {
1226                 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1227                 .connect = {
1228                         [0] = INTF_DISABLED,
1229                         [1] = INTF_DSI,
1230                         [2] = INTF_DSI,
1231                         [3] = INTF_HDMI,
1232                 },
1233         },
1234         .max_clk = 412500000,
1235 };
1236
1237 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1238         { .revision = 0, .config = { .hw = &msm8x74v1_config } },
1239         { .revision = 2, .config = { .hw = &msm8x74v2_config } },
1240         { .revision = 3, .config = { .hw = &apq8084_config } },
1241         { .revision = 6, .config = { .hw = &msm8x16_config } },
1242         { .revision = 8, .config = { .hw = &msm8x36_config } },
1243         { .revision = 9, .config = { .hw = &msm8x94_config } },
1244         { .revision = 7, .config = { .hw = &msm8x96_config } },
1245         { .revision = 11, .config = { .hw = &msm8x76_config } },
1246         { .revision = 15, .config = { .hw = &msm8917_config } },
1247         { .revision = 16, .config = { .hw = &msm8x53_config } },
1248 };
1249
1250 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1251         { .revision = 0, .config = { .hw = &msm8998_config } },
1252         { .revision = 2, .config = { .hw = &sdm660_config } },
1253         { .revision = 3, .config = { .hw = &sdm630_config } },
1254 };
1255
1256 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
1257
1258 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1259 {
1260         return cfg_handler->config.hw;
1261 }
1262
1263 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1264 {
1265         return &cfg_handler->config;
1266 }
1267
1268 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1269 {
1270         return cfg_handler->revision;
1271 }
1272
1273 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
1274 {
1275         kfree(cfg_handler);
1276 }
1277
1278 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1279                 uint32_t major, uint32_t minor)
1280 {
1281         struct drm_device *dev = mdp5_kms->dev;
1282         struct platform_device *pdev = to_platform_device(dev->dev);
1283         struct mdp5_cfg_handler *cfg_handler;
1284         const struct mdp5_cfg_handler *cfg_handlers;
1285         struct mdp5_cfg_platform *pconfig;
1286         int i, ret = 0, num_handlers;
1287
1288         cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
1289         if (unlikely(!cfg_handler)) {
1290                 ret = -ENOMEM;
1291                 goto fail;
1292         }
1293
1294         switch (major) {
1295         case 1:
1296                 cfg_handlers = cfg_handlers_v1;
1297                 num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1298                 break;
1299         case 3:
1300                 cfg_handlers = cfg_handlers_v3;
1301                 num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1302                 break;
1303         default:
1304                 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1305                                 major, minor);
1306                 ret = -ENXIO;
1307                 goto fail;
1308         }
1309
1310         /* only after mdp5_cfg global pointer's init can we access the hw */
1311         for (i = 0; i < num_handlers; i++) {
1312                 if (cfg_handlers[i].revision != minor)
1313                         continue;
1314                 mdp5_cfg = cfg_handlers[i].config.hw;
1315
1316                 break;
1317         }
1318         if (unlikely(!mdp5_cfg)) {
1319                 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1320                                 major, minor);
1321                 ret = -ENXIO;
1322                 goto fail;
1323         }
1324
1325         cfg_handler->revision = minor;
1326         cfg_handler->config.hw = mdp5_cfg;
1327
1328         pconfig = mdp5_get_config(pdev);
1329         memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
1330
1331         DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1332
1333         return cfg_handler;
1334
1335 fail:
1336         if (cfg_handler)
1337                 mdp5_cfg_destroy(cfg_handler);
1338
1339         return ERR_PTR(ret);
1340 }
1341
1342 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
1343 {
1344         static struct mdp5_cfg_platform config = {};
1345
1346         config.iommu = iommu_domain_alloc(&platform_bus_type);
1347
1348         return &config;
1349 }